Design Of Phase Frequency Detector Research Articles

Optimisation and Performance Computation of a Phase Frequency Detector Module for IoT Devices

The Internet of Things (IoT) is pivotal in transforming the way we live and interact with our surroundings. To cope with the advancement in technologies, it is vital to acquire accuracy with the speed. A phase frequency detector (PFD) is a critical device to regulate and provide accurate frequency in IoT devices. Designing a PFD poses challenges in achieving precise phase detection, minimising dead zones, optimising power consumption, and ensuring robust performance across various operational frequencies, necessitating complex engineering and innovative solutions. This study delves into optimising a PFD circuit, designed using 90 nm standard CMOS technology, aiming to achieve superior operational frequencies. An efficient and high-frequency PFD design is crafted and analysed using cadence virtuoso. The study focused on investigating the impact of optimising PFD design. With the optimised PFD, an operational frequency of 5 GHz has been achieved, along with a power consumption of only 29 µW. The dead zone of the PFD was only 25 ps.

A High Speed Phase Detection Circuit with No Dead Zone Suitable for Minimal Jitter and Low Power Applications

A novel phase frequency detector design is introduced in this study, which removes dead and blind zone issues by eliminating reset path, therefore accelerating the acquisition process. High speed, low power and minimal phase noise are all characteristics of the proposed circuit. The circuit is designed in the Cadence Virtuoso environment and is implemented in CMOS GPDK 180 nm library using a 1.8 V supply voltage. Post-layout simulations have been conducted to ensure that the findings are accurate. The circuit’s robustness is tested over process, voltage and temperature fluctuations. The suggested PFD achieves a phase noise of [Formula: see text][Formula: see text]dBc/Hz, which is significantly lower than other published circuits. This PFD dissipates 10.25[Formula: see text][Formula: see text]W of power at its maximum operating frequency of 10 GHz. The PFD encompasses an area of 275[Formula: see text][Formula: see text]m2. The proposed PFD outperforms other PFD circuits in the literature, making it ideal for applications requiring minimal jitter, low power, etc.

A New Blind Zone Free PFD in Fractional-N PLL for Bluetooth Applications

This paper presents a new Phase Frequency Detector (PFD) used in the Fractional-N synthesizer PLL for the Bluetooth range frequencies using TSPC based D-FF. The PFD is designed by using 16 transistors. The operating frequency of the PFD can be modelled in between 2.2GHz-3.8GHz with an input reference frequency is applied of about 50MHz. The design of PFD is done by using GPDK 45nm CMOS technology on SPECTRE simulator with 1.8 V supply voltage. The designed PFD is having maximum operating range and free from blind zone. The results reported in this paper are compared and focused on the blind zone and minimum jitter contribution. The designed PFD consumes least power, minimum number of transistors and minimum jitter contributed by the transistors as compared with the reset free based PFD.

Design of phase frequency detector with improved output characteristics operating in the range of 1.25 MHz–3.8 GHz

In this paper, a CMOS based precharged phase frequency detector (PPFD) with improved output characteristic for phase locked loop (PLL) has been proposed and analyzed. The proposed PFD minimizes the reset time to improve the output characteristics and works upto the frequency of 1.25 MHz–3.8 GHz. In addition, it has an advantage of precharged PFD which has low power consumption capability i.e., 285.77 $$\upmu$$ w. The design is based on standard 0.18 $$\upmu$$ m CMOS process technology with the supply voltage of 1.8 V and achieves phase noise of $$-135.45$$ dBc/Hz at 1 MHz offset. Further, the proposed design has minimized the Blind zone to 63 ps and has completely eliminated the dead zone in the phase characteristics. This is required for low noise phase locked loop (PLL) application.

Integer‐ N charge pump phase locked loop for 2.4 GHz application with a novel design of phase frequency detector

In this article, a novel design is presented, for an Integer- N charge pump phase locked loop (PLL). The design is with a resetless phase frequency detector, and with the differential design of charge pump. The voltage-controlled oscillator is of current starved type. The proposed PLL is not having any blind zone and is having near-zero dead zone. When compared to the conventional design, the current mismatch in the charge pump is reduced by 3.21%, and the lock time of the PLL is reduced by 79%. The PLL is intended for 2.4 GHz application, and the obtained lock time is 1.7 μs. The implementation is done with the three-stage ring oscillator, with divider of modulus as 24, in 180 nm TSMC technology. At 1.8 V supply voltage, the circuit consumes 9.72 mW of power.

Analysis and design of ultra-low-voltage low-power rail-to-rail VCO-based comparator in subthreshold region

In this paper, analysis and design of an ultra-low-voltage low-power voltage controlled oscillator (VCO)-based comparator operating in subthreshold region is presented. It is composed of a pseudo differential VCO and a phase-frequency detector (PFD). An analytical design approach is developed resulting in closed-form expressions for important properties of the comparators such as resolution, comparison time, comparison energy and input-referred noise. Using the developed expressions, the design of phase-frequency detector (PFD) and its limitations is fully addressed and the possibility of using a signal premapping strategy allowing for rail-to-rail operation is investigated. To comprehensively verify the operation of the proposed comparator, it has been adopted in an 8 bits, 13 kS/s SAR ADC suitable for biomedical applications. Using a 0.18 μm standard CMOS process under a 0.5-V supply voltage, the total power consumption is about 153 nW. The simulated SNDR and SFDR are 49.15 dB and 57.76 dB, respectively. The DNL is +0.12/−0.13 LSB and the INL is +0.24/−0.51 LSB.

Design of phase frequency detector with a novel delay unit

Design of phase frequency detector with a novel delay unit

A faster phase frequency detector using transmission gate–based latch for the reduced response time of the PLL

SummaryIn this paper, we present a new design of phase frequency detector (PFD) without reset, such that the blind zone and dead zone issues in the phase locked loop are annihilated. The PFD is designed using transmission gate–based latches, which produce UP and DOWN pulses only when there is a distinct phase difference between the reference and divided frequencies. Thus, the continuous pulses that get produced by the conventional NAND gate–based latches are avoided, leading to reduced power consumption of the PFD. The charge pump makes use of an op‐amp used as a buffer, to reduce the current mismatch. The loop filter used is of second order, and the voltage‐controlled oscillator is of conventional current–starved type. The divider makes use of true single‐phase clock latches. It was found that the phase locked loop with new design of PFD, compared with the conventional design, consumes 27% lesser power, and the lock time is decreased by 79%. In addition, it was found that the control voltage swing is reduced by 71%, which leads to much lesser spur content at the output of the voltage‐controlled oscillator.

Design of a CMOS PFD-CP module for a PLL

This paper introduces a modified design of Phase frequency detector (PFD) with reduced dead zone and improved charge pump (CP) with reduced current mismatch for a Phase Locked Loop (PLL). Three modified PFD circuits are proposed, designed, simulated, and the results are analyzed considering dead zone as a constraint. Design of pass transistor logic network plays a part in the diminution of the dead zone. Further, an improved design of CP is proposed to reduce current mismatch. It is achieved by placing the single ended differential amplifier in current–voltage feedback configuration which offers high output impedance. Simulations are performed using T-SPICE, implemented in IBM 0.13 µm technology under 1.3 V power supply. Results show that the modified PFD design has a dead zone of 0.3 ns and the current mismatch decrements to 0.1 µA in an improved CP design.

Analysis and Design of Phase Frequency Detector using Current Mode Logic

Analysis and Design of Phase Frequency Detector using Current Mode Logic

Low Power Phase Locked Loop Frequency Synthesizer for 2.4 GHz Band Zigbee

Problem statement: Wireless communication systems are required for many applications. There are different standards for these systems. IEEE 802.15.4 defines the communication system standard for zigbee. This study discussed designing one of the blocks of zigbee transceiver which is the Phase Locked Loop (PLL). A major target for any communication systems is saving battery power, especially for zigbee as it is meant to be a low cost communication system. Phase Locked Loop is responsible on carrier frequency selection in a communication system. It is the most power consumer block in the transceiver as well. The objective of this study was designing a low power fully integrated integer-N PLL frequency synthesizer targeting the 2.4 GHz band IEEE 802.15.4 Std zigbee. Approach: Minimizing total power consumption of PLL was achieved by introducing a novel design of Phase Frequency Detector (PFD) and modifying the rest of the PLL blocks. The proposed PFD used only 12 transistors and it preserved the main characteristics of the conventional PFD with a simple architecture. The Charge Pump (CP) was single-ended source switch to save power and minimize mismatches. The Voltage Controlled Oscillator (VCO) spans from 4.737-4.977 GHz band using LC resonator. The VCO worked at double the frequency band to avoid local oscillator leakage and feed through. The integer N divider used a 15/16 dual modulus. Results: The proposed PLL was designed using Silterra 0.18 um CMOS process. It consumed 3.2 mW with 1.8 voltage supply. Phase noise is-113.4 dBc Hz-1 at 1 MHz. The proposed PFD works up to 2.5 GHz with free dead zone. The Charge Pump (CP) works with 20 uA, lock-in time is 27 us and total die area is 1×2 mm. All results were taken from extracted layout simulations. Conclusion: The results of this study indicated that a PLL can work with less power consumption and save the transceiver battery. The proposed PFD was suitable for high speed applications.

A Modular Phase-Frequency Detector Design with �2n? Linear Range of Operation

To extend the linearity range of the phase-frequency detector/charge pump (PFD/CP) circuit, a modular design for a novel PFD architecture is proposed. The new circuit yields a modular extension range of –2Nπ to 2Nπ, where N is an integer representing the order of the PFD/CP extension. The efficacy of the new PFD/CP is demonstrated by the improved frequency acquisition time obtained via closed-loop simulation. Hence, the developed architecture is a good candidate for phase-locked loops requiring the use of PFD/CP with a broad linear range of operation.