Phase And Frequency Detector Research Articles

Low power 10T phase and frequency detector for high frequency phase locked loop

AbstractThe high‐frequency circuits used in communication systems significantly depend on the functioning of the Phase‐Locked Loop (PLL). The power consumption is traded with the performance in the high‐frequency PLL. The proposed robust Phase and Frequency Detector (PFD) has multiple benefits of low‐power and reliable functioning at high frequency. The PFD highly contributes to the stable performance of the PLL, and this work proposes a 10T PFD for low‐power. The proposed PFD employs Gate Diffusion Input (GDI) logic based D‐flip flop and the pass transistor logic in the reset path to reduce power consumption. The PFD uses only 10 transistors, enabling a faster reset path and consuming less power at high frequencies. The 10T PFD was designed using 90 nm CMOS PDKs and simulated using CADENCE Specter for functional verification and performance analysis. The 10T PFD achieved a reset time of 61.4 ps at 3 GHz alongside a power consumption of 189.2 nW. Also, the overall power consumption of PLL using the proposed PFD at 3 GHz was demonstrating the effectiveness of 10T PFD over other conventional PFDs.

A Wideband 4-Phase Phase-Locked Loop for Single-Slope Ramp ADC in SCA ASIC

Waveform digitization is an important research direction in high-energy physics experiments. Compared to analog-to-digital converter (ADC) solutions, switched capacitor arrays (SCAs) have the advantages of high sampling rate, low power consumption, and easy multichannel integration. However, the dead time of SCA is a limitation for high-hit-rate applications. To reduce the quantization time contributed by the on-chip Wilkinson ADC, a strategy of a high-speed less-bit coarse counter combined with multi-phase clock locking can be adopted. In this case, a high-precision PLL with multiple phases is needed. This paper presents the design and test of a 4-phase PLL for a 12-bit single-slope ramp ADC employed in our SCA ASIC in research. It contains a linear phase and frequency detector (PFD), a current steering charge pump (CP), a second order loop filter, a wideband voltage-controlled oscillator (VCO), VCO calibration, a band-locked detector, and a frequency divider (FD). The frequency tuning range is achieved from 1 GHz to 2 GHz. In addition, another output clock, supporting division by 1, 2, 4, or 8, can be used as a serial readout clock. The PLL has been designed and fabricated in 0.13 μm CMOS technology. The 1024-cycle jitter is approximately 0.013 periods. The area of the PLL core is 0.077 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The power consumption of the PLL core is 14.5 mW.

A 5.91–8.94GHz phase‐locked loop in 65 nm CMOS for 5G applications

AbstractA low‐noise fully‐integrated charge‐pump phase‐locked loop (CPPLL) for 5G applications is presented in this letter. The PLL architecture includes a phase and frequency detector (PFD), a charge pump (CP), a low‐pass filter (LPF), a voltage‐controlled oscillator (VCO), and a programmable divider. To achieve low phase noise, class‐C VCO, TSPC logic, and other methods are employed in the PLL circuit design. Fabricated in 65 nm technology, the PLL measures a tuning range of 5.91–8.94 GHz. The minimum and maximum measured phase noise are −125 dBc/Hz and −116.6 dBc/Hz @1 MHz. The size of CPPLL core area is 0.8 mm by 0.95 mm without the pads while having a 50‐mW power consumption.

A 2.4 GHz integer-N frequency synthesizer for ZigBee applications

This paper presents a fully integrated Integer-N Phase Locked Loop (INPLL) for ZigBee applications. In this paper the effects of delay in the reset path of Phase and Frequency Detector (PFD) and current gain mismatch in the Charge Pump (CP) on the spectral purity of the Local Oscillator (LO) signal of INPLL is studied theoretically. Then a linearization technique is introduced for a conventional CP to minimize the current gain mismatch and also a modified PFD is presented to achieve a fully symmetrical structure in order to simplify physical verification. The proposed linearization technique of the CP leads to minimize the current gain mismatch from 8.5 to 2.5 µA and the linearity range enhanced 7 times more than conventional structure. Finally, an INPLL is implemented in 0.18 µm CMOS standard to use in ZigBee applications. Reference spurs of the LO signal of the designed INPLL are suppressed more than 8 dBc/Hz when the linearization technique is incorporating in the INPLL. The power consumption of the whole INPLL with a 1.8 V DC supply is 9.15 mW.

Design of PLL based Frequency Synthesizer using Harmonic Extraction Techniques

Objectives: This paper introduces a design of PLL based Frequency Synthesizer using Harmonic Extraction Technique. Different parameters of PLL and Frequency Synthesizer are analyzed. Methods: The Harmonic Extraction technique includes VCO with common gate amplifier, cascode amplifier and Differential output Buffer. The LC tank circuit used in this paper is a current mirror VCO. In order to extract the harmonics, Band pass filter is used. After that dual loop PLL is introduced which consists of proportional path and integral path. Furthermore Phase and Frequency Detector (PFD) is implemented using Gate Diffusion input (GDI) method. The proposed design is implemented using 90nm Cadence Virtuoso Analog Design Environment tool. Findings: As a result of using this technique, VCO achieves tuning range of 23.17% and phase noise of -85dBc/Hz @1MHz and -93dBc/Hz@10MHz with a small power dissipation of 50uW and Frequency Synthesizer achieves power dissipation of 4.8mW. Improvements/Applications: The performance analysis has shown that the designed Frequency Synthesizer has better tuning range, low power and low Phase noise which makes it suitable to operate in high frequency applications.

Effects of Radio Front-end PLL Phase Noise on GNSS Baseband Correlation

This article presents a study of Global Navigation Satellite System (GNSS) receiver correlation performance in the presence of phase noise (PN) originating from the radio front-end's phase-locked loop (PLL). Various constituent PLL sub-blocks, such as the reference oscillator (RO), phase and frequency detector (PFD), voltage controlled oscillator (VCO), loop filter and frequency dividers contribute to the overall PN of the PLL. The PLL phase noise modeling is covered in detail. Correlation performance of GNSS baseband tracking loops is then calculated as a function of several PLL design parameters, such as the VCO thermal PN, loop filter bandwidth (BW), frequency division ratio (FDR), and the receiver correlator's pre-detection integration times (PIT). The effects of these parameters on the signal to noise ratio (SNR) of the correlation product are described and simulated. Based on the results of these simulations, we present guidelines for radio front-end PLL circuit design in order to maintain a minimum baseband correlation performance within the GNSS receiver. Copyright © 2014 Institute of Navigation.

A digital optical phase-locked loop for diode lasers based on field programmable gate array

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382∕MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat note line width below 1 Hz, residual mean-square phase error of 0.14 rad(2) and transition time of 100 μs under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.

An 8 GHz silicon bipolar clock-recovery and data-regenerator IC

This contribution shows that a monolithic integrated silicon bipolar circuit can provide phase and frequency locked loop (PFLL) based clock recovery and data regeneration up to 8Gb/s. Moreover, phase and frequency detector (PFD) operation up to 15Gb/s (with an external VCO) is demonstrated. Owing to the wide tuning range of the quadrature VCO, the circuit lends itself to operation over a wide range of bit rates. Other applications of the quadrature VCO, e.g. as a synthesizer, are possible. As shown by circuit simulations, the operating frequency can be extended beyond 1OGHz, if a small unbalance between both ring oscillator stages is eliminated by minor design changes. >