Peripheral Component Interface Research Articles

Automated Test System for Test and Evaluation of C-Band Transmitter Packages for Geosat Spacecrafts

The aim of this paper is to develop an Automated Test System (ATS) for the Test and Evaluation of C-Band Transmitter packages for GEOSAT Space crafts using Virtual Instrumentation. Efficiency, coverage, quality and accuracy for the test and evaluation of Device Under Test (DUT) can be increased by Automated Testing. Minimizing the errors anticipated with manual intervention. Automated Test System using Virtual instrumentation (VI) combines rapid development software and modular, flexible hardware to create user-defined test systems. Here Modular PXI (Peripheral component interface Extensions for Instrumentation) instruments from National Instruments are used with NI-LabVIEW software for realizing the ATS. For characterizing the C-Band Transmitter, Spectrum analyzer & Digital Multimeter (DMM) is configured in PXI form-factor and the Power supply is controlled through GPIB (General Purpose Interface Bus) bus. The complete software is developed using NI LabVIEW which takes care of configuring the test condition and analyzing the DUT performance. The user friendly GUI well takes care of user interaction to the ATS.

ATCA-Based Hardware for Control and Data Acquisition on Nuclear Fusion Fast Control Plant Systems

In contemporary control and data acquisition systems for Nuclear Fusion devices, the galloping need for high channel density and real-time multi-input-multi-output (MIMO) controller support gave rise to a new generation of hardware architecture based on the Advanced Telecommunications Computing Architecture (ATCA) specification. In addition, ATCA successfully delivered solutions in other sensitive issues like redundancy, power dissipation and available area for components and routing. Experience has shown, however, that such hardware devices can require a lengthy development. The ATCA specification allows for custom solutions in areas of the interfaces which can be used to define extensions of the standard for instrumentation needs. The"'xTCA for Physics" workgroups are currently developing ATCA and MicroTCA extensions for Physics instrumentation applications. These ex tensions will define interfaces in customizable areas which will support functionalities required by the instrumentation and facilitate hardware development and its posterior operation in a Fusion control plant environment-most notably, dedicated timing and input-output (IO) port assignment on the Rear Transition Module (RTM). The prototype hereby presented is a Peripheral Component Interface (PCIe) switch Advanced Mezzanine Card (AMC) carrier blade. The device serves as a hub, as to control and handle I/O data from its parent nodes existing within the same ATCA shelf through its fabric channels in dual-star topology. Parent node blades, under development, are equally linked through ATCA's agnostic fabric in full-mesh topology, as to attain system MIMO functionality from all I/O endpoints. The switch blade carries up to four AMC modules, adding up to modularity and versatility. This allows for a much more independent and speedier hardware development, as dedicated AMC modules, such as data processing and storage devices, can be simultaneously developed. Commercial off-the-shelf (COTS) AMC products are readily available and may also be immediately integrated in the system.

DSP/FPGA-based Controller Architecture for Flexible Joint Robot with Enhanced Impedance Performance

Some practical issues associated with enhancing the Cartesian impedance performance of flexible joint manipulator are investigated. A digital signal processing/field programmable gate array (DSP/FPGA) structure is proposed to realize the singular perturbation based impedance controller. To increase the bandwidth of torque control and minimize the joint torque ripple, boundary layer system and field-oriented control (FOC) are fully implemented in a FPGA of each joint. The kernel of the hardware system is a peripheral component interface (PCI)-based high speed floating-point DSP for the Cartesian level control, and FPGA for high speed (200 us cycle time) multipoint low-voltage differential signaling (M-LVDS) serial data bus communication between robot Cartesian level and joint level. Experimental results with a four-degree-of-freedom flexible-joint manipulator under constrained-motion task, demonstrate that the controller architecture can enhance the robot impedance performance effectively.

BladeCenter processor blades, I/O expansion adapters, and units

This paper describes the electrical architecture and design of the IBM eServer™ BladeCenter® processor blades, expansion blades, and input/output (I/O) expansion adapters and units. The processor blades are independent, general-purpose servers containing processors, chipsets, main memory, hard drives, network interface controllers, power input control circuitry, and local systems management. The blade architecture is robust and flexible enough to enable the design of general-purpose Intel-processor-based two-way and four-way blades, IBM POWER™-processor-based blades, blades based on AMD Opteron™ processors, and common expansion blades. In addition, the processor blades, expansion adapters, and units use a serialized-deserialized (SerDes) interface for the internal I/O fabrics, thus giving blades the flexibility to support virtually any I/O protocol that supports SerDes. Support for I/O fabrics beyond the base Gigabit Ethernet is accomplished via optional I/O expansion adapters for Fibre Channel, Myricom Myrinet®, InfiniBand®, or additional Gigabit Ethernet. Additional storage or peripheral component interface capability can be added to the processor blades via expansion blades.

End-to-end performance of 10-gigabit ethernet on commodity systems

Apart form the success in local-area networks (LANs) and system-area networks and anticipated success in metropolitan and wide area networks (MANs and WANs), Ethernet continues to evolve to meet the increasing demands of packet-switched networks. Although the recently ratified 10-Gigabit Ethernet standard differs from earlier Ethernet standards, primarily in that 10GbE operates only over fiber and only in full-duplex mode, the differences are largely superficial. More importantly, l0GbE does not make obsolete current investments in network infrastructure. The 10GbE standard ensures interoperability not only with existing Ethernet but also with other networking technologies such as Sonet, thus paving the way for Ethernets expanded use in MANs and WANs. The world's first host-based 10GbE adapter, officially known as the Intel PRO/10GbE LR server adapter, introduces the benefits of l0GbE connectivity into LAN and system-area network environments, thereby accommodating the growing number of large-scale cluster systems and bandwidth-intensive applications, such as imaging and data mirroring. The 10GbE controller is optimized for servers that use the I/O bus backplanes of the peripheral component interface (PCI) and its higher speed extension, PCI-X.

A FADC system based on CompactPCI for DCBA

A flash analog to digital converter (FADC) board of low cost and power saving has been developed based on Compact Peripheral Component Interface (CompactPCI) for Drift Chamber Beta-ray Analyzer (DCBA), which is an experiment to study double-beta decay. This board has been designed and constructed with 8 channels, each of which has an 8-bit 100 MHz FADC chip and a double-buffered memory. The design philosophy using recent semiconductor technology is described together with the performance of the FADC board.

Focus on Data Acquisition

Focus on Data Acquisition

A parallel embedded-processor architecture for ATM reassembly

The asynchronous transfer mode (ATM) reassembly algorithm for adaptation layer five is broken down into concurrent tasks for efficient VLSI implementation. VHDL and HSPICE simulations show that the proposed reassembly chip architecture will function with ATM line rates up to 700 Mb/s. The architecture is based upon three embedded lightweight processors, a variety of supporting circuitry, and a peripheral component interface (PCI) bus host interface. An important architectural feature is the use of a paged memory management system for the reconstruction of variable length messages.

STiNG

"STiNG" is a Cache Coherent Non-Uniform Memory Access (CC-NUMA) Multiprocessor designed and built by Sequent Computer Systems, Inc. It combines four processor Symmetric Multi-processor (SMP) nodes (called Quads), using a Scalable Coherent Interface (SCI) based coherent interconnect. The Quads are based on the Intel P6 processor and the external bus it defines. In addition to 4 P6 processors, each Quad may contain up to 4 GBytes of system memory, 2 Peripheral Component Interface (PCI) busses for I/O, and a Lynx board. The Lynx board provides the datapath to the SCI-based interconnect and ensures system-wide cache coherency. STiNG is one of the first commercial CC-NUMA systems to be built. This paper describes the motivation for building STiNG as well as its architecture and implementation. In addition, performance analysis is provided for On-Line Transaction Processing (OLTP) and Decision Support System (DSS) workloads. Finally, the status of the current implementation is reviewed.