Performance Of Pentacene Thin-film Transistors Research Articles

Role of Fluoride Doping in Low-Temperature Combustion-Synthesized ZrOx Dielectric Films.

Zirconium oxide (ZrOx) is an attractive metal oxide dielectric material for low-voltage, optically transparent, and mechanically flexible electronic applications due to the high dielectric constant (κ ∼ 14-30), negligible visible light absorption, and, as a thin film, good mechanical flexibility. In this contribution, we explore the effect of fluoride doping on structure-property-function relationships in low-temperature solution-processed amorphous ZrOx. Fluoride-doped zirconium oxide (F:ZrOx) films with a fluoride content between 1.7 and 3.2 in atomic (at) % were synthesized by a combustion synthesis procedure. Irrespective of the fluoride content, grazing incidence X-ray diffraction, atomic-force microscopy, and UV-vis spectroscopy data indicate that all F:ZrOx films are amorphous, atomically smooth, and transparent in visible light. Impedance spectroscopy measurements reveal that unlike solution-processed fluoride-doped aluminum oxide (F:AlOx), fluoride doping minimally affects the frequency-dependent capacitance instability of solution-processed F:ZrOx films. This result can be rationalized by the relatively weak Zr-F versus Zr-O bonds and the large ionic radius of Zr+4, as corroborated by EXAFS analysis and MD simulations. Nevertheless, the performance of pentacene thin-film transistors (TFTs) with F:ZrOx gate dielectrics indicates that fluoride incorporation reduces I-V hysteresis in the transfer curves and enhances bias stress stability versus TFTs fabricated with analogous, but undoped ZrOx films as gate dielectrics, due to reduced trap density.

Dimethyl Ketone Treatment of Cross-linked Poly(4-vinylphenol) Insulators for Pentacene Thin-film Transistors

We demonstrate a dimethyl ketone treatment to produce a hydrophobic surface of cross-linked poly(4-vinylphenol) (c-PVP) insulators for pentacene thin-film transistors (TFTs). Through water contact angle measurements, the dimethyl ketone treatment is proven to significantly increase the surface hydrophobicity of c-PVP films. The results of X-ray diffraction analyses indicate that the dimethyl ketone-treated c-PVP insulator contributes to enhancing the crystallinity of pentacene films and reducing the density of lamellar grains and bulk phase crystallites in pentacene films. In addition, the growth of lamellar grains is elucidated by examining the initial growths of the pentacene films on the c-PVP films with different surface energies. Consequently, the enhancement in the performance of pentacene TFTs is achieved by incorporating the dimethyl ketone-treated c-PVP films as gate insulators.

Charge transport and morphology of pentacene films confined in nano-patterned region

The transport and morphology of macroscopic organic transistors have been thoroughly explained. However, the relationship between charge transport and the morphology of organic semiconductors in nano-confined regions is not well understood, which is required to design high-performance nano-electronics. Therefore, in this study, the electrical performance of pentacene thin-film transistors (TFTs) fabricated on nano-scale confined geometries was compared with that of other TFT systems fabricated on micro-scale confined or flat dielectrics. The results showed that the photoresist (PR) reliefs patterned onto silicon dioxide (SiO2) dielectrics could control the growth mode of pentacene in the confined regions. As the line spacing between the PR patterns decreased to below the average size of pentacene normally grown on SiO2 dielectrics (∼1.7 μm), field-effect mobility (μFET) of pentacene TFTs improved considerably. Specifically, the μFET values for the 250 nm patterned dielectric system were as high as 0.33 cm2 V−1 s−1, which was greater than those of the wider-patterned PR or flat dielectric systems (⩽ 0.15 cm2 V−1 s−1). These findings were related to the enhancement of charge-carrier transport owing to the anisotropic π-conjugated crystals nucleated from the nano-confined edges, providing important information that can be used in the design of high-performance nano-scale organic electronics. We have analyzed the effect of the morphology of the pentacene films confined in the micro- and nano-scale relief patterns on the charge transport. As the patterned space region for confining the growth of organic semiconductors decreased to below the average grain size (∼ 1.7 μm), the field-effect mobility increased. Because the molecular ordering is influenced by the pattern’s confining effect on pentacene film growth. Our results will provide an approach that can be used to further increase the charge transport mobility of polycrystalline organic semiconductors by increasing the molecular ordering in the direction of charge transport. While the effect of morphology on an organic semiconductor's charge transport is generally well understood, less is known about the effect when the material is confined, despite this being a highly relevant situation for nanoelectronic devices. A South Korea-based research team led by Tae-Woo Lee has now determined how the performance of a thin-film transistor is affected when its pentacene semiconductor is confined in a nanoscale pattern rather than a microscale pattern or a flat dielectric system. The researchers observed higher field-effect mobility in the nanopattern-based device compared to the other configurations. The enhancement arises as a result of the nanopattern's effect on the arrangement of the pentacene molecules in the thin film — favouring their ordering in the direction of the charge transport, which in turn improves the device's performance. This understanding of the effect of confinement on charge mobility may contribute to the engineering of more efficient organic semiconductors.

Effect of the phenyl ring orientation in the polystyrene buffer layer on the performance of pentacene thin-film transistors

The phenyl groups of polystyrene (PS) thin films untreated and thermally treated at 80 and 120 °C assume tilt angles of 27°, 39° and 62°, respectively. The PS films were inserted between SiO 2 and organic semiconductors as buffer layers for organic thin-film transistors (OTFTs). The results showed that a flat orientation of phenyl ring at the surface of the PS films optimized the surface energy of PS film, resulting in higher crystallinity of pentacene films deposited onto it and an improved interconnection between the pentacene crystalline domains. The device with the PS film thermally treated at 120 °C showed superior performance, affording a mobility as high as 4 cm 2/V s, an on/off ratio of about 10 7–10 8 and a threshold voltage of about 6.5 V in the saturation region.

Enhanced electrical and photosensing properties of pentacene organic thin-film phototransistors by modifying the gate dielectric thickness

The effects of dielectric layer thickness on the electrical performance and photosensing properties of organic pentacene thin-film transistors have been investigated. To improve the electrical performance of pentacene thin-film transistors (TFTs), the poly-4-vinylphenol (PVP) polymer with various thicknesses was used in fabrication of the pentacene transistors. The pentacene thin-film transistor with the PVP dielectric layer of 70 nm exhibited a field-effect mobility of 4.46 cm 2/Vs in the saturation region, a threshold voltage of −4.0 V, a gate voltage swing of 2.1 V/decade and an on/off current ratio of 5.1 × 10 4. In the OFF-state, the photoresponse of the transistors increases linearly with illumination intensity. The pentacene transistor with the thinner dielectric layer thickness indicates the best photosensing behavior. It is evaluated that the electrical performance and photosensing properties of pentacene thin-film transistors can be improved by using various thickness dielectric layer.

Effects of Physical Treatment of ITO Electrodes on the Electrical Properties of Pentacene Thin-Film Transistors

We report that treating indium tin oxide (ITO) source and drain electrodes with ozone or oxygen (O 2 ) plasma enhances the hole injection from these electrodes to pentacene semiconductor, thereby improving the performance of pentacene thin-film transistors. Synchrotron radiation photoelectron spectroscopy results showed that the ozone and O 2 plasma treatments of the electrodes increased their work functions by about 0.4 and 1.0 eV, respectively, compared to the as-deposited ITO electrode. These increases in work function were found to lower the hole injection barrier, producing remarkable increases in the field-effect mobility.

Effect of surface free energy in gate dielectric in pentacene thin-film transistors

The surface free energy of a dielectric has a strong influence on the performance of pentacene thin-film transistors. Research shows that by matching surface free energy in the interface of the dielectric and the orthorhombic thin-film phase of pentacene film, the field-effect mobility of transistors is enhanced reaching above 2.0cm2∕Vs. The authors suggested that a more complete first monolayer of pentacene was formed upon the gate dielectric surface with almost identical surface free energy, benefiting carrier transportation. The research also discusses the mechanism of surface free energy effects on the crystalline size and structural disorder in pentacene film.

Effect of Dielectric Roughness on Performance of Pentacene TFTs and Restoration of Performance with a Polymeric Smoothing Layer

The morphology, structure, and transport properties of pentacene thin film transistors (TFTs) are reported showing the influence of the gate dielectric surface roughness. Upon roughening of the amorphous SiO2 gate dielectric prior to pentacene deposition, dramatic reductions in pentacene grain size and crystallinity were observed. The TFT performance of pentacene films deposited on roughened substrates showed reduced free carrier mobility, larger transport activation energies, and larger trap distribution widths. Spin coating roughened dielectrics with polystyrene produced surfaces with 2 A root-mean-square (rms) roughness. The pentacene films deposited on these coated surfaces had grain sizes, crystallinities, mobilities, and trap distributions that were comparable to the range of values observed for pentacene films deposited on thermally grown SiO2 (roughness also approximately 2 A rms).

Effect of source/drain undercut on the performance of pentacene thin-film transistors on plastic

We studied the electrical properties of bottom contact pentacene thin-film transistors (TFTs) on plastic with and without source/drain undercut. The undercut depends on the Cr thickness in Au∕Cr source/drain electrodes, where Au is used for the ohmic contact with pentacene, and the Cr is to enhance the adhesion of Au to the cross-linked poly-4-vinyphenol gate insulator. The undercut can be removed by reducing the Cr thickness less than 5nm. The TFTs with and without undercut exhibited the field-effect mobility in the saturation region of 0.96 and 1.3cm2∕Vs, respectively, but in the linear region the field-effect mobility of the TFT with source/drain undercut is ∼1∕9 that of the organic TFT without undercut.