Performance Of Junctionless Research Articles

P-Type Trigate Junctionless Nanosheet MOSFET: Analog/RF, Linearity, and Circuit Analysis

Silicon (Si) nanosheet (NS) metal-oxide semiconductor field effect transistors (MOSFETs) are realized as an outstanding structure to obtain better area scaling and power performance compared to FinFETs. The Si NS MOSFETs provide high current drivability due to wider effective channel (W eff) and maintain better short channel performance. Here, the performance of junctionless (JL) SOI NS p-MOSFET is evaluated by invoking HfxTi1−xO2 gate stack to overcome adverse short channel effects (SCEs). The device performance is enhanced using various spacer dielectrics and the electrical characteristics are presented. Moreover, the effect of NS width variation on I ON/I OFF, SS, V th is presented and the analog/RF metrics of the device are evaluated. The power consumption, dynamic power, and static power analyses of NS MOSFET is presented with respect to the ITRS road map. Our investigation reveals that the device exhibits an I ON/I OFF ratio of more than ∼106 with NS widths of 10 to 30 nm, respectively. The device exhibits better performance (I ON) with higher NS widths and ensures potential towards high-performance applications. However, with an increase in NS widths the threshold voltage (V th) tends to downfall and leads to deterioration in subthreshold performance . With high-k spacer dielectric the device exhibits better static power consumption for the CMOS inverter. By careful control of NS width and effective usage of spacer dielectric ensures better p-MOSFET design for future technology nodes.

Influence of Channel Doping on Junctionless and Negative Capacitance Junctionless Transistors

In this work, we report on the impact of channel doping on the performance of junctionless (JL) and negative capacitance (NC) JL devices designed with a gate length (L g) of 18 nm. Results showcase that NCJL devices exhibit negative internal gate voltage (V int) at zero gate bias, which becomes more negative as the channel doping increases. The occurrence of negative V int is the unique feature of NCJL transistors, which is responsible for efficient channel depletion. The analysis showcases that negative V int in NCJL devices leads to lower off-current along with NC induced higher on-current than conventional JL devices. The results reported in this work provide insights into the functionality of NCJL devices and highlight the benefits of designing negative capacitance junctionless devices.

Effects of Work-function Variation on Performance of Junctionless and Inversion-mode Dual-metal Gate Nanowire Transistors

Effects of Work-function Variation on Performance of Junctionless and Inversion-mode Dual-metal Gate Nanowire Transistors