Circuit Performance Research Articles

CNFET-Based Energy-Efficient 4:2 Compressor for Multiplier Applications

Diverse applications in today’s digital era have a high demand for low-power, faster, and high-performance arithmetic circuits. In a multiplier, the power is the costliest part of carrying out partial products. A compressor type of adder is used for faster operation and has lesser power consumption. In this paper, a low-power, energy-efficient 4:2 compressor design has been presented. The proposed design is based on multi-threshold logic. A capacitive network has been used at the input side instead of resistors for better circuit operations. The CNFET-based network is used to design the same. Powers, delay, PDP, and EDP of the proposed design have been computed. It is observed that with 32[Formula: see text]nm CNFET technology it shows a maximum improvement in PDP and EDP of 69% and 70%, respectively. Moreover, extensive performance analyses against power supply, channel length, temperature, load, and operating frequency have been presented. Finally, the proposed compressor is applied to design Wallace’s multiplier which shows that it outperforms all other designs considered in this study. This indicates that the proposed compressor is quite useful for low-power VLSI circuits and systems applications.

Design and Implementation of Device Circuit of Microcontroller-Based Smart Traffic Light Control System

In this paper, the design and implementation of a microcontroller-based smart traffic light control system is presented. The proposed smart traffic light is meant to mitigate or entirely eliminate hassles encountered by road users, mostly at road intersections. The system is sensitive to road density and therefore operates in smart and normal modes, with normal mode as the default; however, it switches to smart whenever the need arises. The approach adopted includes; typical intersection design, circuit diagram design, circuit analysis and overall system development and implementation. The microcontroller, which serves as the overall system brain is programmed using proteus electronic software; and then interfaced with already calibrated ultrasound modules and other components. Afterwards, it is initiated to confirm that research objectives have been met. The design employs a crossbar to prevent drivers from using a lane when not supposed. The traffic light control system, if implemented would significantly minimize traffic frustrations and ugly experiences road users encounter daily on Nigeria roads. However, this work is centred more on circuit operation and design, circuit analysis and overall system development and implementation.

Assessing the Impact of Surface Blast Design Parameters on the Performance of a Comminution Circuit Processing a Copper-Bearing Ore

Open-pit mining remains the dominant method for copper extraction in current operations, with blasting playing a pivotal role in the efficiency of downstream processes such as loading, hauling, crushing, and milling. This study assesses the impact of surface blast design parameters on the performance of a comminution circuit processing a copper-bearing ore. The analysis focuses on important design parameters such as burden, spacing, stemming, and powder factor, evaluating their influence on the fragment size distribution and downstream comminution circuit performance. Using the Kuz-Ram model, four novel blast designs are compared against a baseline to predict the size distribution of rock fragments (X80). Key performance indicators throughput and specific energy consumption are calculated to evaluate the comminution circuit performance. Results demonstrated that reducing the X80 from 500 mm to 120 mm led up to a 20% increase in throughput and a 29% reduction in total specific energy consumption. Furthermore, achieving finer particle sizes through more intensive blasting contributed to a reduction in total operating costs by up to 12%. These findings provide valuable insights for optimizing blast design to improve comminution circuit performance, contributing to sustainable mining practices by reducing energy consumption, operating costs, and the environmental footprint of mining operations.

Area and power efficient FIR filter design in quantum cellular automata using competent adder

Abstract An 8-tap FIR filter is being considered for this research work. The basic modules of the FIR filter are Adders, Delay elements and multipliers. These basic elements are constructed using the majority voter. The interconnections between various logic elements of the circuit are carried out using novel multi-layer interconnection. Also, fast adders such as carry look-ahead adder, carry save adder, and carry select adder have been realized in quantum cellular automata. The circuit performance has been evaluated mainly based on the number of cells used for construction and area. Also additionally, area-latency product (ALP), QCA cost and power-performance area (PPA) have been estimated for validating the effectiveness of the design. Because of the majority voter and multi-layer configuration, the basic elements had occupied a lesser area; due to which the overall area for the 8-tap filter has been reduced effectively. The basic elements had a cell count improvement of 16.27% to 89.37% for full adder, 52.54% to 94.11% for DFF and 15.71% to 94.79% for multiplier with respect to the existing methods. Also, an 8-tap FIR filter consumes 2156 cells, 3447.6 nm2 area, 36.0876 energy dissipation, 13790.4 ALP, and 124415.6 PPA in quantum cellular automata.

Thermally-assisted reformation of spray-printed polymer channel layer for improved transistor performance and device-to-device uniformity

Bulk and surface morphology of a channel layer needs to be controlled to obtain desirable electrical performance of organic transistors and circuits based on them. Although spray coating is widely used in industry for continuous production of thin films, the microscopically rough nature of the spray-printed films makes it challenging to apply in electronics. Herein, we demonstrate a simple, scalable, and general approach by combining solvent mixing and thermal annealing to improve surface flatness, and therefore device reproducibility, without additional apparatuses attached to the spraying tools. We find that a small amount (2–5 vol%) of a high-boiling-point solvent, which can dissolve the channel material only at an elevated temperature, reduces surface roughness and rearranges the internal microstructure of the channel layer via dissolution and re-solidification during heat treatment. Thermally-assisted reformation of the channels of representative polymers (P3HT and PDPP2T-TT) results in 1.5–2.1 times enhancement of charge-carrier mobility in organic electrochemical transistors compared to as-printed films. At the same time, the device-to-device variation is significantly reduced with about 4–5 times lower coefficient variation in electrical characteristics.

Sex-and Stress-Dependent Plasticity of a Corticotropin Releasing Hormone / GABA Projection from the Basolateral Amygdala to Nucleus Accumbens that Mediates Reward Behaviors.

Motivated behaviors are executed by refined brain circuits. Early-life adversity (ELA) is a risk for human affective disorders involving dysregulated reward behaviors. In mice, ELA causes anhedonia-like behaviors in males and augmented reward motivation in females, indicating sex-dependent disruption of reward circuit operations. We recently identified a corticotropin-releasing hormone (CRH) expressing GABAergic projection from basolateral amygdala (BLA) to nucleus accumbens (NAc) that governs reward-seeking deficits in adult ELA males, but not females. To probe the sex-specific role of this projection in reward behaviors, adult male and female CRH-Cre mice raised in control or ELA conditions received excitatory or inhibitory Cre-dependent DREADDs in BLA, and then clozapine N-oxide or vehicle to NAc medial shell during reward behaviors. We determined the cell identity of the projection using immunostaining and electrophysiology. Using tissue clearing, light sheet fluorescence microscopy and deep learning pipelines, we mapped brain-wide BLA CRH+ axonal projections to uncover sex differences in innervation. Chemogenetic manipulations in male mice demonstrated inhibitory effects of the CRH+ BLA-NAc projection on reward behaviors, whereas neither excitation nor inhibition influenced female behaviors. Molecular and electrophysiological cell-identities of the projection did not vary by sex. By contrast, comprehensive whole-brain mapping uncovered significant differences in NAc innervation patterns that were both sex and ELA-dependent, as well as selective changes of innervation of other brain regions. The CRH/GABA BLA-NAc projection that influences reward behaviors in males differs structurally and functionally in females, uncovering potential mechanisms for the profound sex-specific impacts of ELA on reward behaviors.

Imaging dendrite growth in solid-state sodium batteries using fluorescence tomography technology.

Dendrite growth in solid-state sodium batteries (SSBs) is one of the most concerned issues that critically affect the battery efficiency and cycling performance. Here, by designing a fluorescent Eu3+-doped Na3Zr2Si2PO12 solid electrolyte (SE) to facilitate three-dimensional (3D) optical imaging on a confocal laser scanning microscopy, a fluorescence tomography (FT) method is developed for observing the sodium dendrite growth during charge/discharge cycles of the SSBs in a 3D view. It is quantitatively revealed that small-size sodium islands appear after several cycles, and with the cycles increasing, large-size dendrites in tens of micrometers gradually form until a critical sodium dendrite volume arrives where a short circuit or severe performance deterioration occurs. Furthermore, by regulating the Eu3+ doping ratio, a record-high sodium plating/stripping cycling stability for more than 1 year (487.5 days) is achieved at 25°C. This work demonstrates an FT method observing sodium dendrite growth in SSBs and will promote the functional design of high-performance SEs.

Quantum Privacy-Preserving Range Query Protocol for Encrypted Data in IoT Environments.

With the rapid development of IoT technology, securely querying sensitive data collected by devices within a specific range has become a focal concern for users. This paper proposes a privacy-preserving range query scheme based on quantum encryption, along with circuit simulations and performance analysis. We first propose a quantum private set similarity comparison protocol and then construct a privacy-preserving range query scheme for IoT environments. By leveraging the properties of quantum homomorphic encryption, the proposed scheme enables encrypted data comparisons, effectively preventing the leakage of sensitive data. The correctness and security analysis demonstrates that the designed protocol guarantees users receive the correct query results while resisting both external and internal attacks. Moreover, the protocol requires only simple quantum states and operations, and does not require users to bear the cost of complex quantum resources, making it feasible under current technological conditions.

Application of fractional modified taylor wavelets in the dynamical analysis of fractional electrical circuits under generalized caputo fractional derivative

Abstract This study examines the application of fractional calculus in the analysis and modeling of electrical circuits of fractional order, highlighting its potential to explain the behaviour of complex electrical circuits accurately. In the domain of electrical circuits, fractional differential equations are employed in the analysis and simulation of systems that consist of resistors, capacitors and inductors. In the present paper, a novel approach utilizing fractional order modified Taylor wavelets is implemented to solve the fractional model of RL, LC, RC and RLC electrical circuits under generalized Caputo fractional derivative which offers precise and flexible modeling of non-locality and hereditary characteristics in complex systems. Furthermore, an additional parameter σ (time scale parameter) is incorporated in fractional circuit dynamics to maintain the physical dimensionality. The considered wavelets with the collocation technique offer an efficient solution by converting the fractional model of electrical circuits into a set of algebraic equations which are further solved by using the Newton iteration method. Moreover, this study discusses the significance of Ulam-Hyers stability, emphasizing its role in ensuring stable and reliable circuit performance. The impact of fractional order on the dynamics of the electric circuit model is presented by tables and graphs. The approximate solutions obtained by the proposed method are well comparable with exact solutions and some other existing wavelet-based techniques. The residual errors are also evaluated under various model parameters for fractional orders. Furthermore, the graphs illustrate that the error progressively decreases as the number of wavelets basis increases.

AI‐Driven Learning and Regeneration of Analog Circuit Designs From Academic Papers

ABSTRACTThis paper presents an artificial intelligence (AI)‐based framework designed for learning and regenerating analog circuits from academic papers. The framework comprises four distinct modules: circuit extractor, table extractor, text extractor, and simulation executor. The circuit extractor module utilizes deep learning object detection to identify devices and their associated textual descriptions while extracting interconnections between devices. The table extractor module handles textual and image‐based tables, extracting device parameters, and simulation data. The text extractor module leverages optical character recognition (OCR) and AI models to extract supplementary information. The simulation executor employs this information to conduct simulations and optimize circuit performance. In our experiments, our method effectively extracts multimodal circuit design information, achieving an average accuracy of up to 97% in target detection within the circuit extractor module. The improved performance during the simulation process further validates the effectiveness of our framework.

Prevention of Air Embolism in Extracorporeal Membrane Oxygenation Systems: An In Vitro Study on Protection of Central Venous Catheter Lumen.

Background and Objectives: This study aimed to investigate the risk and mechanisms of air entry into the extracorporeal membrane oxygenation (ECMO) circuit through the central venous catheter (CVC) in a veno-venous configuration. The primary goal was to assess the impact of different air volumes on ECMO circuit performance at varying pump speeds. Material and Methods: The study utilized a circuit model to simulate ECMO conditions and evaluate the potential entry points of air, specifically through the unprotected lumen of the CVC. Various interventions, such as the use of a closed three-way stopcock or clave, were implemented to assess their efficacy in preventing air entry. Results: The unprotected lumen of the central venous catheter posed a significant risk for air entry into the ECMO circuit. The introduction of a closed three-way stopcock or clave proved effective in preventing air ingress through the central venous catheter. Auditory cues, such as a distinct hissing sound, served as an early warning sign of air presence in the circuit. The study demonstrated that even small volumes of air, as minimal as 1 mL, could pass through the oxygenator at specific pump speeds, and larger volumes could lead to pump dysfunction. Conclusions: The study identified the unprotected lumen of the central venous catheter as a potential entry point for air into the ECMO circuit. The use of a closed three-way stopcock or one-way valve was found to be a reliable protective measure against air infiltration. Early detection through the observation of a hissing sound in the circuit provided a valuable warning sign. These findings contribute to enhancing the safety and performance of ECMO systems by minimizing the risk of air embolism.

The Application of Secondary Effects in Optimizing Analog Circuits

Abstract. This study delves into the application of secondary effects, specifically body effect, channel length modulation effect, and subthreshold conduction effect, in the optimization of analog integrated circuits. The research highlights the critical role these effects play in modern circuit design, especially as device dimensions continue to shrink. Through a systematic analysis, the study presents key strategies for mitigating these effects to enhance circuit performance, reliability, and power efficiency. Notably, the implementation of a transient BD scheme in partially analog-assisted D-LDOs (Digital Low Dropout Regulators) has shown a performance improvement of over 10% compared to schemes without this enhancement, while also significantly reducing total coupling. Techniques such as DIBL effect compensation have proven effective in reducing load sensitivity and power consumption. This study provide valuable insights and practical approaches for the design and optimization of high-performance, energy-efficient electronic systems, making a significant contribution to the field of integrated circuit design.

Analytical Analysis of Power-Constrained Repeaters’ Insertion in Large-Scale CMOS Chips

As the die area of CMOS integrated circuits continues to increase, interconnects will become dominant in determining the performance of the circuits from the standpoint of speed and power consumption. Uniform repeater insertion is an effective method used to reduce the propagation delay of a signal in long resistive-capacitive lines. However, non-optimal repeaters’ insertion yields non-optimal circuit performance. In this work, we provide a mathematical treatment for optimal repeater insertion with power consumption constraints. In particular, a closed-form expression for the optimum number and size of repeaters is given for a two-stage buffer used as a repeater. The validation of the analytical solution is assessed by means of circuit simulations, by comparing the theoretical optimal number and size of the repeaters to be placed in the long resistive-capacitive line with the simulated values.

Long‐Channel Effects in Randomly Oriented Carbon Nanotube Thin Film Transistors

AbstractCarbon nanotube (CNT) thin film transistors (TFTs) have demonstrated great potential for application in highly sensitive biosensors and large‐area electronics. However, research on the electrical behavior of long‐channel CNT TFTs is lacking; thus, the purposeful improvement in the performance of biosensors or circuits is difficult. In this study, the electrical transport characteristics of ionic‐liquid‐gate CNT TFTs with channel lengths (Lch) ranging from 10 to 400 µm are investigated. The CNT TFTs present classical drift‐diffusion transport at on‐state with a carrier mobility of around 27 cm2 V−1 s−1. In the subthreshold region of the CNT TFTs, an abnormal Lch‐dependent subthreshold swing (SS) relationship, named as the long‐channel effect (LCE)is observed, where SS worsens with increasing Lch. The existence of the junctions between the CNTs results in an unconventional density of states for carriers and a large series resistance for sharing the gate voltage; this dominates the abnormal scaling behavior in the subthreshold region by degrading the electrostatic integrity. The discovery of the abnormal LCE can aid in the construction of device models and purposefully improve the performance of CNT TFTs for biosensors and other large‐scale electronic applications.

Input / Output Relationships for the Primary Hippocampal Circuit.

The hippocampus is the most studied brain region but little is known about signal throughput -- the simplest, yet most essential of circuit operations -- across its multiple stages from perforant path input to CA1 output. Using hippocampal slices derived from male mice, we have found that single-pulse lateral perforant path (LPP) stimulation produces a two-part CA1 response generated by LPP projections to CA3 ('direct path') and the dentate gyrus ('indirect path'). The latter, indirect path was far more potent in driving CA1 but did so only after a lengthy delay. Rather than operating as expected from the much discussed trisynaptic circuit argument, the indirect path used the massive CA3 recurrent collateral system to trigger a high frequency sequence of fEPSPs and spikes. The latter events promoted reliable signal transfer to CA1 but the mobilization time for the stereotyped, CA3 response resulted in surprisingly slow throughput. The circuit transmitted theta (5Hz) but not gamma (50Hz) frequency input, thus acting as a low-pass filter. It reliably transmitted short bursts of gamma input separated by the period of theta wave - CA1 spiking output under these conditions closely resembled the input signal. In all, the primary hippocampal circuit does not behave as a linear, three-part system but instead uses novel filtering and amplification steps to shape throughput and restrict effective input to select patterns. We suggest that the operations described here constitute a default mode for processing cortical inputs with other types of functions being enabled by projections from outside the extended hippocampus.Significance statement Despite intense interest in hippocampal contributions to behavior, surprisingly little is known about how signals are processed across the network linking cortical input to CA1 output. Here, we describe the first input/output relationship for the system with results challenging the traditional tri-synaptic circuit concept. Signal throughput requires mobilization of recurrent activity within CA3 to amplify sparse input from the dentate gyrus into an unexpectedly stereotyped composite response. Potent low-pass filters determine effective input patterns. These results open the way to new analyses of how variables such as aging affect hippocampus and its contributions to behavior while providing material needed for biologically realistic models of the structure.

Phase Separation to Resolve Growth-Related Circuit Failures.

Fluctuations in host cell growth poses a significant challenge to synthetic gene circuits, often disrupting circuit function. Existing solutions typically rely on circuit redesign with alternative topologies or additional control elements, yet a broadly applicable approach remains elusive. Here, we introduce a new strategy based on liquid-liquid phase separation (LLPS) to stabilize circuit performance. By engineering a self-activating circuit with transcription factors (TF) fused to an intrinsically disordered region (IDR), we enable the formation of TF condensates at the promoter region, maintaining local TF concentration despite growth-mediated dilution. This condensate formation preserves bistable memory in the self-activating circuit, demonstrating that phase separation can robustly counteract growth fluctuations, offering a novel design principle for resilient synthetic circuits.

Selecting alternative metals for advanced interconnects

Interconnect resistance and reliability have emerged as critical factors limiting the performance of advanced CMOS circuits. With the slowdown of transistor scaling, interconnect scaling has become the primary driver of continued circuit miniaturization. The associated scaling challenges for interconnects are expected to further intensify in future CMOS technology nodes. As interconnect dimensions approach the 10 nm scale, the limitations of conventional Cu dual-damascene metallization are becoming increasingly difficult to overcome, spurring over a decade of focused research into alternative metallization schemes. The selection of alternative metals is a highly complex process, requiring consideration of multiple criteria, including resistivity at reduced dimensions, reliability, thermal performance, process technology readiness, and sustainability. This Tutorial introduces the fundamental criteria for benchmarking and selecting alternative metals and reviews the current state of the art in this field. It covers materials nearing adoption in high-volume manufacturing, materials currently under active research, and potential future directions for fundamental study. While early alternatives to Cu metallization have recently been introduced in commercial CMOS devices, the search for the optimal interconnect metal remains ongoing.

Design and Development of a Low Cost Smart Electronic School Bell

Abstract: A considerable advancement of automation over the decades shows automation is very much essential in every sectors especially where time is a major factor. Hence there is a huge demand for automated notification or bell system which has high degree of accuracy and low cost. The main purpose of this project is to develop a smart bell system which can be used all kinds of educational institutions. Smart school bell implement a smart way to manage class periods and breaks without use of manually operated manpower. There is a controller machine, where each class can be set up as desired and from this machine one speaker will be installed in each class. Bell will play in every room through the speakers. The machine will be equipped with a microphone that allows the headmaster or anyone to send the message to all classes simultaneously or to any class separately. The system is made by establishing a serial interface between PIC microcontroller (PIC16F877A) and a Real Time Clock (RTC) is designed with the help of PIC 16F72 module and the LCD display units provide real time and class time separately. The software coding part is done using micro C and hardware implementation is done using the components. The main advantage of this project is due to very easy circuit operation it is easy to operate, cost effective and can be password protected to avoid unauthorized access.

The future of transcranial ultrasound as a precision brain interface

Our understanding of brain circuit operations and disorders has rapidly outpaced our ability to intervene and restore them. Developing technologies that can precisely interface with any brain region and circuit may combine diagnostics with therapeutic intervention, expediting personalised brain medicine. Transcranial ultrasound stimulation (TUS) is a promising noninvasive solution to this challenge, offering focal precision and scalability. By exploiting the biomechanics of pressure waves on brain tissue, TUS enables multi-site targeted neuromodulation across distributed circuits in the cortex and deeper areas alike. In this Essay, we explore the emergent evidence that TUS can functionally test and modify dysfunctional regions, effectively serving as a search and rescue tool for the brain. We define the challenges and opportunities faced by TUS as it moves towards greater target precision and integration with advanced brain monitoring and interventional technology. Finally, we propose a roadmap for the evolution of TUS as it progresses from a research tool to a clinically validated therapeutic for brain disorders.

Investigation of PNN Inverter-Based Low PDP 12T GNRFET Full Adder for VLSI Signal Processing Applications

When an adder circuit, which uses less power and operates at a higher speed, is introduced as a fundamental building block, the multiplier, arithmetic and logic unit (ALU), and digital system’s power delay product (PDP) performance can be easily improved. The graphene nanoribbon field effect transistor (GNRFET) used in very large-scale integrated (VLSI) circuits was developed in the submicron regime and offers superior electrical properties to the MOS transistor. This research paper introduces a full-adder circuit containing twelve GNRFETs (12T GF-FA). Calculations have been made about the introduced 12T GF-FA’s power usage, speed, PDP and leakage power. A few of the existing full adders with 8–32 transistors are compared to the performance of the newly proposed 12T GF-FA in terms of power and delay. For this comparison, some conventional full adders with 8–32 transistors have been implemented using 16[Formula: see text]nm technology GNRFETs. The pull-down network of the suggested adder has two stacked GNRFETs. The proposed adder’s current conduction and power consumption are reduced by the use of stacked transistors. According to the simulation results, the PDP of the suggested 12T GF-FA is 73.2–99% lower when compared to other full adders considered state-of-the-art. Additionally, it has been researched and documented how variations in the PVT and GNRFET parameters affect the performance of full-adder circuits. The proposed adder, with its low PDP, is especially suitable for VLSI signal processing applications. The simulation was carried out using the HSPICE simulation tool and the 16[Formula: see text]nm MOS-GNRFET model.