Perform Multiplication Operations Research Articles

Design of Modified Booth’s Encoder Using SPST technique

This paper presents the design and implementation of signed-unsigned Modified Booth Encoding (SUMBE) multiplier. The present Modified Booth Encoding (MBE) multiplier and the Baugh-Wooley multiplier perform multiplication operation on signed numbers only. Therefore, this paper presents the design and implementation of SUMBE multiplier. The modified Booth Encoder circuit generates half the partial products in parallel. By extending sign bit of the operands and generating an additional partial product the SUMBE multiplier is obtained. The Carry Save Adder (CSA) tree and the final Carry Look ahead (CLA) adder used to speed up the multiplier operation. Since signed and unsigned multiplication operation is performed by the same multiplier unit the required hardware and the chip area reduces and this in turn reduces power dissipation and cost of a system. The proposed radix-2 modified Booth algorithm MAC with SPST gives a factor of 5 less delay and 7% less power consumption as compared to array MAC.

Discrete Time Sequence Reconstruction of a Signal Based on Local Approximation Using a Fourier Series by an Orthogonal System of Trigonometric Functions

The article considers the development of mathematical and algorithmic support for the sample’s reconstruction in problem sections of a discrete sequence of a continuous signal. The work aimed to ensure the reconstruction of lost samples or sections of samples with a non-constant distorted time grid when sampling a signal with a uniform step and at the same time to reduce the computational complexity of digital reconstruction algorithms. The solution to the stated problem is obtained based on the local approximation method. The specific of this method application was the use of two subsequences of samples located symmetrically concerning the reconstructed section of the sequence. The approximating model is a Fourier series on an orthogonal system of trigonometric functions. The optimal solution to the approximation problem is based on the minimum square error criterion. Mathematical equations are obtained for this type of error. They allow us to estimate its value depending on the model order and the samples number in the subsequences used in the reconstruction process. The peculiarity of the mathematical equations obtained in this paper for signal reconstruction is that they do not require the preliminary calculation of the Fourier series coefficients. They provide a direct calculation of the values of reconstructed samples. At the same time, when the number of samples in the subsequences used for reconstruction will be even, it is not necessary to perform multiplication operations. All this made it possible to reduce the computational complexity of the developed algorithm for signal reconstruction. Experimental studies of the algorithm were carried out based on simulation modeling using a signal model that is an additive sum of harmonic components with a random initial phase. Numerical experiments have shown that the developed algorithm provides the reconstruction result of signal samples with a sufficiently low error. The algorithm is implemented as a software module. The operation of the module is carried out on the basis of asynchronous control of the sampling reconstruction process. It can be used as part of metrologically significant software for digital signal processing systems.

16-Bit Fixed-Point Number Multiplication With CNT Transistor Dot-Product Engine

Resistive crossbar arrays can carry out energy-efficient vector-matrix multiplication, which is a crucial operation in most machine learning applications. However, practical computing tasks that require high precision remain challenging to implement in such arrays because of intrinsic device variability. Herein, we experimentally demonstrate a precision-extension technique whereby high precision can be attained through the combined operation of multiple devices, each of which stores a portion of the required bit width. Additionally, designed analog-to-digital converters are used to remove the unpredictable effects from noise sources. An 8 × 15 carbon nanotube transistor array can perform multiplication operation, where operands have up to 16 valid bits, without any error, making in-memory computing approaches attractive for high-throughput energy-efficient machine learning accelerators.

Implementation of Modified Booth Encoding Multiplier for signed and unsigned 32 bit numbers

This paper presents the design and implementation of Modified Booth encoding multiplier for both signed and unsigned 32 - bit numbers multiplication. The already existed Modified Booth Encoding multiplier and the Baugh-Wooley multiplier perform multiplication operation on signed numbers only. Whereas the array multiplier and Braun array multipliers perform multiplication operation on unsigned numbers only. Thus, the requirement of the modern computer system is a dedicated and very high speed unique multiplier unit for signed and unsigned numbers. Therefore, this paper presents the design and implementation of SUMBE multiplier. The modified Booth Encoder circuit generates half the partial products in parallel. By extending sign bit of the operands and generating an additional partial product the SUMBE multiplier is obtained. The Carry Save Adder (CSA) tree and the final Carry Look ahead (CLA) adder used to speed up the multiplier operation. Since signed and unsigned multiplication operation is performed by the same multiplier unit the required hardware and the chip area reduces and this in turn reduces power dissipation and cost of a system. Index Terms: Modified Booth Encoding multiplier, Baugh-Wooley multiplier, array multiplier, CSA, CLA Partial product, Signed-unsigned.

Parallelizing GF (p) Montgomery Elliptic Curve Crypto-System Operations to Improve Security and Performance

The elliptic curve crypto-system (ECC) performs two levels of computations, lower point operations, and upper scalar multiplication levels. The use of usual serial design and affine coordinates to apply ECC computations increases the time delay and weaken the security of the crypto-system against simple power attack (SPA). This work combines the inherited parallelism in both computation levels for GF (p) Montgomery ECC to improve performance and enhance the immunity of the ECC against SPA. Moreover, projective coordinates were used to apply ECC operations to eliminate the time-consuming inversion operation. In order to increase the speed even further, this paper proposes to use known NAF algorithm for scalar multiplication, as well as Montgomery multiplier to perform multiplication operations. Hardware implementations with target FPGA for GF (p) Montgomery ECC are also presented. The best performance level was achieved when parallelizing Montgomery ECC computations to eight parallel multipliers (PM) using homogeneous coordinates. Such strategy, although it requires extra resources, is worth considering due to its attractive security and performance conclusions.

Guest Editorial: Special Section on Computer Arithmetic for Optical Computing

Around the same time, non-binary systemssuch as multiple valued logic ~MVL!~Ref. 3! alsoachieved prominence both in optics and digital comput-ing. Since then a large number of papers have been pub-lished in optical computer arithmetic. This special sectionis an attempt to capture current research in computerarithmetic for optical computing. The five major areasthat are presented in this section are MSD-based algo-rithm and systems, optimization of MVL, novel architec-tures for binary optical computing, high accuracy analogoptical system implementations, and system studies forfault-tolerance and accuracy. Some of the papers mayhave overlap of two or more areas with one primary fo-cus; they are pointed out in the following discussion.The largest cluster of papers appears in the area ofsigned-digit arithmetic and its implementation. A numberof different techniques for addition, multiplication and di-vision are proposed by several authors. The number sys-tems addressed include redundant binary, MSD binary,negabinary, MSD trinary, recoded trinary and MSD qua-ternary. In terms of number of steps, addition/subtractionin single, dual and triple step has been proposed. Whilethe MSD number system leads to higher information den-sity, if the number of steps is reduced, the truth tablesmay become humongous, which may impose challengingrequirements on the actual implementation. Techniquesfor reducing the cost of such implementations have beenaddressed by some authors. Proposed implementations in-clude space-variant logic array, correlator~composite andpseudo-inverse filter! and non-holographic content ad-dressable memory ~CAM! using electron-trapping mate-rial. Several authors have proposed novel algorithms andtheir possible optical implementations while others havesuggested implementations and/or optimization on knownalgorithms.The first paper in the area of signed-digit arithmetic byLi et al. presents negabinary arithmetic operations for ad-dition, subtraction and multiplication and implementsthem using electron trapping material. A carry free addi-tion technique in signed-digit negabinary ~SDN! is pre-sented with a conversion technique from SDN to normalnegabinary. Zhang and Karim propose modified two-step,one-step, canonical and three-input algorithms for addi-tion of redundant binary numbers and provide architectureand encoding for corresponding optical space-variantimplementation. Cherri demonstrates single step trinaryand quaternary signed-digit circuits. In general, the reduc-tion in step increases the complexity of the truth table.However, Cherri overcomes the problem by smart digitgrouping to reduce the number of rules and an intelligentpixel encoding to implement the system within a certainspace-bandwidth product. Huang, Itoh and Yatagai pro-pose a new technique for high-speed 2-D data array addi-tion and multiplication based on binary MSD addition anddigit-decomposition-plane representation. Huang, Itohand Yatagai generate all the partial products in paralleland propose to add them using an MSD adder tree. It isinteresting to note that they perform multiplication opera-tion using five elementary operations such as bitwiseproduct, duplication, shifting, masking and magnification.In the next paper, Alam introduces trinary division tech-nique based on recoded trinary addition and multiplica-tion. The proposed implementation uses a pseudo-inversefilter correlator. The last two papers in this group byAhmed, Awwal and Power and by Zhang and Karim pro-pose novel implementations of trinary and binary MSDalgorithm. Ahmed, Awwal and Power implement an MSDtrinary adder using composite phase-only-filter correlatorarchitecture. In this framework, the truth table rules are