Per-core Power Gating Research Articles

Understanding Power Gating Mechanism Based on Workload Classification of Modern Heterogeneous Many-Core Mobile Platform in the Dark Silicon Era

The rapid progress in mobile computing necessitates energy efficient solutions to support substantially diverse and complex workloads. Heterogeneous many core platforms are progressively being adopted in contemporary embedded implementations for high performance at low power cost estimations. These implementations experience diverse workloads that offer drastic opportunities to improve energy efficiency. In this paper, we propose a novel per core power gating (PCPG) approach based on workload classifications (WLC) for drastic energy cost minimization in the dark silicon era. Core of our paradigm is to use an integrated sleep mode management based on workloads classification indicated by the performance counters. A number of real applications benchmark (PARSEC) are adopted as a practical example of diverse workloads, including memory- and CPU-intensive ones. In this paper, these applications are exercised on Samsung Exynos 5422 heterogeneous many core system showing up to 37% to 110% energy efficient when compared with our most recent published work, and ondemand governor, respectively. Furthermore, we illustrate low-complexity and low-cost runtime per core power gating algorithm that consistently maximize IPS/Watt at all state space.

Fine-Grained Online Energy Management of Edge Data Centers Using Per-Core Power Gating and Dynamic Voltage and Frequency Scaling

It is important to minimize the energy consumption of large-scale, geographically distributed edge data centers (EDCs). While modern processing units (PUs) have energy-saving features like Dynamic Voltage and Frequency Scaling (DVFS) and Per-Core Power Gating (PCPG), optimization is still complex and requires a holistic approach. This paper presents a new decentralized, three-timescale, online optimization approach that enables multicore micro data centers (MDCs) to optimize their per-PU power states, per-enabled-PU voltage-frequency levels and offloading schedules at three different timescales. The key idea is that we employ multi-timescale Lyapunov optimization to decouple the energy minimization between workload scheduling and result delivery at a small timescale and PU configuration at large timescales. Another important aspect is that we apply the primal decomposition to decouple the PU configuration between a per-enabled-PU voltage-frequency level at an intermediate timescale and a per-PU power state at a large timescale. Experiments demonstrate that the proposed approach improves energy efficiency significantly by up to 4.5 times in our considered lightly loaded situations where DVFS alone does not work effectively, compared to existing benchmarks.

Reliability-Aware Runtime Power Management for Many-Core Systems in the Dark Silicon Era

Power management of networked many-core systems with runtime application mapping becomes more challenging in the dark silicon era. It necessitates considering network characteristics at runtime to achieve better performance while honoring the peak power upper bound. On the other hand, power management has a direct effect on chip temperature, which is the main driver of the aging effects. Therefore, alongside performance fulfillment, the controlling mechanism must also consider the current cores' reliability in its actuator manipulation to enhance the overall system lifetime in the long term. In this paper, we propose a multiobjective dynamic power management technique that uses current power consumption and other network characteristics including the reliability of the cores as the feedback while utilizing fine-grained voltage and frequency scaling and per-core power gating as the actuators. In addition, disturbance rejecter and reliability balancer are designed to help the controller to better smooth power consumption in the short term and reliability in the long term, respectively. Simulations of dynamic workloads and mixed criticality application profiles show that our method not only is effective in honoring the power budget while considerably boosting the system throughput, but also increases the overall system lifetime by minimizing aging effects by means of power consumption balancing.

Runtime power reduction capability of the IBM POWER7+ chip

Four new energy management features in the POWER7+™ chip enable larger reductions in chip power consumption and further increase energy efficiency of the system during runtime compared with prior POWER7® systems. First, per-core power gating reduces idle power consumption by allowing the system to turn off the voltage to the processor cores when they are not being used. Second, real-time measurement and control of operational guardband allows for higher maximum clock frequency as well as better dynamic voltage selection to reduce power. Third, per-thread utilization counters enable the firmware to sense processor utilization on a finer granularity and set per-core frequency targets with greater accuracy. Finally, a per-core memory access counter allows firmware to more accurately account for power consumption and budget it on a per-processor core basis. These hardware capabilities together enable new EnergyScale™ firmware functions that include voltage optimization to achieve higher turbo frequencies under stressful environmental conditions, automated idle state detection and management, per-core adaptive frequency scaling, and online power modeling for real-time estimation of energy savings.

Analyzing Potential Throughput Improvement of Power- and Thermal-Constrained Multicore Processors by Exploiting DVFS and PCPG

Process variability from a range of sources is growing as technology is scaled below 65 nm, increasing variations of transistor delay and leakage current both within a die and across dies. This, in turn, negatively impacts maximum operating frequency and total power consumption of processors. Meanwhile, manufacturers have integrated more cores in a single die to improve the throughput of processors running highly-parallel workloads. However, many existing workloads do not have high enough parallelism to exploit multiple cores in a processor. First, in this paper, we maximize the throughput of power- and thermal-constrained multicore processors using per-core power gating and dynamic voltage/frequency scaling. When we do not have enough parallelism to effectively use all cores, we turn off some cores using per-core power gates that are already available in commercial multicore processors. This provides extra power and thermal headroom, and allows active cores to run faster through voltage/frequency scaling within power, thermal, and voltage scaling limits. Our analysis using a 32 nm predictive technology model demonstrates that jointly optimizing the number of active cores and maximum operating frequency can improve the throughput of a 16-core processor running workloads with limited parallelism by up to 14%. Second, we extend our throughput analysis and optimization to consider the impact of within-die spatial process variations that lead to considerable core-to-core frequency and leakage power variations in multicore processors. Our analysis shows that exploiting core-to-core frequency variations can improve the throughput of a 16-core processor by up to 57%.

Power Management of Datacenter Workloads Using Per-Core Power Gating

While modern processors offer a wide spectrum of software-controlled power modes, most datacenters only rely on dynamic voltage and frequency scaling (DVFS, a.k.a. P-states) to achieve energy efficiency. This paper argues that, in the case of datacenter workloads, DVFS is not the only option for processor power management. We make the case for per-core power gating (PCPG) as an additional power management knob for multi-core processors. PCPG is the ability to cut the voltage supply to selected cores, thus reducing to almost zero the leakage power for the gated cores. Using a testbed based on a commercial 4-core chip and a set of real-world application traces from enterprise environments, we have evaluated the potential of PCPG. We show that PCPG can significantly reduce a processor's energy consumption (up to 40%) without significant performance overheads. When compared to DVFS, PCPG is highly effective saving up to 30% more energy than DVFS. When DVFS and PCPG operate together they can save up to almost 60%.