Modular multilevel converters consist of many capacitor half-bridge or full-bridge converter cells. Stresses on the capacitors result from peak capacitor voltage, capacitor voltage ripple and current ripple. Three new tractable convex optimisation problems are presented that reduce peak capacitor voltage and limit rms arm current using injected zero-sequence voltages, circulating currents and selecting the initial stored capacitor energy. These optimisation problems are compared to assess their performance in terms of key indicators which include factors related to capacitor stress, capacitor and semiconductor ratings, and power loss: peak capacitor voltage, capacitor voltage ripple, capacitor current ripple, average and rms arm current. The optimisation methods permit designers to understand the trade-offs in achieving the limits imposed by device specifications and power losses.