Pb-free Bumps Research Articles

A Study of Low-Cost Sequential Electroplating Bumping Process and its Metallurgical Behavior

Studies were conducted to validate from a metallurgical point of view whether a lower cost sequential plating approach to SnAg and SnAgCu (SAC) solder bumping is a suitable alternative to the conventional alloy plating process. A range of Ag content corresponding to typical bump applications was explored with respect to Ag diffusion and intermetallic compound (IMC) formation. Variables that can affect such IMC formation were further explored as a function of underbump metallization (UBM) structure and cooling rate during bump solidification. By comparing the results to those previously reported on SnAg-based alloys, it is demonstrated that the proposed sequential plating process produces very similar microstructures and Ag3Sn IMC morphologies, due to the rapid diffusion and distribution of Ag through the liquid Sn. Known means to mitigate the less desirable large Ag3Sn platelets, that is by changing the top UBM layer from Cu to Ni or by employing an ultrarapid cooling rate, are shown to be equally effective for sequential plating. These observations, in conjunction with the simplicity and flexibility of plating multiple single metals, propose adoption of the sequential plating process as a cost-effective and robust Pb-free bumping solution for fine pitch flip-chip packaging.

Package Technology Selection of 28nm High Power FPGA with Pb-Free Solder Bumps: Flip Chip Molded BGA (FCMBGA) versus Traditional Flip Chip Bare Die Package

Selecting the optimal flip-chip package technology for the next generation 28nm FPGA is critical not only to meet reliability benchmarks for Pb-free bumps, but also in meeting the field-use environment requirements for high power devices. Component level reliability testing was conducted on three separate package types: Bare die flip chip BGA (FCBGA), flip chip molded BGA with capillary underfill (FCMBGA w/CUF), and flip chip molded BGA with molded underfill. (FCMBGA). Testing was conducted independently at two separate sites. Testing included moisture resistance testing (MRT), temperature cycle (JESD22-A104 Condition Level B), and a hybrid test combining 100 hours of unbiased HAST (JESD22-A118A) with temperature cycling. Reliability monitoring was conducted through multiple means including electrical testing for circuit continuity, CSAM imaging at frequent read points to monitor silicon integrity and underfill adhesion performance, cross-sections for the inspection of bump crack propagation, and FIB analysis of the UBM structure after test completion. In addition to reliability testing of three flip chip BGA platforms, other usage factors were considered. These include package specific design rule flexibility for passive placement and future generation packaging requirements. The results of the evaluation demonstrated that bump integrity remained strong for all three package types – showing no cracks after 1,500 temperature cycles, hybrid testing, or MRT. Ultimately, the FCMBGA with molded underfill was selected based on the quality of the bumps after testing, the design rule flexibility for capacitor placement, and improved component protection from mechanical damage.

Packaging Approach for Integrating 40/45-nm ELK Devices Into Wire Bond and Flip-Chip Packages

There is a rapid transition in the semiconductor packaging industry of devices moving toward 40/45-nm extreme low k (ELK) from the development phase into mainstream semiconductor assembly manufacturing. The drive to achieve adoption without major changes to process and equipment infrastructure while meeting the superior yield necessary is high. The main goal of this paper is to share learning's and provide solutions for integration and qualifications of 40/45-nm ELK devices into flip-chip (FC) and wire-bond (WB) package technology. The scope of this paper covers the fine-pitch ball grid array for the WB packages and FC chip-scale package for the FC Devices. The main challenge and focus point for WB 45/40-nm interconnects is on the first bond process. This paper will share some detailed analysis on the following. 1) Characterization for 45 nm ELK ultrafine-pitch. 2) Key factors for good Au ball bond integrity. 3) Recommendations for achieving the required levels of reliability for 45-nm Cu ELK. The challenge of FC Technology today has been changing at a faster rate and more and more adoption has been made from the conventional eutectic solder bumps or high lead solder bumps toward the lead free solder bump mainly due to the Green initiatives. This paper will share analysis on the following areas. 1) Thermo-mechanical simulation on key input factors and its correlation to actual evaluations. 2) Integration of Pb Free ELK bumps with 40-nm ELK technology are various critical processes. 3) Moldable underfill technology for Pb Free + ELK devices. In addition, critical process control is also required at the wafer level process of wafer thinning and dicing, including the need of Laser Grooving will also be covered.

A Comparison of Flip Chip Bump Electromigration Reliability for Cu Pillar, High Pb, SnAg, and SnPb Bump Structures

Electromigration failure in flip-chip bumps has emerged as a major reliability concern due to potential elimination of Pb from flip-chip bumps and a continuous drive to increased IO density resulting in a reduction of bump size and pitch. Traditionally, flip-chip interconnects incorporate a high Pb bump soldered with a SnPb eutectic paste to the substrate or another die. However, because of RoHS directives, the industry is responding with Pb free bump development, such as SnAg bump with SAC solder or Cu Pillar with SAC/SnAg solder. Although a number of recent publications deal with electromigration reliability of Pb free and Cu Pillar bumps, a gap exists in terms of their performance comparison with high Pb and SnPb solder on the same bump geometry. The available test data is based on different test vehicles and it becomes difficult to determine the relative performance of these different metallurgies under accelerated test conditions. In addition, not all published data provides the essential parameters of Black's equation to determine the performance and reliability for actual use conditions. This paper attempts to fill this gap by comparing electromigration performance of High Pb, SnPb eutectic, SnAg, and Cu Pillar bumps using the same test vehicle. A special test vehicle was designed with daisy chain structures for electromigration testing and the packages we assembled on test cards. The testing is being done using five (5) stress conditions (combination of current and temperature) to estimate the current density exponent, n, and activation energy, Ea, parameters for Black's equation. The reliability data as well as failure modes for these bump metallurgies will be presented in the paper.

Forward and Backward Compatibility of Solder Alloys With Component and Board Finishes

The primary objective of the research presented in this paper is to qualify the reliability of mixed assemblies by comparing them to the conventional Sn-Pb assembly and completely Pb-free assembly. The research investigates both forward and backward compatibility in electronic assemblies using a design of experiments (DOE) approach. The investigation utilized a test vehicle containing an area array component (BGA169) and chip components (0603 resistors). Hot air solder leveling (HASL) and organic solderability preservative (OSP) surface finishes were used on the test vehicles to represent Sn-Pb and Pb-free alternatives, respectively. The assembled test vehicles were cut into two panels - one containing a resistor section for isothermal aging and the other containing a BGA and another resistor section for thermal shock. The assemblies were subjected to isothermal aging and thermal shock tests as per Interconnecting and Packaging Electronic Circuits/Joint Electronic Device Engineering Council (IPC/JEDEC) standards. The resistors were sheared in the as-soldered condition, and at various isothermal aging intervals and thermal shock cycles. In order to simulate an intermetallic failure in isothermal aging, a reduced shear height (20 mum) was used for the shear test. The performance of the resistor solder joints were quantified in terms of the shear force. The performance of the ball grid array (BGA) solder joint during thermal shock testing was quantified in terms of the number of cycles to failure. Experimental results from shear analysis of resistor solder joints show that Pb-free alloy assemblies' performance is superior to those assembled using Sn-Pb alloy. Also, the ductile nature of the Sn-Ag-Cu (SAC) alloy provides the joints a better fatigue life. With the area array components, Pb-free assembly joints outlived the traditional Sn-Pb joints when subjected to thermal shock loading. Among the mixed assemblies, backward-compatible assemblies (Pb-free bumps and Sn-Pb solder alloy) showed superior performance. The microstructural analysis of the solder joints indicate a uniform distribution of lead in the solder joint matrix.

Nickel silicon thin film as barrier in under-bump-metallization by magnetronsputtering deposition for Pb-free chip packaging

In the search for a Pb-free compatible under-bump-metallization (UBM) barrier material, magnetron sputtering of a nonmagnetic nickel silicon alloy (NiSi) target was used to deposit a low-stress polycrystalline NiSi thin film. In the reaction with SnAg3.0Cu0.5 solder, NiSi was found to have greatly reduced reaction and intermetallics (IMC) formation rates compared with sputtered NiV. A continuous layer of IMCs in NiSi UBM-solder joint remains stable after 10 reflows and 1000 h thermal aging tests, resulting in preferred bulk solder failure mode in ball shearing/pull testing. Our results demonstrate that NiSi is a highly promising thin film barrier material suitable for Pb-free solder bumping.

Under bump metallurgy study for Pb-free bumping

The demand for Pb-free and high-density interconnection technology is rapidly growing. The electroplating-bumping method is a good approach to meet fine-pitch requirements, especially for high-volume production, because the volume change of patterned-solder bumps during reflow is not so large compared with the stencil-printing method. This paper proposes a Sn/3.5Ag Pb-free electroplating-bumping process for high-density Pb-free interconnects. It was found that a plated Sn/Ag bump becomes Sn/Ag/Cu by reflowing when Cu containing under bump metallurgy (UBM) is used. Another important issue for future flip-chip interconnects is to optimize the UBM system for high-density and Pb-free solder bumps. In this work, four UBM systems, sputtered TiW 0.2 µm/Cu 0.3 µm/electroplated Cu 5 µm, sputtered Cr 0.15 µm/Cr-Cu 0.3 µ/Cu 0.8 µm, sputtered NiV 0.2 µm/Cu 0.8 µm, and sputtered TiW 0.2 µ/NiV 0.8 µm, were investigated for interfacial reaction with electroplated Pb/63Sn and Sn/3.5Ag solder bumps. Both Cu-Sn and Ni-Sn intermetallic compound (IMC) growth were observed to spall-off from the UBM/solder interface when the solder-wettable layer is consumed during a liquid-state "reflow" process. This IMC-spalling mechanism differed depending on the barrier layer material.