Pattern-dependent Jitter Research Articles

Bandwidth Enhancement of Flip-Flops Using Feedback for High-Speed Integrated Circuits

This brief presents a high-speed inductorless D flip-flop (DFF) architecture that works on the principle of equalization using two feedbacks. Feedback from the first latch output to the input effectively results in a linear equalizer, whereas the feedback of the flip-flop output to the input culminates in decision feedback equalization. The proposed feedback-based DFF designed in a 90-nm CMOS technology shows 37.5% improvement in speed, as compared with the conventional flip-flops (conv-DFFs) without feedbacks. Post-layout circuit simulations also show an overall 33.7% improvement in the speed of a high-speed pseudorandom binary sequence generator when such feedbacks are added to conv-DFFs in it. Additionally, when this technique is used in a Hogge phase detector for clock and data recovery, 89% improvement in vertical eye opening and 73% reduction in pattern-dependent jitter at the input of the phase detector are observed. In essence, the technique effectively achieves distributed equalization in high-speed communication circuits.

Transition‐aware feed‐forward equaliser for reducing pattern‐dependent jitter in four‐level pulse‐amplitude modulation transmitters

To reduce pattern-dependent jitter in four-level pulse-amplitude modulation (PAM-4) signalling, a transition-aware feed-forward equaliser (TFFE) is proposed. By allowing the transition time to vary according to the transition types of the PAM-4 symbols, switching jitter in TFFE-based PAM-4 transmitters can be greatly suppressed, down to the non-return-to-zero (NRZ) level. Simulation results confirm that a PAM-4 transmitter that employs a TFFE can reduce the jitter level by 0.18 unit interval peak-to-peak, and this proposed equaliser can achieve nearly identical eye height as the conventional PAM-4 feed-forward equalisers design without introducing any signal-to-noise ratio penalty.

A 40 Gb/s Multi-Data-Rate CMOS Transmitter and Receiver Chipset With SFI-5 Interface for Optical Transmission Systems

A fully integrated 40 Gb/s transmitter and receiver chipset with SFI-5 interface is implemented in a 65 nm CMOS technology and mounted in a plastic BGA package. The transmitter chip provides good jitter performance with a 40 GHz full-rate clock architecture that alleviates pattern-dependent jitter and eliminates duty cycle dependence. The measured RMS jitter on the output is 570 fs to 900 fs over the range of 39.8 Gb/s to 44.6 Gb/s with a 231-1 PRBS pattern. The receiver chip operates over the range of 37 Gb/s to 41 Gb/s. The measured RMS jitter on the recovered clock is 359 fs to 450 fs. By taking advantage of CMOS technology, each chip achieves low power consumption of 2.8 W and full integration of SFI-5 functions, PRBS generators/error checkers, a DPSK precoder/decoder, and control interfaces in a 4.9 × 5.2 mm2 die.

Line Codes for Clock Recovery with Low-Q Filtering

The principles of multiple block code (MBC) that feature in filter-less clock recovery are overviewed. Jitter generations are discussed to show that reducing the total amount of delay in MBC family coding can lead to suppressing jitter generation. Jitter accumulation in the repeater chain is also discussed to show that applying very low-Q filtering can drastically reduce the accumulation of high-frequency jitter. New members of MBC family codes for clock recovery with low-Q filtering that can reduce the total amount of delay in coding by a factor of six at the most are proposed. It is confirmed in an experimental set up that pattern dependent jitter can be reduced by a factor of three. An extended version of family members that can improve coding efficiency are proposed and confirmed in an experimental set up.

The importance of calibration standards in jitter measurements

When ITU-T standardized SONET/SDH in 1988, the highest speed was 156 Mb/s. The rapid growth of the Internet, as well as other factors, has increased the necessary speed of today's networks to 10 Gb/s or 40 Gb/s (10G, 40G). In 2000, ITU-T Recommendation G.783 specified the maximum jitter for error-free communications on 10G and 40G networks, but there was not a standard process to verify the accuracy of jitter measurements and no reference source with a known jitter amount. Accurate jitter measurements at high speed are difficult because of the small times involved, but they are essential for implementing error-free networks. The paper describes a method which shows that accurate jitter measurements at 10G and above must correctly account for both pattern-dependent and random jitter. Pattern-dependent jitter is caused to a much greater extent by the transmitter than by the receiver. Incorrect assumptions about the source of pattern-dependent jitter can result in large inconsistencies in jitter measurements at high speed. The method outlined solves those problems.

Enhanced on-wafer time-domain waveform measurement through removal of interconnect dispersion and measurement instrument jitter

We have measured the output waveshape and rise time of two high-speed digital circuits on a wafer using a 50-GHz prototype of a new instrument. The instrument uses vector error correction to de-embed the component under test like a network analyzer, but reads out in the time domain after the fashion of an equivalent-time oscilloscope. With the calibration plane of the instrument set at the tips of the wafer probes, errors arising from dispersion in the connection hardware are removed. We show that the random jitter in the measurement system is removed without the convolution penalty usually incurred by averaging so that anomalies such as pattern-dependent jitter are exposed. The system rise time is 7 ps, compared to a system rise time of 12-13 ps for a conventional equivalent-time oscilloscope of the same bandwidth in the presence of wafer probes, bias networks, and cables.

Measurements and modelling of pattern-dependent BER and jitter in reshaping optoelectronic repeaters

A reshaping optoelectronic repeater is investigated in a loop experiment. If such a device is used in an optical network, the jitter accumulation and its influence on the cascadability are important issues. Whereas the RMS jitter was fairly independent for PRBS patterns, the bit-error rate showed a large pattern dependence. In order to explain these results, a simplified model of the repeater is used, where the device is modelled as a filter followed by an ideal limiter.

Wavelet-based signal design for reduced jitter timing-recovery

This paper addresses two issues in clock synchronization in the context of the theory of wavelets: design of prefilters eliminating pattern-dependent jitter (PPJ) and design of low-jitter shaping pulses for timing recovery. We derive low-jitter symmetric and time-limited shaping pulses via a perturbational technique from the autocorrelation of the Daubechies (1992) scaling function.

Clock synchronisation without self-noise using wavelets

The authors present a symbol synchronisation scheme using wavelets that completely eliminates pattern-dependent jitter [1]. This is achieved by obtaining the optimal prefilter using a particular linear combination of the wavelet and its translates.

Spectral analysis of timing jitter effects on the cyclostationary PPM format

An original spectral characterisation for the cyclostationary PPM format is developed when the format is impaired by timing jitter. Consideration is first given to the self-noise giving rise to pattern-dependent jitter. Then a Gaussian noise environment is considered and the resultant jitter is evaluated. The spectral characterisation together with a linearised phase lock loop (PLL) model are used to evaluate the extracted slot clock timing variance. Later an analysis is carried out to interpret the jitter on the slot clock as an increase in the system error rate. The results indicate that with proper selection of the PPM parameters (hence the spectra observed at the PLL input), PLL parameters and fibre bandwidth, the additional error rate impairment due to jitter can be maintained much lower than the PPM system operating error rate of 10 −9.

A class of data-aided timing-recovery schemes

This paper develops a class of data-aided timing-recovery schemes whose structure and operating principle are reminiscent of zero-forcing equalizer adaptation. The schemes exhibit no pattern-dependent jitter and are applicable to a variety of modulation codes and reception techniques. They come in both oversampled and baud-rate forms, and permit maximum-likelihood tracking performance whenever the oversampling factor satisfies the sampling theorem. Subject to this condition, even simple schemes can be close to optimum. It is shown that various existing; schemes belong to the class under study or are closely related to it.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Theoretical characterisation and practical implementation of optical fibre PPM self synchronisation sequences

AbstractA novel technique for estimating the optical fibre PPM frame phase and eliminating the pattern dependent jitter is proposed while practical implementations and a mathematical characterisation for the technique are reported. Use is made of naturally occurring sequences thus avoiding the sensitivity and bit rate penalties associated with the previous methods. Tracking additional sequences is demonstrated and shown to be beneficial resulting in a frame rate discrete component enhancement of 10.8 dB and timing variance reduction from 12 × 10−3 rad2 to 3.6 × 10−3 rod2. Utilising the systematic jitter rejection method proposed resulted in a measured timing variance reduction from 3.6 × 10−3 rad2 to 4.2 × 10−5 rod2. The limit is imposed by the PLL performance while good correlation is depicted with the theoretical model.

The accumulation of pattern-dependent jitter for a chain of fiber optic regenerators

The experimentally validated linear, shift-invariant jitter model of an individual fiber-optic regenerator is used to derive the jitter accumulation model for a chain of nonidentical fiber-optical regenerators. The jitter characteristics of 40 regenerators are measured individually and are used as parameters in the jitter accumulation model. The calculated accumulation is compared to an accumulation measurement made along a chain of these same 40 regenerators to estimate the portion of pattern-dependent jitter that accumulates systematically. >

Jitter in digital networks

The accumulation and tolerance of timing jitter in digital networks is analysed for transmission links containing regenerators as well as dejitterizers and/or multiplexer—demultiplexer pairs, and for timing circuits employing phase-locked-loops. Both systematic pattern-dependent jitter and waiting-time jitter are taken into account. It is shown that, under practical circumstances, the total accumulated jitter can be adequately described by some simple equations and measurement data confirm these equations. An experimental relation between peak-peak jitter values over a long period and those over a short period is presented. The results of the analysis have led to the conclusion that the internationally recommended maximum permissible peak-peak jitter values at digital interfaces will never be reached in the Dutch digital network.

Report: Parallel Scrambling Techniques for Digital Multiplexers

Scrambling of a digital bit stream is required in order to reduce interference (by randomizing a bit stream), to provide a high transition rate, and to suppress static pattern-dependent jitter. <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1,2</sup> Two fundamental scrambling techniques, self- and frame-synchronous scrambling, are widely used in transmission systems. Self-synchronous scrambling has an error multiplication effect and may not work properly for consecutive input of zeros and ones. <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> For a certain periodic input, the scrambled sequence has a periodicity the same as that of the input. <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup>

Linear Phase-Locked Loop Theory for Cyclostationary Input Disturbances

This paper presents a general method for evaluating the linearized tracking performance of phase-locked loops (PLL's) estimating the phase of an unmodulated sinusoid corrupted by an additive disturbance which is described in terms of cyclostationary processes. Such disturbances are frequently encountered in carrier modulated systems where the sidebands are responsible for the error in estimating the carrier phase, and in baseband pulse amplitude modulation (PAM) systems where the timing error is caused by the so-called pattern-dependent jitter. The tracking performance has already been determined in the case where the disturbance is band limited [12]. In this paper, a general solution which applies to both cases of carrier extraction and clock synchronization is derived. One might be tempted to replace the disturbance by a stationary process with the same power spectral density, and then evaluate the linearized tracking performance by means of conventional linear PLL theory. It is shown that the mean-square phase error can be severely overestimated by applying this procedure.

Comment on "Tracking Performance of the Filter and Square Bit Synchronizer"

The method for evaluating the tracking performance in the above paper obliterates the contribution to the mean square error which is due to the cyclostationarity of the disturbances. Beside this, the pattern-dependent jitter has not been considered in the paper. Our results include the effect of cyclostationarity and the pattern-dependent jitter.

Optimizing Pulse Shaping for Baseband Digital Transmission with Self-Bit Synchronization

An effort is made to devise pulse shaping methods for self-bit-synchronizing systems that minimize both intersymbol interference and pattern-dependent jitter. Attention is confined to minimum-phase shaping which is considered from the standpoint of baseband applications. A short review of jitter analyses is also provided. It lays stress on discerning jitter components that accumulate along repeater chains from those that do not. Pulse shaping functions for the signal path, i.e., Nyquist's problem under minimum-phase constraint, are investigated first and found to result in Bessel filtering as well as its steepest descent modifications. It is observed that reducing intersymbol interference leads to increased pattern-dependent jitter. Next, pulse shaping functions for the timing path are developed. A broad sense symmetrical waveform concept produces a method of synthesizing shaping networks that can drastically reduce waveform dependent jitter, at the sacrifice of increased intersymbol interference. Finally, simultaneous minimizations of intersymbol interference and timing jitter are attempted. A minimal oscillatory tail shaping method incorporating a predistortion technique is shown to be quite efficient for this purpose and thus attractive for simple implementations.

Techniques to Generate ISI and Jitter-Free Bandlimited Nyquist Signals and a Method to Analyze Jitter Effects

An analytical method to predict the data pattern dependent jitter is presented. Results obtained are shown to be in excellent agreement with those obtained by computer simulation and laboratory measurement. In order to find methods that can generate an ISI (intersymbol interference) and jitter-free bandlimited Nyquist signal, a double-intervaled raised cosine and its spectral characteristics are studied. Based on this, a search for new double-intervaled pulses having low spectral sidelobes is conducted. Pulses having desirable spectral characteristics and their application in communication systems are discussed. Two methods for the generation of ISI and jitter-free Nyquist signals are described. The first one uses the concept of pulse overlapping while the second one incorporates the nonlinear switching concept. These two methods are equivalent as they can generate the same output signals. Hardware implementation and measured results on this nonlinear switching filter are given. The simplicity of its design and its low cost will enable this type of nonlinear switching filter suitable for use in low bit rate satellite communication systems.