Path Delay Variations Research Articles

Deformation Estimation Using Beidou GEO-Satellite-Based Reflectometry

Deformation monitoring has been brought to the fore and extensively studied in recent years. Global Navigation Satellite System Reflectometry (GNSS-R) techniques have so far been developed in deformation estimation applications, which however, are subject to the influence of mobile satellites. Rather than compensating for the path delay variations caused by mobile satellites, adopting Beidou geostationary Earth orbit (GEO) satellites as transmitters directly eliminates the satellite-motion-induced phase error and thus provides access to stable phase information. This paper presents a novel deformation monitoring concept based on GNSS-R utilizing Beidou GEO satellites. The geometrical properties of the GEO-based bistatic GNSS radar system are explored to build a theoretical connection between deformation quantity and the echo carrier phases. A deformation retrieval algorithm is proposed based on the supporting software receiver, thus allowing echo carrier phases to be extracted and utilized in deformation retrieval. Two field validation experiments are conducted by constructing passive bistatic radars with reflecting plates and ground receiver. Utilizing the proposed algorithm, the experimental results suggested that the GEO-based GNSS reflectometry can achieve deformation estimations with an accuracy of around 1 cm when the extracted phases does not exceed one complete cycle, while better than 3 cm when considering the correct integer number of phase cycles. Consequently, based on the passive bistatic radar system, the potential of achieving continuous, low-cost deformation monitoring makes this novel technique noteworthy.

Critical Path Tube Redundancy for Power Minimization in CNFET Circuits With Variations

Tube redundancy and correlation has been proposed to increase the functional yield of CNFET-based circuits under CNT variations. However, adding redundant-CNTs is associated with increased power and sometimes increased area. The impact of CNT correlation on CNFET-based circuit performance also remains unexplored. Adding redundancy to all transistors in a circuit was considered in many works. In this paper, we propose adding an optimized number of redundant tubes only to transistors on critical paths. The optimized number of redundant-CNTs is pre-calculated for a desired functional yield. We show that this restricted redundancy retains the improved delay-limited yield achieved in circuits with redundant-CNTs added to all transistors. Moreover, this limited redundancy also reduces power dissipation without exceeding the allowed delay degradation. To ensure redundant tubes are added to all transistors on all critical paths which can emerge in all fabricated circuits due to CNT variations, those paths must first be identified. We propose an efficient method to identify all the critical paths that can exist in the presence of CNT variations. With uncorrelated-CNFETs, our approach reduces the average power increase by 7.8% as compared to all-transistor redundancy. Results also show an improvement in critical path delay by 15-20% and up to 10% reduction in allowed delay-degradation. To examine the influence of tube correlation on CNFET-based circuit performance, two correlated-CNFET standard-cell layouts are evaluated. An average increase of 1.8X in critical path delay variation due to CNFET correlation is noticed in a set of ISCAS'85 benchmarks.

Novel Prediction Framework for Path Delay Variation Based on Learning Method

Path delay variation becomes a serious concern in advanced technology, especially for multi-corner conditions. Plenty of timing analysis methods have been proposed to solve the issue of path delay variation, but they mainly focus on every single corner and are based on a characterized timing library, which neglects the correlation among multiple corners, resulting in a high characterization effort for all required corners. Here, a novel prediction framework is proposed for path delay variation by employing a learning-based method using back propagation (BP) regression. It can be used to solve the issue of path delay variation prediction under a single corner. Moreover, for multi-corner conditions, the proposed framework can be further expanded to predict corners that are not included in the training set. Experimental results show that the proposed model outperforms the traditional Advanced On-Chip Variation (AOCV) method with 1.4X improvement for the prediction of path delay variation for single corners. Additionally, while predicting new corners, the maximum error is 4.59%, which is less than current state-of-the-art works.

Low-Power Addition With Borrow-Save Adders Under Threshold Voltage Variability

It is well known that reduced logic depth allows for operation at low voltages, therefore reducing power dissipation. However, such circuits are particularly susceptible to variations, which may compromise expected benefits. This brief presents a solution for low-power addition under variability, which successfully handles the challenge of increased threshold voltage variation. Specifically, we quantitatively compare the impact of variation on the performance of ripple-carry adder (RCA) and borrow-save adder (BSA), quantify the average power reduction achieved by BSA attained at low voltage values, at the cost of increased delay variation, and propose a technique that enhances BSA tolerance to variations. Using statistical timing evaluation at the 45-nm and 32-nm nodes, we estimate the maximum critical path delay variation and average power dissipation of BSA at different supply voltages. Our analysis reveals that BSA achieves three times smaller standard deviation of maximum delay than RCA at the same supply voltage. In addition, we show that it is possible to substantially reduce the supply voltage, decreasing by almost 60% the overall power dissipation of BSA in comparison to a counterpart operating at nominal voltage while keeping maximum delay less than that of RCA. Furthermore, simple design optimizations in the design of BSA are introduced that trade latency for variability, significantly reducing normalized standard deviation of the maximum delay.

Novel Offset Techniques for Improving Bitstring Quality of a Hardware-Embedded Delay PUF

Statistical properties including uniqueness, randomness, and reproducibility are commonly used as metrics for physical unclonable functions (PUFs). When PUFs are used in authentication protocols, the first two metrics are critically important to the overall security of the system. In this paper, we investigate the statistical qualities of bitstrings generated by a hardware-embedded delay PUF called HELP using hardware data collected from a set of 500 Xilinx Zynq FPGAs. HELP analyzes variations in path delays that occur within a hardware-implemented macro. Two novel techniques are proposed in which the verifier computes a set of offsets that are used to fine tune the token’s digitized path delays as a means of maximizing entropy and reproducibility in the generated bitstrings. The offsets are derived from the enrollment data stored by the server in a secure database. A population-based offset method is proposed, which computes median values using data from multiple tokens. A second chip-specific technique is proposed, which fine tunes path delays using the stored enrollment data associated with the authenticating token. The analysis of FPGA data shows that the population-based offset method significantly improves entropy while the chip-specific technique, used alone or in combination with the population-based method, significantly improves reproducibility.

Leveraging Distributions in Physical Unclonable Functions

A special class of Physical Unclonable Functions (PUFs) referred to as strong PUFs can be used in novel hardware-based authentication protocols. Strong PUFs are required for authentication because the bit strings and helper data are transmitted openly by the token to the verifier, and therefore are revealed to the adversary. This enables the adversary to carry out attacks against the token by systematically applying challenges and obtaining responses in an attempt to machine learn, and later predict, the token’s response to an arbitrary challenge. Therefore, strong PUFs must both provide an exponentially large challenge space and be resistant to machine-learning attacks in order to be considered secure. We investigate a transformation called temperature–voltage compensation (TVCOMP), which is used within the Hardware-Embedded Delay PUF (HELP) bit string generation algorithm. TVCOMP increases the diversity and unpredictability of the challenge–response space, and therefore increases resistance to model-building attacks. HELP leverages within-die variations in path delays as a source of random information. TVCOMP is a linear transformation designed specifically for dealing with changes in delay introduced by adverse temperature–voltage (environmental) variations. In this paper, we show that TVCOMP also increases entropy and expands the challenge–response space dramatically.

A Privacy-Preserving, Mutual PUF-Based Authentication Protocol

This paper describes an authentication protocol using a Hardware-Embedded Delay PUF called HELP. HELP derives randomness from within-die path delay variations that occur along the paths within a hardware implementation of a cryptographic primitive, such as AES or SHA-3. The digitized timing values which represent the path delays are stored in a database on a secure server (verifier) as an alternative to storing PUF response bitstrings. This enables the development of an efficient authentication protocol that provides both privacy and mutual authentication. The security properties of the protocol are analyzed using data collected from a set of Xilinx Zynq FPGAs.

Voltage and Frequency Tuning Methodology for Near-Threshold Manycore Computing using Critical Path Delay Variation

Near-threshold computing (NTC) is now regarded as a promising candidate for innovative power reduction, which cannot be achieved with conventional super-threshold computing (STC). However, performance degradation and vulnerability to process variation in the NTC regime are the primary concerns. In this paper, we propose a voltage- and frequency-tuning methodology for mitigating the process-variation-induced problems in NTC-based manycore architectures. To implement the proposed methodology, we build up multiplevoltage multiple-frequency (MVMF) islands and apply a voltage-frequency tuning algorithm based on the critical-path monitoring technique to reduce the effects of process variation and maximize energy efficiency in the post-silicon stage. Experimental results show that the proposed methodology reduces overall power consumption by 8.2–20.0%, compared to existing methods in variation-sensitive NTC environments.

Within-Die Delay Variation Measurement and Power Transient Analysis Using REBEL

Variations in path delays are increasing with scaling, and are increasingly affected by neighborhood interactions. To fully characterize within-die variations, delays must be measured in the context of actual core-logic macros using embedded test structures (ETSs). In this brief, we propose an ETS called regional delay behavior (REBEL) that is designed to measure path delays in a minimally invasive fashion. REBEL provides capabilities similar to an off-chip logic analyzer. We implemented REBEL in a 90-nm test chip and present results on within-die path delay variations in a floating point unit. We also analyze the impact on delay when the chips are subjected to industrial-level temperature and voltage variations.

Clock Tree Synthesis Considering Slew Effect on Supply Voltage Variation

This work tackles a problem of clock power minimization within a skew constraint under supply voltage variation. This problem is defined in the ISPD 2010 benchmark. Unlike mesh and cross link that reduce clock skew uncertainty by multiple driving paths, our focus is on controlling skew uncertainty in the structure of the tree. We observe that slow slew amplifies supply voltage variation, which induces larger path delay variation and skew uncertainty. To obtain the optimality, we formulate a symmetric clock tree synthesis as a mathematical programming problem in which the slew effect is considered by an NLDM-like cell delay variation model. A symmetry-to-asymmetry tree transformation is proposed to further reduce wire loading. Experimental results show that the proposed four methods save up to 20% of clock tree capacitance loading. Beyond controlling slew to suppress supply-voltage-variation-induced skew, we also discuss the strategies of clock tree synthesis under variant variation scenarios and the limitations of the ISPD 2010 benchmark.

ASIC implementation of a hardware‐embedded physical unclonable function

Within-die variations in path delays are increasing with scaling. Although higher levels of within-die delay variations are undesirable from a design perspective, they represent a rich source of entropy for applications that make use of ‘secrets’, such as authentication, hardware metering and encryption. Physical unclonable functions or PUFs are a class of circuit primitives that leverage within-die variations as a means of generating random bitstrings for these types of applications. In this study, the authors present test chip results of a hardware-embedded delay PUF (HELP) that extracts entropy from the stability characteristics and within-die variations in path delays. HELP obtains accurate measurements of path delays within core logic macros using an embedded test structure called regional delay behaviour (REBEL). REBEL provides capabilities similar to an off-chip logic analyser, and allows very fast analysis of the temporal behaviour of signals emerging from paths in a core logic macro. Statistical characteristics related to the randomness, reproducibility and uniqueness of the bitstrings produced by HELP are evaluated across industrial-level temperature and supply voltage variations.

Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation

Power supply noise and ground bounce can cause considerable path delay variations. Capturing the worst case power supply noise at a gate level is not a sufficient indicator for measuring the worst case path delay. Furthermore, path delay variations depend on multiple parameters such as input stimuli, cell placement, switching frequency, and available decoupling capacitors. All these variables obscure the rapport between supply noise and path delay and make the selection of stimuli for worst case path delay a difficult task during test pattern generation. In this paper, we utilize power supply noise and ground bounce distribution along with physical design data to generate test patterns for capturing worst case path delay. We propose accurate close-form mathematical models for capturing the effect of power supply noise and ground bounce on path delay. These models are based on modified nodal analysis formulation of power and ground networks, where current waveforms are obtained from levelized simulation and cell library characterization. The proposed test pattern generation flow is a simulated-annealing-based iterative process, which utilizes mathematical models for capturing the impact of supply noise on path delay for a given input pattern. We perform experiments on ITC'99 benchmarks and show that path delay variation can be considerable if test patterns are not properly selected.

Parameterizing both path amplitude and delay variations of underwater acoustic channels for block decoding of orthogonal frequency division multiplexing

There are no commonly-agreed mathematical models for the input-output relationship of underwater acoustic channels. For each path in a time-varying multipath channel within a short period of time (e.g., one short data block), this paper proposes to use one polynomial to approximate the amplitude variation and another polynomial up to the first order to approximate the delay variation within a block duration. Under such a channel parameterization, the discrete-time channel input- output relationship tailored to zero-padded orthogonal-frequency-division-multiplexing (OFDM) transmissions is then derived, based on which an OFDM receiver is validated using experimental data collected during the 2008 Surface Processes and Acoustic Communications Experiment. For channels with a short coherence time, the numerical results show that incorporating both the amplitude and delay variations improves the system performance.

Three-Dimensional Humidity Retrieval Using a Network of Compact Microwave Radiometers to Correct for Variations in Wet Tropospheric Path Delay in Spaceborne Interferometric SAR Imagery

Spaceborne interferometric synthetic aperture radar (SAR) (InSAR) imaging has been used for over a decade to monitor tectonic movements and landslides, as well as to improve digital elevation models. However, InSAR is affected by variations in round-trip propagation delay due to changes in ionospheric total electron content and in tropospheric humidity and temperature along the signal path. One of the largest sources of uncertainty in estimates of tropospheric path delay is the spatial and temporal variability of water vapor density, which currently limits the quality of InSAR products. This problem can be partially addressed by using a number of SAR interferograms from subsequent satellite overpasses to reduce the degradation in the images or by analyzing a long time series of interferometric phases from permanent scatterers. However, if there is a sudden deformation of the Earth's surface, the detection of which is one of the principal objectives of InSAR measurements over land, the effect of water vapor variations cannot be removed, reducing the quality of the interferometric products. In those cases, high-resolution information on the atmospheric water vapor content and its variation with time can be crucial to mitigate the effect of wet-tropospheric path delay variations. This paper describes the use of a ground-based microwave radiometer network to retrieve 3-D water vapor density with fine spatial and temporal resolution, which can be used to reduce InSAR ambiguities due to changes in wet-tropospheric path delay. Retrieval results and comparisons between the integrated water vapor measured by the radiometer network and satellite data are presented.

Crosstalk-Induced Delay, Noise, and Interconnect Planarization Implications of Fill Metal in Nanoscale Process Technology

In this paper, we investigate the crosstalk-induced delay, noise, and chemical mechanical polishing (CMP)-induced thickness-variation implications of dummy fill generated using rule-based wire track fill techniques and CMP-aware model-based methods for designs implemented in 65 nm process technology. The results indicate that fill generated using rule-based and CMP-aware model-based methods can have a significant impact on parasitic capacitance, interconnect planarization, and individual path delay variation. Crosstalk-induced delay and noise are significantly reduced in the grounded-fill cases, and designs with floating fill also experience a reduction in average crosstalk-induced delay and noise, which is in contrast to the predictions of previous studies on small-scale interconnect structures. When crosstalk effects are included in the analysis, the observed delay behavior is significantly different from the delay modeled without considering crosstalk effects. Consequently, crosstalk-induced delay and noise must be simultaneously considered in addition to parasitic capacitance and interconnect planarization when developing future fill generation methods.

A Novel Fault Localization Technique Based on Deconvolution and Calibration of Power Pad Transients Signals

This paper describes a new fault localization method that is based on the analysis of power supply transient signals. Impulse response functions derived from the power grid are used to de-construct the measured power port transient signals into a set of gate level transients generated by the logic gates as signals propagate along paths in the circuit. By comparing these gate transients with those obtained from a defect-free chip or simulation model, it is possible to identify anomalies produced by defects and to locate them to specific path segments in the layout. Impulse response functions are used to significantly reduce both the attenuation effects of the power grid on the gate-generated transients and the chip-to-chip impedance variations in the power grid and test environment. Non-linear calibration techniques are proposed to reduce the chip-to-chip variations in path delays introduced by process variations. The procedure is demonstrated using simulation experiments to locate the position of defects to one or a small group of gates.

Analytical Estimation of Path-Delay Variation for Multi-Threshold CMOS Circuits

Circuits utilizing advanced process technologies have to correctly account for device parameter variation to optimize its performance. In this paper, analytical formulas for evaluating path delay variation of Multi-Threshold CMOS (MTCMOS) circuits are proposed. The proposed formulas express path delay and its variation as functions of process parameters that are determined by fabrication technology (threshold voltage, carrier mobility, etc.) and the circuit parameters that are determined by circuit structure (equivalent load capacitance and the concurrently switching gates). Two procedures to obtain the circuit parameter sets necessary in the calculation of the proposed formulas are also defined. With the proposed formulas, calculation time of a path delay variation becomes three orders faster than that of Monte-Carlo simulation. The proposed formulas are suitably applied for efficient design of MTCMOS circuits considering process variation.

Formation Pointing Dynamics of Tether-Connected Architecture for Space Interferometry

The baseline pointing dynamics, i.e., the attitude of the instantaneous plane of rotation, of a linear tethered interferometer with single baseline orbiting in an Earth trailing, heliocentric orbit is analyzed. Two tether arms provide a passive control of the spacecraft formation by keeping two light collectors and one combiner aligned while spinning about the boresight of the interferometer. The interferometer optical path delay variation under gravity gradient perturbation and unbalanced solar radiation torque is investigated analytically for a fixed-length dumbbell model. Analytical results are compared with results from numerical simulations of a visco-elastic massive tether model in order to assess the effect of the tether dynamics on the pointing stability of the formation. The study highlights the fundamental role of spin stabilization in counteracting the effect of external perturbation on the interferometer Optical Path Delay (OPD).

Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits

In this paper we address both empirically and theoretically the impact of an advanced manufacturing phenomenon on the performance of high-speed digital circuits. Using data collected from an actual state-of-the-art fabrication facility, we conducted a comprehensive characterization of an advanced 0.18-/spl mu/m CMOS process. The measured data revealed a significant systematic, rather than random spatial intrachip variability of MOS gate length, leading to large circuit path delay variation. The delay of the critical path of a combinational logic block varies by as much as 17%, and the global skew is increased by 8%. Thus, a significant timing error and performance loss takes place if variability is not properly addressed. We derive a model, which allows estimating performance degradation for the given circuit and process parameters. We demonstrate explicitly that intrachip Lgate variation has a significant detrimental impact on the overall circuit performance, shifting the entire distribution of clock frequencies toward slower values. This is in striking contrast to the impact of interchip Lgate variation, traditionally considered in statistical circuit analysis, which leads to the variation of chip clock frequencies around the average value. Moreover, analysis shows that the spatial, rather than proximity-dependent systematic Lgate variability, is the main cause of large circuit speed degradation. The degradation is worse for the circuits with a larger number of critical paths and shorter average logic depth. We propose a location-dependent timing analysis methodology that allows mitigation of the detrimental effects of Lgate variability and have developed a tool linking the layout-dependent spatial information to circuit analysis. We discuss the details of practical implementation of the methodology, and provide guidelines for managing design complexity.

GPS site testing at chajnantor in Chile

We present first results on the site coordinates and the atmospheric propagation delay parameters from the permanent Global Positioning System site established at Chajnantor, in the Chilean Andes, at 5000 m altitude. The site is designed to ensure a long-term monument stability. The primary reason behind the site establishment is the future construction of the Atacama Large Millimeter Array (ALMA), a radio astronomy facility, at the same location. There is an interest to observe the site coordinate stability as well as the total radio propagation path delay variations which is possible employing the GPS technique. The fact that the site is known to have mainly a dry delay component makes it also a unique site for GPS accuracy studies. We present first results on the estimated site coordinates and the zenith total and wet atmospheric delays. Structure function results of the delays are included as well as the impact of using different elevation cut off angles in the data processing. We also discuss the performance of the mapping functions used for the estimation of the zenith delay terms.