Path Delay Faults In Circuits Research Articles

Test enrichment for path delay faults using multiple sets of target faults

Test sets for path delay faults in circuits with large numbers of paths are typically generated for path delay faults associated with the longest circuit paths. It is shown that such test sets may not detect faults associated with the next-to-longest paths. This may lead to undetected failures since shorter paths may fail without any of the longest paths failing. In addition, paths that appear to be shorter may actually be longer than the longest paths if the procedure used for estimating path length is inaccurate. A test enrichment procedure is proposed that increases significantly the number of faults associated with the next-to-longest paths that are detected by a test set without increasing its size. This is achieved by targeting both types of faults, but ensuring that the test generation procedure would detect the faults associated with the longest paths, while allowing the procedure the flexibility of detecting or not detecting the faults associated with the next-to-longest paths. The proposed procedure thus improves the quality of the test set without increasing its size. The test enrichment procedure is built on top of a new and effective dynamic test compaction procedure in order to demonstrate that test enrichment is effective even for compact test sets.

A statistical methodology for modeling and analysis of path delay faults in VLSI circuits

Due to the rapid development of semiconductor technology, the complexity of VLSI circuits has dramatically increased. Testing such circuits is becoming a severe problem. With the increased densities of integrated circuits, several different types of faults can occur. Faults in digital circuits which result from random defects can introduce DC (stuck-at) faults as well as AC (delay) faults. Previous work in statistical modeling and analysis for delay fault testing generally assumes that at most a single delay fault can occur along any given path in the circuit under test (Shelly, J. H. and Trayon, D. R., Statistical techniques of timing verification. In Proc. 20th Design Automation Conf., 1983, pp. 396–402; Tendokar, N. N., Analysis of timing failures due to random AC defects in VLSI circuits. In Proc. 22nd Design Automation Conf., 1985, pp. 709–714; Park, E. S., Mercer, M. R. and Williams, T. W., A statistical model for delay fault testing. IEEE Design and Test of Computers, 1989, February, 45–55). In this paper we investigate the statistical effect of multiple delay faults along any path in a circuit under test, and predict the path delay fault probabilities as well as the maximum number of path delay faults for both combinational and sequential benchmark circuits. We begin with the development of a statistical model for path delay faults in VLSI circuits (Hamad, M. and Landis, D., A statistical model for path delay faults in VLSI circuits. In Proc. IEEE South East Conf., April 1996, pp. 388–392) which takes into account multiple delay faults along any signal path. We define and compute the path delay fault probabilities for all paths in a circuit; the single fault assumption is only a special case of our path delay fault model. Furthermore, we demonstrate how our statistical model is used to predict such important information as the maximum number of path delay faults in a circuit. Finally, we show that when multiple faults are considered during circuit analysis, the path delay fault probability, pp, and not the delay defect probability, p, should be used in the evaluation of system parameters such as statistical delay fault coverage, yield, and AC quality level.

Test generation for path delay faults using binary decision diagrams

A new test generation technique for path delay faults in circuits employing scan/hold type flip-flops is presented. Reduced ordered binary decision diagrams (ROBDDs) are used to represent Boolean functions realized by all signals in the circuit, as well as to represent the constraints to be satisfied by the delay fault test. Two faults are considered for each path in the circuit. For each fault, a pair of constraint functions, corresponding to the two time frames that constitute a transition, is evaluated. If the constraint function in the second time frame is non-null, robust-hazard-free-test generation for the delay fault is attempted. A robust test thus generated belongs either to the class of fully transitional path (FTP) tests or to the class of single input transition (SIT) tests. If a robust test cannot be found, the existence of a non-robust test is checked. Boolean algebraic manipulation of the constraint functions guarantees that if neither robust nor non-robust tests exist, the fault is undetectable. In its present form the method is applicable to all circuits that are amenable to analysis using ROBDDs. An implementation of this technique is used to analyze delay fault testability of ISCAS '89 benchmark circuits. These results show that the algebraic technique is one to two orders of magnitude faster than previously reported methods based on branch-and-bound algorithms.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>