Passive High-pass Filter Research Articles

Penggunaan Virtual lab. Circuit Wizard Untuk Simulasi Rangkaian High Pass Filter Pasif

Passive High Pass Filter will be discussed in this paper; the filter itself is a circuit that determines the amount of a certain frequency to be streamed and will reject frequencies that are not suitable. Meanwhile, a passive filter is an electrical circuit that can block intervals at certain signal frequencies to filter incoming signals. The benefit of passive filters is that they can be used at higher frequencies because their dimensions are larger than active filters. Measurement of the voltage gain in the Passive High Pass Filter circuit using laboratory methods using a simulation approach with the Circuit Wizard simulator or directly. The research method consists of two experimental scenarios that aim to compare the signals generated from stage I to stage V. For the scenario I, the simulation is carried out using the Circuit Wizard simulator. The capacitor is one of the reactive components that will offer a variety of resistance to different frequency signals based on a High Pass RC Filter circuit with a capacitor that has a high value of resistance to low frequencies or resistance to high-frequency transmissions will be minimal. The capacitor feature makes it resistant to low-frequency or DC signals, so only high-frequency signals can travel through the capacitor and block the path of low-frequency impulses. The high pass filter can attenuate or maintain low frequencies below the cut-off frequency while passing high signal frequencies or passing signals above them.

A 1.45-pJ/b 16-Gb/s Edge-Based Sub-Baud-Rate Digital CDR Circuit

A 16-Gb/s edge-based sub-baud-rate digital clock and data recovery (CDR) circuit is presented. By using the proposed edge-based sub-baud-rate technique and a passive high-pass filter, the complementary clocks are used to save the power. To improve the jitter tolerance, the intrinsic delay of the high-pass filter is compensated by using compensation delay cells. The proposed sub-baud-rate CDR circuit is fabricated in 40-nm CMOS technology. Its active area is 0.0376mm2 and the power is 23.2mW for a supply of 1.2V at the data rate of 16 Gb/s. The calculated energy efficiency of this CDR circuit is 1.45 pJ/b.

A PVT-Robust AFE-Embedded Error-Feedback Noise-Shaping SAR ADC With Chopper-Based Passive High-Pass IIR Filtering for Direct Neural Recording.

This paper presents a PVT-robust error-feedback (EF) noise-shaping SAR (NS-SAR) ADC for direct neural-signal recording. For closed-loop bidirectional neural interfaces enabling the next generation neurological devices, a wide-dynamic-range neural recording circuit is required to accommodate stimulation artifacts. A recording structure using an NS-SAR ADC can be a good candidate because the high resolution and wide dynamic range can be obtained with a low oversampling ratio and power consumption. However, NS-SAR ADCs require an additional gain stage to obtain a well-shaped noise transfer function (NTF), and a dynamic amplifier is often used as the gain stage to minimize power overhead at the cost of vulnerability to PVT variations. To overcome this limitation, the proposed work reutilizes the capacitive-feedback amplifier, which is the analog front-end of the neural recording circuit, as a PVT-robust gain stage to achieve a reliable NS performance. In addition, a new chopper-based implementation of a passive high-pass IIR filter is proposed, achieving an improved NTF compared to prior EF NS-SAR ADCs. Fabricated in a 180-nm CMOS process, the proposed NS-SAR ADC consumes 4.3-μW power and achieves a signal-to-noise-and-distortion ratio (SNDR) of 71.7 dB and 82.7 dB for a bandwidth of 5 kHz and 300 Hz, resulting in a Schreier figure of merit (FOM) of 162.4 dB and 162.1 dB, respectively. Direct neural recording using the proposed NS-SAR ADC is demonstrated successfully in vivo, and also its tolerance against stimulation artifacts is validated in vitro.

Numerical Analysis of Filtering Circuit for Partial Discharges

Partial Discharge (PD) is a small electrical spark that happens within the insulation of medium and high voltage electrical assets. It is important to note that the discharge will erode the insulation and eventually result in disastrous insulation failure. Thus, PD detection is a crucial issue in high voltage insulation area. However, the on-site field PD tests, the high frequency PD signals detected by sensors, are vulnerable to interferences and background noises. This has a negative effect on high voltage apparatus fault diagnosis and localization accuracy. For that reason, noise suppression has become an urgent and vital issue for field high frequency PD signal testing. Thus, this research aims to model a filtering circuit to suppress the noise along with PD in high frequency measurement. A filtering circuit was analysed by using Proteus software to filter out the noise along with PD with decent accuracy and efficiency. Then, performance investigation of active high pass and passive high pass was conducted and studies to filter out PD noise suppression in high frequency were successfully developed. The active filter was focusing on the first order stage until fourth order stage. The passive filter only concentrated on two types of order stage; first order stage and second order stage. The result demonstrated that active high pass filter presented the best performance with low decibel frequency response (-20 dB), and was suitable for this research purpose compared to passive high pass filter. Besides, 700 Vrms has been selected to check the response at high voltages and the frequency values set at 50 Hz for low frequency and 8 kHz for high frequency. This specification design values have been selected because it is suitable for situations in high-tension power line. This type of filtering circuit is suitable to be used for academic and lab experimentation.

Performance Limits of Generalized Sampling Based 2-Channel Analog-to-Digital Converter

This brief proposes an analog-to-digital converter (ADC) based on Generalized Sampling Theorem and derives a closed form expression of its performance, viz., signal-to-quantization noise ratio (SQNR) and alias-suppression (AS). The ADCs in the 2-channels sample the signal and its filtered version, respectively, at half the Nyquist rate. The outputs of the two ADCs are upsampled by a factor of 2, passed through appropriate reconstruction filters, and then added to give an effective sample-rate which is double that of the sample-rate of each channel ADC. Performance of the proposed ADC has been summarized for simple filters like differentiator, integrator, passive RC low-pass filter, and passive CR high-pass filters. The proposed ADC could therefore be used as an alternative to other popular ADC structures like time-interleaved, frequency-interleaved, and filter-bank ADCs, to achieve high sample-rate with minimal analog circuit overhead.

Interference mechanism analysis and mitigation measures with railway signalling equipment from harmonics in the traction system

Abstract With the development of high-speed railway and heavy-haul rail transport in China, a large number of new types of electric locomotives and electric multiple units have been put into operation, improving the efficiency and equipment quality of railway transportation. However, harmonics emitted from the traction system and locomotives often interfere with the railway signalling equipment, which can lead to critical malfunction of the equipment. Based on field test data, this paper analyses the interference coupling mechanism and magnitude of traction harmonics to the signalling equipment using a three-element method of interference. It examines the three essential elements of electromagnetic interference, studies harmonic mitigation measures and proposes to solve the problem of inteference with signalling equipment by installing a passive high-pass filter in the coupling path. After comparing the effects of several types of filters using simulation tests, this paper verified the validity of the method and concluded that a second-order passive filter is the optimal solution for harmonic interference mitigation.

Development of tunable filters using self-folding technology

This paper seeks to demonstrate the functionality and verify the capabilities of capacitance adjustment by a self-folding device. The self-folding devices using polyvinyl chloride (PVC) shrink wrap and copper foil tapes with predefined creases were fabricated. By modifying a simple self-folding device and exposing it to a temperature between 50 to 90 degrees Celsius, the capacitor plates could be angled from 15 to 90 degrees. As a result, the capacitance changed as the inner angle decreased, from only 0.724 picofarads measured at 90 degrees, to 2.27 picofarads measured at 15 degrees. With the capacitance for each angle obtained, the next phase of development was conducted, to determine the tune-ability using a passive high pass filter. By scaling up the number of self-folding capacitors to thirty times, a cut-off frequency of 4.99 kHz at 15 degrees up to 7.25 kHz at 75 degrees was measured. As a result, this paper’s unique way of turning a self-folding device into a capacitor demonstrates great potential for development of tunable filters using capacitance adjustment and self-folding.

Design of Analog Front-end Circuit for Audio-frequency Magnetotelluric Instrument

High-performance audio-frequency magnetotelluric (AMT) instrument is one means of obtaining high-quality electromagnetic (EM) data. To improve the ability of AMT system to obtain high-quality data, this paper presents a design for a high-performance analog front-end circuit for AMT instrument. It mainly consists of the input protection, preamplifier, passive high pass filter, power frequency notch filter, programmable amplifier, and active low pass filter. In addition, this paper proposes a design of low-noise, high-performance preamplifier, which improves the common-mode rejection ratio (CMRR) of analog front-end circuit and effectively enhances the signal-to-noise ratio (SNR) of the circuit. The front-end circuit utilized two-stage twin-T notch filter to effectively suppress the strong interference of fundamental component of power frequency. Also, it used signal relays to control circuit gain and selection of cutoff frequency of anti-aliasing filter, resulting in the improvement of the capability of the analog-to-digital Converter (ADC) to distinguish weak EM signal. The measured results of the electric field and magnetic field channel showed that: 1) The circuit works in frequency range of 1 Hz∼100 kHz; 2) The CMRR values of the preamplifier of electric field channel at low frequencies (1 Hz∼1 kHz) are 111 dB and 97 dB when the gains are 20 dB and 6 dB respectively; 3) The maximum attenuation fundamental power frequency can reach −39.46 dB and −39.04 dB respectively; 4) The total harmonic distortion rate at 1 kHz is 0.022% and 0.029% respectively; 5) The input noise levels of electric field channel are 12.67nV / [Formula: see text] @10Hz and 8.15V / [Formula: see text] @1kHz, while the input noise levels of magnetic field channel are 8.97nV / [Formula: see text] @10Hz and 6.16V / [Formula: see text] @1kHz; and 6) In conclusion, the analog front-end circuit is superior to meet the requirements of the AMT methods, and provides a useful reference for the development of AMT instrument.

A Digital Filtering ADC With Programmable Blocker Cancellation for Wireless Receivers

This paper presents a long-term evolution (LTE) receiver (RX) front end with a digital filtering analog to digital converter (ADC) in the baseband to perform multi-band blocker cancellation. The digital filtering ADC has a digitally defined transfer function that is highly reconfigurable and insensitive to PVT variations. The dynamic range requirement of the blocker cancellation feedback digital to analog converter (DAC) is relaxed with a trivial uncalibrated first-order passive high-pass filter. The programmable digital filter provides 34.9-dB attenuation of transmitter leakage and variable attenuation of an additional blocker anywhere in the frequency range 17.5–107.5 MHz. A blocker detection algorithm for this RX is presented and takes approximately 26 $\mu \text{s}$ to converge. The RX front end operates at 1.8 GHz with a noise figure of 3.9 dB and IIP3 of −5 dBm, and consumes only 20.4–37.5 mW, the lowest among the state-of-the-art designs.

NeuroMonitor: a low‐power, wireless, wearable EEG device with DRL‐less AFE

Electroencephalography (EEG) is an effective tool to non-invasively capture brain responses. Traditional EEG analogue front end (AFE) requires a driven right leg (DRL) circuit that restricts the number of channels of the device. The authors are proposing a new `DRL-less' AFE design, and have developed a wearable EEG device (NeuroMonitor), which is small, low-power, wireless, and battery operated. The EEG device with two independent channels was fabricated on an 11.35 cm 2 PCB that contained a system-on-a-chip microcontroller, a low-noise instrument amplifier, a low-power Bluetooth module, a microSD, a microUSB, and a LiPo battery. The DRL circuit was eliminated by utilising the high CMRR instrument amplifier with differential inputs, and followed by a modified high-Q active Twin-T notch filter (( f c Notch = 60 Hz, -38 dB). The signal was conditioned with a band-pass filter composed of a two-stage 2nd-order Chebyshev-I Sallen-Key low-pass filter cascaded with a passive 2nd-order low-pass filter ( f c LP = 125 Hz) and a 1st-order passive high-pass filter ( f c HP = 0.5 Hz). Finally, the signal was amplified to achieve an overall gain of 55.84 dB, and digitised with a 16-bit delta-sigma ADC (256 sps). The prototype weighs 41.8 gm, and has been validated against a research-grade EEG system (Neuroscan).

Bulk silicon micromachined suspended fixed-end SiO2 film capacitor for passive high-pass RC filter

We reported a suspended fixed-end 5 μm thin SiO2 film beam and plate MEMS capacitor for passive high-pass RC filter. This suspended structure was fabricated using bulk silicon two-sided alignment micromachining technology. The dynamic model included both a first order derivative of a high-pass filter electrical system and MEMS variable capacitors driven by electrostatic force. The room temperature experiment showed that the MEMS high-pass filter circuit can convert a rectangular wave input signal into high frequency spikes at its output. Finite element calculating software COMSOL and numerical simulation MATLAB were both used to evaluate the motion modal and the output voltage. Compared with the commercial static capacitor in a high-pass filter, we could also find that the coupling of the electrostatic force and dynamic motion of the electrode plate in the designed single device and dual-device could show an asymmetric offset voltage electrical response.

Design and validation of a wearable "DRL-less" EEG using a novel fully-reconfigurable architecture.

The conventional EEG system consists of a driven-right-leg (DRL) circuit, which prohibits modularization of the system. We propose a Lego-like connectable fully reconfigurable architecture of wearable EEG that can be easily customized and deployed at naturalistic settings for collecting neurological data. We have designed a novel Analog Front End (AFE) that eliminates the need for DRL while maintaining a comparable signal quality of EEG. We have prototyped this AFE for a single channel EEG, referred to as Smart Sensing Node (SSN), that senses brain signals and sends it to a Command Control Node (CCN) via an I2C bus. The AFE of each SSN (referential-montage) consists of an off-the-shelf instrumentation amplifier (gain=26), an active notch filter fc = 60Hz), 2nd-order active Butterworth low-pass filter followed by a passive low pass filter (fc = 47.5 Hz, gain = 1.61) and a passive high pass filter fc = 0.16 Hz, gain = 0.83). The filtered signals are digitized using a low-power microcontroller (MSP430F5528) with a 12-bit ADC at 512 sps, and transmitted to the CCN every 1 s at a bus rate of 100 kbps. The CCN can further transmit this data wirelessly using Bluetooth to the paired computer at a baud rate of 115.2 kbps. We have compared temporal and frequency-domain EEG signals of our system with a research-grade EEG. Results show that the proposed reconfigurable EEG captures comparable signals, and is thus promising for practical routine neurological monitoring in non-clinical settings where a flexible number of EEG channels are needed.

Comprehensive Background Calibration of Time-Interleaved Analog-to-Digital Converters

A dynamic path-mismatch calibration operating on direct derivative information (DDI) augments the reference-path equalization technique of that treats static mismatch errors in time-interleaved (TI) analog-to-digital converters (ADC). The approach results in a comprehensive background calibration of interleaved ADC arrays suitable for digitizing wideband inputs. The DDI of the analog input is produced by a passive high-pass filter (HPF) followed by a zero-crossing comparator, and subsequently utilized in the process to extract the dynamic mismatch profiles of the TI conversion paths, i.e., timing skew, bandwidth mismatch, etc. A zero-forcing algorithm drives the adaptive tuning procedures of the converter front-end circuits to eliminate the mismatch errors at source. The non-idealities of the DDI circuitry and their impact on the calibration performance are discussed. Behavioral simulation of an 8-bit, 20-GS/s TI-ADC reveals that signal-to-noise plus distortion ratio (SNDR) and spurious-free dynamic range (SFDR) over 47 dB and 70 dB, respectively, can be routinely obtained for single-tone inputs from DC to Nyquist after calibration, demonstrating the efficacy of the proposed technique.

A Breakage-Stop System for Linen Wet Spinning Frame

A multi-way control system for spun yarn breakage detecting and tow stopping is presented for linen wet spinning frame upgrade in medium-sized businesses of southeastern China. The signals from periodic rotations of spun yarns are picked by piezoelectric sensors. After input protection and multiplexers, the weak voltage signal from gated channel is processed through links including voltage following, passive high-pass filter, active low-pass filter, in-phase and reversedphase proportional amplifying, precision full-wave rectification, retardation voltage comparison, etc.. After regulated at a zener diode link, the final electrical level is sent to LPC2132 processor which gives trigger signals to actuators when yarn breakage is detected. In the corresponding actuator channel, armature of electromagnet will be pushed off to stop tow feed and the red LED will be lightened to warn spinner. Circuit board units for signal amplifying, conditioning and actuator driving were designed for controlling 24 yarn channels simultaneously. The simulation result and field test verified the circuit accuracy and programmed effectiveness.

Comparison of Nonuniform Transmission Lines With Gaussian and Exponential Impedance Profiles for $Z$-Pinch

The circuit simulation of nonuniform transmission lines that were under consideration for the next generation of petawatt-class <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$Z$</tex></formula> -pinch drivers was performed. It was confirmed that the power-transport efficiency of the designed radial transformer with an exponential impedance profile is higher than that with Gaussian profiles. Based on Fourier's theorem and the principle of superposition, it was found that there are considerable low-frequency components for the input voltage of a half-sine wave with an angular frequency of 14 Mrad/s. Compared with the exponential transformer, the Gaussian transformers amplify the low-frequency components to a lower extent, which makes the difference in power efficiency between the two types of transformers. The radial transformer also serves as a passive high-pass filter, and the Gaussian transformer may give better performance than the exponential transformer does if the signal transport rather than the power transport is concerned.

A novel SFG structure for C-T high-pass filters

A signal flow graph (SFG) structure for simulating passive high-pass ladder filters, called the incremental integration structure, is proposed. The structure requires the use of integrators with nonintegrating inputs, and an implementation based on the MOSFET-C technique is discussed. The incremental integration structure is compared to the leapfrog and direct SFG simulation structures. Leapfrog high-pass filters are relatively simple and show good noise properties, but they are based on differentiators and thus stability problems exist. The direct SFG simulation method is based on integrators and has good stability properties, but it leads to a relatively high circuit complexity and a high noise level. However, the incremental integration structure inherits the low-noise properties of the leapfrog structure and the good stability of the direct SFG simulation method. A sixth-order elliptic high-pass filter chip with a passband frequency of 3.0 kHz has been manufactured, and measurements support the validity of the approach.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>