Passive Equalizer Design Research Articles

A Wide-Band Passive Equalizer Design Approach for Improving the Gain Flatness With Multiple Peaks

This article proposes a new design approach of the wideband passive equalizer for improving the gain flatness with multiple peaks which often appears in the modern transmitter systems, and the general design formulas of this passive equalizer under different practical circumstances are obtained through theoretical analysis. The proposed equalizer mainly adopts multi-stage RCL series or parallel resonant circuit structure. According to the actual multi-peak gain flatness, the structure of the single-stage equalizer, the combination mode of each stage, and the required number of stages can be determined. The proposed equalizer can design the equalization frequency, bandwidth and attenuation flexibly according to the actual situation. Finally, the proposed design approach has been well verified by experimental tests of two four-stage broadband passive equalizers with different structures operating in 0.5-2 GHz.

A Passive Equalizer Design for Shielded Differential Through-Silicon Vias in 3-D IC

This letter develops a simplified circuit model for the shielded differential through-silicon vias (SD-TSVs). The model is consisted of four frequency-independent elements and can accurately predict the insertion loss of the SD-TSVs up to 20 GHz. Based on the model, a parallel resistor–capacitor equalizer is proposed. The proposed passive equalizer achieves wide-band equalization and perfect compensation for high-speed differential signaling.

A Passive Equalizer Optimization Method Based on Time-Domain Inter-Symbol Interference (ISI) Cancellation Technique

In this letter, a channel loss equalization method based on a time-domain inter-symbol interference (ISI) cancellation technique for passive interconnects is proposed. The proposed method can be applied to conventional passive equalizer designs that intentionally suppress the low-frequency and dc components of passive channel responses to compensate for the frequency-dependent losses. An R–L passive equalizer design composed of surface mount inductors and a resistor was employed for validation of the proposed method. With the proposed channel equalization method, it was demonstrated that the ISIs were successfully removed with a significantly improved eye-opening and timing margin.

A Compact Passive Equalizer Design for Differential Channels in TSV-Based 3-D ICs

In this paper, a compact passive equalizer for differential transmission channel is designed in TSV-based three-dimensional integrated circuits (3-D ICs). The compact size of the equalizer is achieved by a square shunt metal line. Three simplified odd-mode half circuit models are proposed for ground-signal-signal-ground (G-S-S-G) type TSVs, differential on-interposer interconnects, and differential channels, respectively. Those simplified models merely consist of frequency-independent elements and can accurately predict the differential insertion losses up to 20 GHz. Moreover, the electrical parameters of the proposed serial resistance-inductance ( RL ) type equalizers are derived from the system transfer functions and optimized by virtue of the time-domain inter-symbol interference cancellation technique. Further, the geometrical parameters of the RL equalizers are calculated by using a genetic algorithm based multi-objective optimization method. Finally, the performance of the designed RL equalizer is validated by both frequency- and time-domain simulations for 20 Gb/s high-speed differential signaling.

Passive Equalizer Design for Through Silicon Vias With Perfect Compensation

This paper proposes a novel passive equalizer which is composed of a parallel resistance-capacitance (RC) circuit and capable of perfect compensation for lossy effects of through silicon via (TSV). To design the equalizer, the conventional transmission line theory is utilized to derive an analytic circuit model of the TSV which is verified by numerical methods. Based on the analytic circuit model, the significance analysis is performed to acquire a much simplified capacitance-conductance circuit model which is employed to construct the design formula for the RC equalizer with perfect compensation. A ten-stacked TSV in series with the designed equalizer is taken as an example to demonstrate the resultant improvement in the eye diagram, namely, nearly zero timing jitter and three times enlarged eye opening.

A Compact and Wide-Band Passive Equalizer Design Using a Stub With Defected Ground Structure for High Speed Data Transmission

A compact wide-band passive equalization design using a stub with defected ground structure is proposed. The proposed design, based on reflections under a slow wave effect, compensates for inter-symbol interference with wide bandwidth, compact size, remarkable compensation capability with few manufacturing limitations, and high design flexibility, compared to previous equalization design. Significant improvements in eye-opening and timing jitter are successfully demonstrated for a data rate of 8 Gbps for a 60 cm transmission line on a printed circuit board.

A Wide-Band Passive Equalizer Design on PCB Based on Near-End Crosstalk and Reflections for 12.5 Gbps Serial Data Transmission

We propose a wide-band passive equalization method for high-speed serial chip-to-chip input/output channels using wave propagation, reflection, and coupling effects on a tightly coupled transmission line structure. This design offers precise control of wideband equalization and low-power consumption as compared to previous active and discrete passive equalizers. Significant improvements in timing jitter and voltage margin are successfully demonstrated for a data rate of 12.5 Gbps on a 40 cm long backplane printed circuit board.