Integration Of Passive Components Research Articles

Hexagonal ferrites for self-biasing circulators integrated in LTCC microwave modules

Next-generation microwave LTCC modules for satellite communication systems require the integration of passive components including circulators to manipulate electromagnetic signals at high frequency. Substituted M-type hexagonal ferrites (Ba/Sr)ScxFe12−xO19 are applied as self-biasing microwave magnetic materials at frequencies of about 30 GHz. The ferrites are integrated into LTCC multilayer devices as sintered drop-in bulk samples. Sintered ferrites with preferential orientation of grains were fabricated by compaction of powders in a magnetic field and sintering at 1300 °C. Alternatively, screen-printed ferrite films were dried in an external magnetic field, and cofired at 900 °C. The magnetic texture of the ferrites is characterized using XRD, EBSD, and magnetic measurements. Integrated Y-type circulators were tested and exhibit non-reciprocal behavior. This indicates that hexagonal ferrites are promising candidates for self-biasing circulators embedded in LTCC microwave modules operating at Ka-band frequencies at around 30 GHz.

Tunable organic active neural probe enabling near-sensor signal processing.

Neural recording systems have significantly progressed to provide an advanced understanding and treatment for neurological diseases. Flexible transistor-based active neural probes exhibit great potential in electrophysiology applications due to their intrinsic amplification capability and tissue-compliant nature. However, most current active neural probes exhibit bulky back-end connectivity since the output is current, and the development of an integrated circuit for voltage output is crucial for near-sensor signal processing at the abiotic/biotic interface. Here, wepresent inkjet-printed organic voltage amplifiers by monolithically integrating organic electrochemical transistors and thin-film polymer resistors on a single, highly flexible substrate for in vivo brain activity recording. Additive inkjet printing enables the seamless integration of multiple active and passive components on the somatosensory cortex, leading to significant noise reduction over the externally connected typical configuration. It also facilitates fine-tuning of the voltage amplification and frequency properties. Wevalidate the organic voltage amplifiers as electrocorticography devices in a rat in vivo model, showing their ability to record local field potentials in an experimental model of spontaneous and epileptiform activity. Ourresults bring organic active neural probes to the forefront in applications where efficient sensory data processing is performed at sensor endpoints. This article is protected by copyright. All rights reserved.

The Influence of CaF2 Doping on the Sintering Behavior and Microwave Dielectric Properties of CaO-B2O3-SiO2 Glass-Ceramics for LTCC Applications

With the rapid development of microelectronic information technology, microelectronic packaging has higher requirements in terms of integration density, signal transmission speed, and passive component integration. Low temperature co-fired ceramics (LTCC) exhibit excellent dielectric properties and low temperature sintering properties, which meets the above-mentioned requirements. This work investigates the effects of CaF2 doping (0–16 mol%) on the glass structure, sintering behavior, crystallization, microstructure, and microwave dielectric properties of the CaO-B2O3-SiO2 (CBS) glass-ceramic system. Glass-ceramics were prepared using the conventional melting and quenching method. The physical and chemical properties of the glass-ceramics were analyzed using various techniques including TMA, SDT, FTIR, XRD, SEM, and a network analyzer. The results indicate that CaF2 doping can effectively reduce the sintering temperature and softening temperature of CBS ceramics. It also substantially improves the densification, dielectric, and mechanical properties. The appropriate amount of CaF2-doped CBS glass-ceramics can be sintered below 800 °C with a low dielectric constant and loss at high frequency (εr < 6, tanδ < 0.02 @ 10~13 GHz). Specifically, 8 mol% CaF2 doped CBS glass-ceramics sintered at 790 °C exhibit excellent microwave dielectric and thermal properties, with εr ~ 5.92 @ 11.4 GHz, tanδ ~ 1.59 × 10−3, CTE ~ 7.76 × 10−6/°C, λ ~ 2.17 W/(m·k), which are attractive for LTCC applications.

A short high-gain waveguide amplifier based on low concentration erbium-doped thin-film lithium niobate on insulator

One hotspot of integrated optics is how to realize a highly integrated and high-gain on-chip amplification system in a thin film of lithium niobate on insulator (TFLNOI). Here, a low erbium-doped TFLNOI waveguide amplifier with shorter length is demonstrated using the photolithography-assisted oblique-reactive ion etching technique. A maximum net internal gain of 5.4 dB in the small-signal-gain regime is measured at the peak emission wavelength of 1531.35 nm for a waveguide length of 1.5 mm and an erbium-doped concentration of 0.1 mol. %, indicating a gain per unit length of 36 dB cm−1. This work paves the way for the monolithic integration of diverse active and passive photonic components on the TFLNOI platform.

Ferroelectric-gated variable-area capacitors with large capacitance tuning ratio using Ce-doped HfO2 film for both gate insulator and capacitor layer

We demonstrate a three-terminal variable-area capacitor integrated with a ferroelectric-gate field-effect transistor (FeFET) and a ferroelectric capacitor. A FeFET using an indium tin oxide (ITO) channel and a ferroelectric Hf0.86Ce0.14O2 gate insulator was fabricated by chemical solution deposition. The fabricated FeFET exhibited a high on-current of ∼0.18 mA μm−1 and a large on-/off-current ratio of 106. The large charge controllability of the FeFET allows the conductive ITO channel to act as an electrode switch that connects and disconnects two capacitors. In order to increase the capacitance density and the capacitance tuning ratio (CTR), we propose a structure wherein a 25-nm-thick ferroelectric film is applied as both a gate insulator and a capacitor. The proposed structure exhibited a large capacitance density of 12.5 nF mm−2 and a wide CTR of approximately 10 000. This work facilitates future integration of passive and active components for advanced highly efficient and miniaturized electronics.

Variable-area capacitors controlled by HfO2-based ferroelectric-gate field-effect transistors

We propose a three-terminal variable-area capacitor integrated with a ferroelectric-gate field-effect transistor (FeFET) and a paraelectric thin-film capacitor. Owing to the large charge controllability and nonvolatile memory function of the ferroelectric Hf0.86Ce0.14O2 (14% Ce-HfO2) gate insulator, the variable-area capacitors exhibited high capacitance tuning ratios of up to 184 with steep modulation to gate voltage swing (440 mV/decade), a capacitance-switching speed of less than 10 ms, and capacitance-memory-retention characteristics of up to 105 s. An FeFET with an indium tin oxide (ITO) channel and a ferroelectric 14% Ce-HfO2 gate insulator was fabricated as a switching FET via chemical solution deposition, followed by stacking a sputtered Al2O3 film as a variable capacitor. The fabricated FeFETs exhibited a high on-current of ∼0.15 A/mm, a large on/off current ratio of 107, a field-effect mobility of 15.6 cm2/V s, and a memory window of ∼5 V. The high on-current, i.e., low on-resistance (84 Ω), and the large on/off current ratio allow the ITO channel to act as a wiring that connects and disconnects two capacitors with different electrode areas; therefore, the proposed variable capacitor can achieve wide and steep modulation by ferroelectric gating. This study provides prospects for the future integration of passive and active components for advanced high-efficiency and miniaturized electronics such as power devices and communication equipment.

A New Integrated Active EMI Filter Topology With Both CM Noise and DM Noise Attenuation

Integration of electromagnetic interference (EMI) filters is a good idea to further decrease the volume and weight of a power converter. However, the conventional research articles mainly focus on the integration of passive components or planar printed circuit board structures. This article proposes a new integrated active EMI filter (AEF) topology. It can attenuate both common-mode (CM) and differential-mode (DM) noise at the same time. Different from the traditional discrete CM AEFs and DM AEFs, noise sensing and cancelation of this proposed topology are performed simultaneously. The working principle and special features of this topology are analyzed in detail. Based upon the theoretical analysis, the insertion loss of this integration topology is close to the traditional separated CM AEFs or DM AEFs. Besides fewer components and dc power supply are demanded. A prototype is built and tested through experiments. Experimental results derived on standard test board and practical converter show good agreement to theoretical analysis.

Review on the Traditional and Integrated Passives: State-of-the-Art Design and Technologies

With the increased necessity of a high power density and efficient system in aerospace and marine industries, integrated motor drives provide an excellent solution in the modern era. Therefore, a close structural and functional integration of passive components has become a prerequisite task to make a compact overall system. This article reviews the existing motor drives system with integrated passive technologies. To start, the design aspect of the traditional and integrated filter inductors, using the area product approach, is discussed. Subsequently, layouts of traditional and integrated inductors are presented. The available capacitor technologies, suitable for integration, are also discussed with pros and cons of each capacitor type.

On‐Chip Integrated Waveguide Amplifiers on Erbium‐Doped Thin‐Film Lithium Niobate on Insulator

AbstractOn‐chip light amplification with integrated optical waveguide fabricated on erbium‐doped thin‐film lithium niobate on insulator (TFLNOI) is demonstrated using the photolithography‐assisted chemomechanical etching (PLACE) technique. A maximum internal net gain of 18 dB in the small‐signal‐gain regime is measured at the peak emission wavelength of 1530 nm for a waveguide length of 3.6 cm, indicating a differential gain per unit length of 5 dB cm−1. This work paves the way to the monolithic integration of diverse active and passive photonic components on the TFLNOI platform.

(Invited) Heterogeneous Integration As Enabler for Future Applications and Products

Future electronic systems like autonomous systems using high performance computing (HPC) and edge computing systems, sensor integrated systems and bio-integrated devices will required more and more functions which cannot be managed by a single chip, even if advanced SoC (System on Chip) concepts are used. Heterogeneous integration will be the next step and will pass beyond current SiP (System in Package) approaches. This concept of true heterogeneous integration is highly important for next-gen devices based on future CMOS-nodes, SiGe, SiC, III/Vs like GaAs or GaN and all different kinds of MEMS.Besides die and package stacking, embedding dies is a key technology for heterogeneous system integration. There are two main approaches for embedded die technologies: Fan-out Wafer and Panel Level integration, where dies are embedded into polymer encapsulants and Chip in Polymer, where dies are embedded into the substrate.Besides multiple die packaging also the integration of passive components as capacitors or resistors as well as the integration of shielding layers, antennas and e.g. resonators in and on package is a key for future applications. Co-design of chip and package for miniaturized heterogeneous packages will also give benefits especially for high frequency applications as 5G and beyond. The extension of advanced process design kits (PDK) towards packaging technologies including larger process tolerances and a much larger number of materials and processes would also support the approach of chip and package co-design.Another trend is moving from planar embedding technology to 3D shaped integration. Conformal electronics offer a functional shape adapted system with embedded electronics for e.g. sensors with aligned sensing direction, 3D shaped high frequency antennas or geometrically adapted electronics to the environment.

Vertical Integration of Passive Microwave Components Using Functional Via Structures in LTCC Multilayer Substrates

A recently developed concept for designing passive microwave components using functional vertical interconnect accesses (vias) for vertical integration in printed circuit boards (PCBs) is extended and transferred to the low temperature cofired ceramic (LTCC) technology. Given the changed material properties and new technology constraints, it is shown how and to what extent the controlled vertical interconnect accesses (via) structures can behave as quasi-transmission lines, thus allowing for another degree of freedom in component design. To demonstrate the validity and utility of functional vias, several novel microwave components are proposed and subsequently analyzed including vertically integrated 2- and 3-way Wilkinson power dividers, as well as vertically integrated 90° and 180° hybrid couplers. Prototypes for the 2-way and 3-way power dividers were manufactured on an LTCC multilayer substrate. Both measurement and full-wave simulation results are in excellent agreement and thus provide a proof of the concept.

Improvement of critical temperature of niobium nitride deposited on 8-inch silicon wafers thanks to an AlN buffer layer

In this paper, we study the crystalline properties and superconducting critical temperature of ultra-thin (5–9 nm) NbN films deposited on 8-inch silicon wafers by reactive sputtering. We show that the deposition of NbN on a thin (10–20 nm) AlN buffer layer, also synthesized by reactive sputtering, improves the critical temperature by several Kelvin, up to 10 K for 9 nm NbN on 20 nm AlN. We correlate this improvement to the higher-crystalline quality of NbN on AlN. While NbN deposited directly on silicon is polycrystalline with randomly oriented grains, NbN on AlN(0001) is textured along (111), due to the close lattice match. The superconducting properties of the NbN/AlN stack are validated by the demonstration of fibre-coupled normal-incidence superconducting nanowire single photon detectors. The whole fabrication process is CMOS compatible, with a thermal budget compatible with the integration of other passive and active components on silicon. These results pave the way for the integration of a large number of surface or waveguide-integrated detectors on large-scale silicon wafers. Furthermore, as AlN is transparent over a broad wavelength range from the visible to the near-infrared, the optimized superconducting NbN/AlN stack can be used for a wide variety of applications, from imaging to quantum communications and quantum computing.

A Monolithic Resonant Switched-Capacitor Voltage Regulator With Dual-Phase Merged-LC Resonator

Fully integrated voltage regulation, while important for a number of applications, is challenging due to the limitations of on-chip passive components, particularly inductors. This work demonstrates a new direction in passive-component integration through the design and implementation of a silicon-integrated merged-LC resonator, used in a resonant switched-capacitor voltage regulator. The merged-LC resonator combines flying capacitance and inductance into a single structure to reduce ac resistive losses, achieving higher efficiency and power density. The voltage regulator is implemented in a 0.18-μm CMOS process and achieves 85.5% efficiency at 0.47 W without off-chip passive components. Light-load efficiency is extended through the use of OFF-time modulation (OTM); the design achieves <; 40-mV under-/over-shoot during 2-50-mA/4-μs load transients.

Monolithic Heterogeneous Integration of 3D Radio Frequency L−C Elements by Self‐Rolled‐Up Membrane Nanotechnology

AbstractThis work reports a three‐dimensional (3D) radio frequency L−C filter network enabled by a CMOS‐compatible two‐dimensional (2D) fabrication approach, which combines inductive (L) and capacitive (C) self‐rolled‐up membrane (S‐RuM) components monolithically into a single L−C network structure, thereby greatly reducing the on‐chip area footprint. The individual L−C elements are fabricated in‐plane using standard semiconductor processing techniques, and subsequently triggered by the built‐in stress to self‐assemble and roll into cylindrical air‐core architectures. By designing the planar structure geometry and constituent layer properties to achieve a specific number of turns with a desired inner diameter when the device is rolled up, the electrical characteristics can be engineered. The network layouts of the L and C components are also reconfigurable by selecting appropriate input, output, and ground contact routing topographies. The devices demonstrated here operate over the range of ≈1−10 GHz. Their area and volume footprints are ≈0.09 mm2 and ≈0.01 mm3, respectively, which are ≈10× smaller than most of the comparable conventional filter designs. These S‐RuM‐enabled 3D microtubular L−C filter networks represent significant advancement for miniaturization and integration of passive electronic components for applications in mobile connectivity and other frequency range.

Effective-medium-cladded dielectric waveguides for terahertz waves.

Terahertz integrated platforms with high efficiency are crucial in a broad range of applications including terahertz communications, radar, imaging and sensing. One key enabling technology is wideband interconnection. This work proposes substrate-less all-dielectric waveguides defined by an effective medium with a subwavelength hole array. These self-supporting structures are built solely into a single silicon wafer to minimize significant absorption in metals and dielectrics at terahertz frequencies. In a stark contrast to photonic crystal waveguides, the guiding mechanism is not based on a photonic bandgap but total internal reflections The waveguides are discussed in the context of terahertz communications that imposes stringent demands on performance. Experimental results show that the realized waveguides can cover the entire 260-400 GHz with single dominant modes in both orthogonal polarizations and an average measured attenuation around 0.05 dB/cm. Limited by the measurement setup, the maximum error-free data rate up to 30 Gbit/s is experimentally achieved at 335 GHz on a 3-cm waveguide. We further demonstrate the transmission of uncompressed 4K-resolution video across this waveguide. This waveguide platform promises integration of diverse active and passive components. Thus, we can foresee it as a potential candidate for the future terahertz integrated circuits, in analogy to photonic integrated circuits at optical frequencies. The proposed concept can potentially benefit integrated optics at large.

Fan-Out Wafer and Panel Level Packaging as Packaging Platform for Heterogeneous Integration.

Fan-out wafer level packaging (FOWLP) is one of the latest packaging trends in microelectronics. Besides technology developments towards heterogeneous integration, including multiple die packaging, passive component integration in packages and redistribution layers or package-on-package approaches, larger substrate formats are also targeted. Manufacturing is currently done on a wafer level of up to 12”/300 mm and 330 mm respectively. For a higher productivity and, consequently, lower costs, larger form factors are introduced. Instead of following the wafer level roadmaps to 450 mm, panel level packaging (PLP) might be the next big step. Both technology approaches offer a lot of opportunities as high miniaturization and are well suited for heterogeneous integration. Hence, FOWLP and PLP are well suited for the packaging of a highly miniaturized energy harvester system consisting of a piezo-based harvester, a power management unit and a supercapacitor for energy storage. In this study, the FOWLP and PLP approaches have been chosen for an application-specific integrated circuit (ASIC) package development with integrated SMD (surface mount device) capacitors. The process developments and the successful overall proof of concept for the packaging approach have been done on a 200 mm wafer size. In a second step, the technology was scaled up to a 457 × 305 mm2 panel size using the same materials, equipment and process flow, demonstrating the low cost and large area capabilities of the approach.

Embedded SIP Modules for next-GEN Heterogeneous “POWER-Devices”

In this paper will focus on the comprehension of System-in-Package (SiP) with embedded active and passive components integration will be described. Embedding of semiconductor chips into substrates provides many advantages that have been noted. It allows the smallest package form-factor with high degree of miniaturization through sequentially stacking of multiple layers containing embedded devices that are optimized for electrical performance with short and geometrically well controlled copper interconnects. In addition, the embedding gives a homogeneous mechanical environment of the chips, resulting in good reliability at system level. Furthermore, embedded technology is an excellent resolution to Power management challenges dealing with new device technologies (Si, GaS, GaN) and optimization on the thermal dissipation with improved efficiency. Embedded technology comes with many challenges in 2019, primarily design for manufacturability (DFM) and maturity. Customers are looking for better-performance capability and pricing normally that means same or lower than die free package cost (DFPC) comparison. This paper will discuss the challenges bring to market the Embedded SIP Modules for next-GEN Heterogeneous “POWER-Devices” Today, the embedded process is being developed by printed circuit board (PCB) manufacturers creating a new supply chain, bringing new players into the semiconductor industry. This new supply chain comes along with new business models. As a result of the increasing interest in implementing embedding technologies, ACCESS Semiconductors in China is committed to be a leader in the adaptation of embedding technologies, with over 10-yrs mature coreless technology and proved design rules for low profile dimensions with seamless Ti/Cu sputtering and Cu pillar interconnect giving advantages in both electrical &amp; power performance. ACCESS Patented “Via-in-Frame” technology provides High Reliability (MSL1, PCT, BHAST) at Cost Effective in high panel utilization for HVM, using standard substrate/PCB known material sets, no need for wafer bumping/RDL, over-mold or under-fill cost adders. ACCESS Semiconductors is currently in HVM on single die 2L, and LVM on multi-devices actives/passives 4L SiP construction both platforms are driven from the power market segment. In-development on Die Last &amp; Frameless (MeSiP) platforms utilizing hybrid technology (mSAP) and Photo Imageable Dielectric (PID) materials for cost down solutions in HVM by Q1FY2020. Also, ACCESS Semiconductors total turn-key solutions will include front-of-line (FOL) and end-of-line (EOL) capability from wafer handling, back-grinding, and dicing with KGD traceability thru the embedded chip process, frame/strip singulation, FT, marking pack &amp; ship providing additional 30% cost reduction in the future. Here's an illustration of Embedded Technology Roadmap and Product Platforms.

Integrated Very-High-Frequency Switch Mode Power Supplies: Design Considerations

This paper presents a power supply using an increased switching frequency to minimize the size of energy storing components, thereby addressing the demands for increased power densities in power supplies, and 100-MHz and higher switching frequencies have been used in resonant power converters, which along with the possible integration of passive components on silicon wafer present a beneficial solution in applications such as mobile phones. This paper presents a design for a 9-W class E resonant power converter in a 0.18- $\mu \text{m}$ CMOS process. The converter is driven by a self-oscillating gate drive, which is presented in an in-depth mathematical analysis. The gate resistance of the designed transistors is of critical importance in order to achieve the correct phase shift required for zero voltage switching. The Z-parameter method is used to characterize the transistors, which is verified through simulations. The required spiral inductors were modeled, and simulations show $Q$ values of as high as 14 at a switching frequency of 250 MHz. Simulations of the converter show an efficiency of 55% with a self-oscillating gate drive. However, the modeled inductor was not adequate for operating with the self-oscillating gate drive, presenting a future challenge for power supplies on chip.

Theoretical and Experimental Investigation of Thermo-Tunable Metal–Insulator–Vanadium Dioxide Coplanar Waveguide Structure

This paper presents a thermo-tunable metal–insulator–vanadium dioxide (MIV) coplanar waveguide structure (CPW). An analytical quasi-TEM model is used to thoroughly study the structural and material-dependent characteristic parameters of the device, while the temperature-dependent broadband permittivity and conductivity of the deposited vanadium dioxide (VO2) thin film at microwave frequencies are experimentally extracted. The designed thermo-tunable MIV-CPW, focused on its slow-wave properties, shows a drastic increase in slow-wave factor when the temperature of the VO2 thin film is increased over its transition temperature. This phase change allows converting this composite structure into the metal–insulator–semiconductor coplanar slow-wave structure. This demonstrates the potential of such MIV-CPW for the design of tunable and reconfigurable integrated microwave passive components with a significantly reduced size.

Reduced Hybrid Ring Coupler Using Surface Micromachining Technology for 94-GHz MMIC Applications

In this study, we developed a reduced 94 GHz hybrid ring coupler on a GaAs substrate in order to demonstrate the possibility of the integration of various passive components and MMICs in the millimeter-wave range. To reduce the size of the hybrid ring coupler, we used multiple open stubs on the inside of the ring structure. The chip size of the reduced hybrid ring coupler with multiple open stubs was decreased by 62% compared with the area of the hybrid ring coupler without open stubs. Performance in terms of the loss, isolation, and phase difference characteristics exhibited no significant change after the use of the multiple open stubs on the inside of the ring structure. The reduced hybrid ring coupler showed excellent coupling loss of 3.87±0.33 dB and transmission loss of 3.77±0.72 dB in the measured frequency range of 90–100 GHz. The isolation and reflection were −48 dB and −32 dB at 94 GHz, respectively. The phase differences between two output ports were 180°±1° at 94 GHz.