Parity Computation Research Articles

MS scheduler: New, scalable, and high-performance sparse AVX-2 parity encoding and decoding technique for erasure-coded cloud storage systems

In cloud storage scenarios, each chunk with multiple symbols of a coding strip resides in a different node and, hence, on a different disk. Existing STAIR and sector-disk (SD) scheduling techniques are not scalable because the performance of existing STAIR and SD encoding and decoding schedulers decreases sharply as the number of parity disks increases. This paper proposes a new, scalable, multisector (MS) scheduler that provides three-level fault tolerance for multiple sectors, disks, and nodes. In addition, the MS scheduler is extendable to multilevel failure recovery. MS schedulers are aware of the inner structure of each node, such as the number of disks and sectors for each node. Compared with SD and STAIR schedulers, an MS scheduler improves the average encoding and decoding performance by 198.34%, on average (ranging from 170.46% to 228.54%). However, STAIR and SD schedulers are bound to a specific number of parity disks and sectors. This is because the MS scheduler uses streaming SIMD extensions (SSE) for the dense matrix-based parity computation software implementation. In contrast, an MS scheduler can perform parity calculations for a large number of parity disks and sectors using advanced vector extensions (AVX)-2, OpenMP thread parallelism, and sparse parity computation software implementation. As a result, fewer XOR operations are performed to calculate parity chunks owing to the diagonal structure of the MS scheduler. The sparse AVX-2/-512 diagonal erasure coding implementation of the MS scheduler enables the proposed scheduler to be compatible with recovery from multilevel failures by skipping a large number of XOR and multiplication operations. This proves that the MS scheduler is suitable for use in a scalable cloud storage environment.

Techniques to Reduce π/4-Parity-Phase Circuits, Motivated by the ZX Calculus

To approximate arbitrary unitary transformations on one or more qubits, one must perform transformations which are outside of the Clifford group. The gate most commonly considered for this purpose is the T = diag(1, exp(i \pi/4)) gate. As T gates are computationally expensive to perform fault-tolerantly in the most promising error-correction technologies, minimising the "T-count" (the number of T gates) required to realise a given unitary in a Clifford+T circuit is of great interest. We describe techniques to find circuits with reduced T-count in unitary circuits, which develop on the ideas of Heyfron and Campbell [arXiv:1712.01557] with the help of the ZX calculus. Following [arXiv:1712.01557], we reduce the problem to that of minimising the T count of a CNOT+T circuit. The ZX calculus motivates a further reduction to simplifying a product of commuting "\pi/4-parity-phase" operations: diagonal unitary transformations which induce a relative phase of exp(i \pi/4) depending on the outcome of a parity computation on the standard basis (which motivated Kissinger and van de Wetering [1903.10477] to introduce "phase gadgets"). For a number of standard benchmark circuits, we show that these techniques -- in some cases supplemented by the TODD subroutine of Heyfron and Campbell [arXiv:1712.01557] -- yield T-counts comparable to or better than the best previously known results.

Elastic Parity Logging for SSD RAID Arrays: Design, Analysis, and Implementation

Parity-based RAID poses a design trade-off issue for large-scale SSD storage systems: it improves reliability against SSD failures through redundancy, yet its parity updates incur extra I/Os and garbage collection operations, thereby degrading the endurance and performance of SSDs. We propose EPLog , a storage layer that reduces parity traffic to SSDs, so as to provide endurance, reliability, and performance guarantees for SSD RAID arrays. EPLog mitigates parity update overhead via elastic parity logging , which redirects parity traffic to separate log devices (to improve endurance and reliability) and eliminates the need of pre-reading data in parity computations (to improve performance). We design EPLog as a user-level implementation that is fully compatible with commodity hardware and general erasure coding schemes. We evaluate EPLog through reliability analysis and trace-driven testbed experiments. Compared to the Linux software RAID implementation, our experimental results show that our EPLog prototype reduces the total write traffic to SSDs, reduces the number of garbage collection operations, and increases the I/O throughput. In addition, EPLog significantly improves the I/O performance over the original parity logging design, and incurs low metadata overhead.

Designing Checksums for Detecting Errors in Fast Unitary Transforms

Parity computations, checksums, over the input and output data of fast unitary transforms are compared, down to roundoff noise levels, to detect the effects from a single error on any one line between stages of the fast algorithm. Error spaces and their dual spaces guide the design process.

A Scheme to Improve the Intrinsic Error Detection of the Instruction Set Architecture

The Instruction Set Architecture (ISA) determines the effect that a soft error on an instruction can have on the processor. Previous works have shown that the ISA has some intrinsic capability of detecting errors. For example, errors that change a valid instruction into an invalid instruction encoding or into an instruction that causes an exception. The percentage of detectable errors varies widely for each bit in the ISA. For example, errors on bits that are used for immediate or register values are unlikely to be detected while those that are used for the opcode are more likely to lead to an exception. In this paper, this is exploited by introducing a simple encoding of the instructions that does not require additional bits. The idea is that the decoding propagates the error so that it affects the most sensitive bit of the ISA and therefore it is more likely to be detected. As no additional bits are required, no changes or overheads are needed in the memory. The proposed scheme is useful when the memory is not protected with parity or Error Correction Codes. The only cost of implementing the technique are simple encoder and decoder circuits that are similar to a parity computation. This technique is applicable to any ISA, no matter the length of the opcodes or their location in the instruction encoding. The effectiveness of the proposed scheme has been evaluated on the ARM Cortex M0 ISA resulting in an increase in the error detection capability of up to 1.64x.

Application-Guided Power-Efficient Fault Tolerance for H.264 Context Adaptive Variable Length Coding

This paper presents a fault-tolerance technique for H.264's Context-Adaptive Variable Length Coding (CAVLC) on unreliable computing hardware. The application-specific knowledge is leveraged at both algorithm and architecture levels to protect the CAVLC process (especially context adaptation and coding tables) in a reliable yet power-efficient manner. Specifically, the statistical analysis of coding syntax and video content properties are exploited for: (1) selective redundancy of coefficient/header data of video bitstreams; (2) partitioning the coding tables into various sub-tables to reduce the power overhead of fault tolerance; and (3) run-time power management of memory parts storing the sub-tables and their parity computations. Experimental results demonstrate that leveraging application-specific knowledge reduces area and performance overhead by 2x compared to a double-parity table protection technique. For functional verification and area comparison, the complete H.264 CAVLC architecture is prototyped on a Xilinx Virtex-5 FPGA (though not limited to it).

High performance GPU‐based parity computing scheduler in storage applications

SummaryThis paper proposes a high‐performance graphics processing unit (GPU)‐based parity computing scheduler, which we call GPU‐redundant array of inexpensive disks (RAID), to reduce the encoding and decoding time for storage applications. The proposed GPU‐RAID differs from existing RAID in that it performs additional pairwise‐parallel XOR operations between data code words in each data stripe by applying divide‐and‐conquer approach using extra reserved space and it also increases parallelism by processing multiple strips in parallel using multiple GPU threads. And so the proposed GPU‐RAID pipelines data blocks into solid‐state disks and parity blocks into hard disk drives at the target server. The proposed algorithm decreases the span complexity of the parity computation schedule to O(log2nw) where n is the number of disks and w is the number of code words in a block, and it can be applied to various types of erasure codes. Experimental results show that the proposed storage application (SA1) improves average encoding performance by 63%, and 41%, and average decoding performance by 58%, and 38%, compared with traditional storage applications GPUStore (SA3) and Gibraltar RAID(SA2), respectively. Copyright © 2016 John Wiley & Sons, Ltd.

Synchronous I/O Scheduling of Independent Write Caches for an Array of SSDs

Solid-state drives (SSD) offer a significant performance improvement over the hard disk drives (HDD), however, it can exhibit a significant variance in latency and throughput due to internal garbage collection (GC) process on the SSD. When the SSDs are configured in a RAID, the performance variance of individual SSDs could significantly degrade the overall performance of the RAID of SSDs. The internal cache on the RAID controller can help mitigate the performance variability issues of SSDs in the array; however, the state-of-the-art cache algorithm of the RAID controller does not consider the characteristics of SSDs. In this paper, we examine the most recent write cache algorithm for the array of disks, and propose a synchronous independent write cache (SIW) algorithm. We also present a pre-parity-computation technique for the RAID of SSDs with parity computations, which calculates parities of blocks in advance before they are stored in the write cache. With this new technique, we propose a complete paradigm shift in the design of write cache. In our evaluation study, large write requests dominant workloads show up to about 50 and 20 percent improvements in average response times on RAID-0 and RAID-5 respectively as compared to the state-of-the-art write cache algorithm.

RAID triple parity

RAID triple parity (RTP) is a new algorithm for protecting against three-disk failures. It is an extension of the double failure correction Row-Diagonal Parity code. For any number of data disks, RTP uses only three parity disks. This is optimal with respect to the amount of redundant information required and accessed. RTP uses XOR operations and stores all data un-encoded. The algorithm's parity computation complexity is provably optimal. The decoding complexity is also much lower than that of existing comparable codes. This paper also describes a symmetric variant of the algorithm where parity computation is identical to triple reconstruction.

Evaluation of software based redundancy algorithms for the EOS storage system at CERN

EOS is a new disk based storage system used in production at CERN since autumn 2011. It is implemented using the plug-in architecture of the XRootD software framework and allows remote file access via XRootD protocol or POSIX-like file access via FUSE mounting. EOS was designed to fulfill specific requirements of disk storage scalability and IO scheduling performance for LHC analysis use cases. This is achieved by following a strategy of decoupling disk and tape storage as individual storage systems. A key point of the EOS design is to provide high availability and redundancy of files via a software implementation which uses disk-only storage systems without hardware RAID arrays. All this is aimed at reducing the overall cost of the system and also simplifying the operational procedures.This paper presents the advantages and disadvantages of redundancy by hardware (most classical storage installations) in comparison to redundancy by software. The latter is implemented in the EOS system and achieves its goal by spawning data and parity stripes via remote file access over nodes. The gain in redundancy and reliability comes with a trade-off in the following areas:• Increased complexity of the network connectivity• CPU intensive parity computations during file creation and recovery• Performance loss through remote disk couplingAn evaluation and performance figures of several redundancy algorithms are presented for dual parity RAID and Reed-Solomon codecs. Moreover, the characteristics and applicability of these algorithms are discussed in the context of reliable data storage systems.

Multi-Fault Tolerance for Cartesian Data Distributions

Faults are expected to play an increasingly important role in how algorithms and applications are designed to run on future extreme-scale systems. Algorithm-based fault tolerance is a promising approach that involves modifications to the algorithm to recover from faults with lower overheads than replicated storage and a significant reduction in lost work compared to checkpoint-restart techniques. Fault-tolerant linear algebra algorithms employ additional processors that store parities along the dimensions of a matrix to tolerate multiple, simultaneous faults. Existing approaches assume regular data distributions (blocked or block-cyclic) with the failures of each data block being independent. To match the characteristics of failures on parallel computers, we extend these approaches to mapping parity blocks in several important ways. First, we handle parity computation for generalized Cartesian data distributions with each processor holding arbitrary subsets of blocks in a Cartesian-distributed array. Second, techniques to handle correlated failures, i.e., multiple processors that can be expected to fail together, are presented. Third, we handle the colocation of parity blocks with the data blocks and do not require them to be on additional processors. Several alternative approaches, based on graph matching, are presented that attempt to balance the memory overhead on processors while guaranteeing the same fault tolerance properties as existing approaches that assume independent failures on regular blocked data distributions. Evaluation of these algorithms demonstrates that the additional desirable properties are provided by the proposed approach with minimal overhead.

Probability of even parity of soft bits

Gallager's lemma, presented originally in the context of decoding low-density parity check (LDPC) codes, computes the probability of even parity for independent, non-identically distributed bits. As the number of bits involved in the parity increases, there is a tendency of the probability of even parity towards 1/2. This tendency is discussed and analysed, resulting in a sort of counter central limit theorem result. In many instances, there are practical limits on the number of bits that can be included in a reliable soft parity computation. Implications affect LDPC decoding, soft descrambling and soft encoding of data.

Exploiting Parity Computation Latency for On-Chip Crosstalk Reduction

This brief provides an efficient method to address both logic errors and crosstalk-induced delay variations. In particular, the inherent skew resulting from parity generation is exploited to ensure that no two adjacent wires switch in opposite directions simultaneously, thereby reducing worst-case on-chip capacitive coupling. Data and parity-check bits are mapped to link driver registers, which are triggered by alternating clock phases. The proposed method reduces worst-case link delay by 25% for a 5 mm link, as compared to a conventional skewed transition approach. Compared with other solutions that simultaneously handle logic and delay errors, the proposed method reduces delay uncertainty by up to 24%, improves residual word error probability by 2.5×, requires fewer wires, and achieves up to 45% and 32% reductions in area and energy consumption, respectively.

Concurrent error detection in wavelet lifting transforms

Wavelet transforms, central to multiresolution signal analysis and important in the JPEG2000 image compression standard, are quite susceptible to computer-induced errors because of their pipelined structure and multirate processing requirements. Such errors emanate from computer hardware, software bugs, or radiation effects from the surrounding environment. Implementations use lifting schemes, which employ update and prediction estimation stages, and can spread a single numerical error caused by failures to many output transform coefficients without any features to warn data users. We propose an efficient method to detect the arithmetic errors using weighted sums of the wavelet coefficients at the output compared with an equivalent parity value derived from the input data. Two parity values may straddle a complete multistage transform or several values may be used, each pair covering a single stage. There is greater error-detecting capability at only a slight increase in complexity when parity pairs are interspersed between stages. With the parity weighting design scheme, a single error introduced at a lifting section can be detected. The parity computation operation is properly viewed as an inner product between weighting values and the data, motivating the use of dual space functionals related to the error gain matrices. The parity weighting values are generated by a combination of dual space functionals. An iterative procedure for evaluating the design of the parity weights has been incorporated in Matlab code and simulation results are presented.