Check Matrix Research Articles

Decoding LDPC Codes with a Regular Check Matrix Structure Using the Bit Flip Method

Problem statement: low-density LDPC codes have become very popular in modern communication systems, which make it possible to implement decoders for them in practice. In conditions of severe limitations of equipment performance, the task of searching and researching the characteristics of decoding algorithms for these codes is urgent. The aim of the work is to find a simplified algorithm for decoding LDPC codes and to study the noise immunity of the proposed algorithm. The methods used: to solve this problem computer simulation is used to compare the noise immunity of known decoding algorithms and the proposed algorithm. Scientific novelty: the noise immunity characteristics of the proposed Bit Flip algorithm for decoding LDPC code with a regular structure of the check matrix using gradient descent and the procedure for escaping the local minimum are investigated. Result: a specific variant of the Bit Flip algorithm for LDPC code with a regular structure check matrix using gradient descent and a procedure for escaping the local minimum is proposed. The results of computer simulation are presented. Theoretical significance: the characteristics of noise immunity for the proposed variant of the LDPC code decoding algorithm with a regular structure of the check matrix are investigated. Practical significance: when using the proposed LDPC code decoding algorithm in the receiver, it is possible to calculate the parameters of the communication system based on the available dependencies of the error coefficient on the signal-to-noise ratio.

Decoding error probability of random parity-check matrix ensemble over the erasure channel

AbstractIn this paper we carry out an in-depth study on the average decoding error probability of the random parity-check matrix ensemble over the erasure channel under three decoding principles, namely unambiguous decoding, maximum likelihood decoding and list decoding. We obtain explicit formulas for the average decoding error probabilities of the random parity-check matrix ensemble under these three decoding principles and compute the error exponents. Moreover, for unambiguous decoding, we compute the variance of the decoding error probability of the random parity-check matrix ensemble and the error exponent of the variance, which implies a strong concentration result, that is, roughly speaking, the ratio of the decoding error probability of a random linear code in the ensemble and the average decoding error probability of the ensemble converges to 1 with high probability when the code length goes to infinity.

Raptor Codes with LT-LDPC Precoding Performance Analysis and FPGA Optimization

Raptor codes are designed to effectively handle packet loss and erasures as a type of fountain code, capable of generating an unlimited number of encoded symbols from source informations, which is particularly useful in scenarios where the number of transmissions is unknown or variable. Luby Transform (LT) codes, a kind of fountain code encoding method, exhibit linear complexity, and Low-Density Parity-Check (LDPC) codes can be constructed by the generator matrix and the parity-check matrix. The LT-LDPC pre-coding method combines the advantages of both, enhancing encoding and decoding efficiency. Deploying code on Field-Programmable Gate Arrays (FPGAs) involves several steps: synthesis, place and route, and bitstream generation, followed by loading the bitstream onto the FPGA to configure its internal logic according to the coding methods. This paper introduces a method of encoding and decoding Raptor codes, utilizing the intimal LT codes and the peripheral LDPC codes constructed by PEG. It employs a lop-BP decoding method over noise channels based on the Tanner graph for decoding and deploys the optimized algorithm on FPGA to enhance performance.

Energy-Efficient Partial LDPC Decoding for NAND Flash-Based Storage Systems

A new decoding method for low-density parity-check (LDPC) codes is presented to lower the energy consumption of LDPC decoders for NAND flash-based storage systems. Since the channel condition of NAND flash memory is reliable for most of its lifetime, it is inefficient to apply the maximum-effort decoding with the full parity-check matrix (H-matrix) from the beginning of the lifespan. As the energy consumption and the decoding latency are proportional to the size of the H-matrix used in decoding, the proposed algorithm starts the decoding with a partial H-matrix selected by considering the channel condition. In addition, the proposed partial decoding provides various error-correcting capabilities by adjusting the partial H-matrix. Based on the proposed partial decoding algorithm, a prototype decoder is implemented in a 65 nm CMOS process to decode a 4 KB LDPC code. The proposed decoder reduces energy consumption by 93% compared to the conventional LDPC decoding architecture at maximum.

Novel intelligent blind information reconciliation for LDPC codes in quantum key distribution systems

Information reconciliation is an important step in quantum key distribution (QKD). As a good channel coding technology, LDPC (low-density parity-check) code perform well in information reconciliation. In this paper, we investigate a new approach, namely blind information reconciliation. In our approach, after the state distribution is carried out by Alice and the measurements are taken by Bob, Alice can select an appropriate LDPC encoder (parity-check matrix) from the predefined candidate pool according to the estimated QBER (quantum bit-error-rate). Bob can use the expectation–maximization (EM) estimator and the maximum average log-likelihood ratio (LLR) detector to blindly identify parity-check matrices associated with not only different code-rates but also different codeword-lengths Alice employed. Moreover, puncturing and shortening can also be invoked to adjust the code-rate slightly to improve the error-correction performance. Monte Carlo simulations have demonstrated that our proposed new blind information-reconciliation scheme can successfully identify the parity-check matrix even under high QBER conditions, reduce the interactive communication-rounds, and improve the reconciliation efficiency in comparison with the conventional rate-adaptive LDPC coding scheme without QBER estimation.

Modified Joint Source–Channel Trellises for Transmitting JPEG Images over Wireless Networks

This paper presents a joint source–channel image transmission model based on a modified trellis construction using variable-length and fixed-length codes. The model employs linear block trellis codes and a modified Bahl–Cocke–Jelinek–Raviv algorithm for decoding in the source channel. Additionally, this model utilizes a hierarchical tree and a parity-check matrix to combine the source and channel codes, reducing errors in the decoding process and enabling the decoding of longer sequences without substantial loss of quality.

GPPM: A Generalized Matrix Operation and Parallel Algorithm to Accelerate the Encoding/Decoding Process of Erasure Codes

Erasure codes are widely deployed in modern storage systems, leading to frequent usage of their encoding/decoding operations. The encoding/decoding process for erasure codes is generally carried out using the parity-check matrix approach. However, this approach is serial and computationally expensive, mainly due to dealing with matrix operations, which results in low encoding/decoding performance. These drawbacks are particularly evident for newer erasure codes, including SD and LRC codes. To address these limitations, this article introduces the Partitioned and Parallel Matrix ( PPM ) algorithm. This algorithm partitions the parity-check matrix, parallelizes encoding/decoding operations, and optimizes calculation sequence to facilitate fast encoding/decoding of these codes. Furthermore, we present a generalized PPM ( gPPM ) algorithm that surpasses PPM in performance by employing fine-grained dynamic matrix calculation sequence selection. Unlike PPM, gPPM is also applicable to erasure codes such as RS code. Experimental results demonstrate that PPM improves the encoding/decoding speed of SD and LRC codes by up to 210.81%. Besides, gPPM achieves up to 102.41% improvement over PPM and 32.25% improvement over RS regarding encoding/decoding speed.

LDPC-coded cylindrical vector beam multiplexing for improved communication performance

Cylindrical vector beams (CVBs) have attracted significant research interest in mode-division multiplexing communication thanks to their capacity to carry orthogonal vector modes. Because CVB modes are the eigen-solutions of few-mode fiber (FMF), they are well-suited for long-distance transmission. Nevertheless, the application of CVB multiplexing communication is impeded by mode coupling in FMF, which leads to mode crosstalk and signal fading. Herein we propose an LDPC coded strategy to provide a channel equalization solution, which enhances the performance of CVB multiplexing communication. Digital signals are encoded using a sparse parity-check matrix that establishes a specific parity-check relationship between the original data bits and the check bits. This enables the correction of error bits for channel equalization. To demonstrate the concept, we built a 4-channel CVB multiplexing communication system that transmitted 24 × 4 Gbit/s QPSK-OFDM signals over 5 km FMF. After equalization, the bit error rate decreased by ∼ 2.5 orders of magnitude, and the communication sensitivity improved by ∼ 8 dB. This proof of concept demonstrates the potential of the proposed LDPC coded strategy to enhance the performance of CVB multiplexing communication systems.

Design and Implementation of a Highly Efficient Quasi-Cyclic Low-Density Parity-Check Transceiving System Using an Overlapping Decoder.

The traditional LDPC encoding and decoding system is characterized by low throughput and high resource consumption, making it unsuitable for use in cost-efficient, energy-saving sensor networks. Aiming to optimize coding complexity and throughput, this paper proposes a combined design of a novel LDPC code structure and the corresponding overlapping decoding strategies. With regard to structure of LDPC code, a CCSDS-like quasi-cyclic parity check matrix (PCM) with uniform distribution of submatrices is constructed to maximize overlap depth and adapt the parallel decoding. In terms of reception decoding strategies, we use a modified 2-bit Min-Sum algorithm (MSA) that achieves a coding gain of 5 dB at a bit error rate of 10-6 compared to an uncoded BPSK, further mitigating resource consumption, and which only incurs a slight loss compared to the standard MSA. Moreover, a shift-register-based memory scheduling strategy is presented to fully utilize the quasi-cyclic characteristic and shorten the read/write latency. With proper overlap scheduling, the time consumption can be reduced by one third per iteration compared to the non-overlap algorithm. Simulation and implementation results demonstrate that our decoder can achieve a throughput up to 7.76 Gbps at a frequency of 156.25 MHz operating eight iterations, with a two-thirds resource consumption saving.

Sparsity-Aware Medium-Density Parity-Check Decoder for McEliece Cryptosystems

McEliece cryptosystem based on medium-density parity-check (MDPC) codes is one of the finalists for the post-quantum cryptography standard. Although decoder design for low-density parity-check (LDPC) codes used for digital communications is well-investigated, the design of MDPC decoders faces many new challenges due to the different structure in the parity-check matrix. Even though the parity-check matrices of MDPC codes have relatively higher density, they are still very sparse. Previous decoder designs did not explore such sparsity and derive the columns of the parity check matrix one after the other by cyclic shifting. This paper proposes a low-complexity MDPC decoder design by exploiting the sparsity of the parity-check matrix. The processing corresponding to zero segments of each parity check matrix column is skipped to substantially reduce the latency. Moreover, the columns are processed in a novel non-consecutive order to significantly reduce the number of memory writes for deriving all the columns and accordingly the power consumption. For an example MDPC code considered for the standard, the proposed design can reduce both the decoding latency and the number of memory writes by 70% with 35% area saving.

Design of Low-Density Parity-Check Code Pair for Joint Source-Channel Coding Systems Based on Graph Theory.

In this article, a graph-theoretic method (taking advantage of constraints among sets associated with the corresponding parity-check matrices) is applied for the construction of a double low-density parity-check (D-LDPC) code (also known as LDPC code pair) in a joint source-channel coding (JSCC) system. Specifically, we pre-set the girth of the parity-check matrix for the LDPC code pair when jointly designing the two LDPC codes, which are constructed by following the set constraints. The constructed parity-check matrices for channel codes comprise an identity submatrix and an additional submatrix, whose column weights can be pre-set to be any positive integer numbers. Simulation results illustrate that the constructed D-LDPC codes exhibit significant performance improvement and enhanced flexible frame length (i.e., adaptability under various channel conditions) compared with the benchmark code pair.

Rate-Diverse Multiple Access Over Gaussian Channels

In this work, we develop a pair of rate-diverse encoder and decoder for a two-user Gaussian multiple access channel (GMAC). The proposed scheme enables the users to transmit with the same codeword length but different coding rates under diverse user channel conditions. First, we propose the row-combining (RC) method and row-extending (RE) method to design practical low-density parity-check (LDPC) channel codes for rate-diverse GMAC. Second, we develop an iterative rate-diverse joint user messages decoding (RDJD) algorithm for GMAC, where all user messages are decoded with a single parity-check matrix. In contrast to the conventional network-coded multiple access (NCMA) and compute-forward multiple access (CFMA) schemes that first recover a linear combination of the transmitted codewords and then decode both user messages, this work can decode both the user messages simultaneously. Extrinsic information transfer (EXIT) chart analysis and simulation results indicate that RDJD can achieve gains up to 1.0 dB over NCMA and CFMA in the two-user GMAC. In particular, we show that there exists an optimal rate allocation for the two users to achieve the best decoding performance given the channel conditions and sum rate.

The weight distribution of codes over finite chain rings

In this work, we determine new linear equations for the weight distribution of linear codes over finite chain rings. The identities are determined by counting the number of some special submatrices of the parity-check matrix of the code. Thanks to these relations we are able to compute the full weight distribution of codes with small Singleton defects, such as MDS, MDR and AMDR codes.

Parity-Check Matrix Partitioning for Efficient Layered Decoding of QC-LDPC Codes

In this paper, we consider how to partition the parity-check matrices (PCMs) to reduce the hardware complexity and increase decoding throughput for the row layered decoding of quasi-cyclic low-density parity-check (QC-LDPC) codes. First, we formulate the PCM partitioning as an optimization problem, which targets to minimize the maximum column weight of each layer while maintaining a block cyclic shift property among different layers. As a result, we derive all the feasible solutions for the problem and propose a tight lower bound ω <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>LB</i></sub> on the minimum possible maximum column weight to evaluate a solution. Second, we define a metric called layer distance to measure the data dependency between consecutive layers and further illustrate how to identify the solutions with desired layer distance from those achieving the minimum value of ω <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>LB</i></sub> = 1, which is preferred to reduce computation delay. Next, we demonstrate that up-to-now, finding an optimal solution for the optimization problem with polynomial time complexity is unachievable. Therefore, both enumerative and greedy partition algorithms are proposed instead. After that, we modify the quasi-cyclic progressive edge-growth (QC-PEG) algorithm to directly construct PCMs that have a straightforward partition scheme to achieve ω <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>LB</i></sub> or the desired layer distance. Simulation results showed that the constructed codes have better error correction performance and achieve less average number of iterations than the underlying 5G LDPC codes.

ELDPC: An Efficient LDPC Coding Scheme for Phase-Change Memory

Low read latency, long lifetime, and high storage density have all been demonstrated in phase-change memory (PCM), making it an attractive contender for main memory. However, due to resistance drift per cell caused by long-term storage, data reliability becomes a major challenge. Low-density parity-check (LDPC) codes with improved error correction capability can be used in PCM to reduce bit error rates and thus improve data reliability. More interestingly, when the raw bit error rates (RBER) of various pages in PCM is compared at the same storage time, a considerable gap appears, resulting in high sensing and decoding latency. We propose eLDPC, an efficient LDPC coding scheme for reducing sensing and decoding latency, in this paper. We start with a preliminary experiment, which reveals that there is a significant variation in resistance drifts between adjacent distributions, resulting in a large RBER gap for different pages. Then, using a submatrix of the parity-check matrix to shorten the codeword length, eLDPC is inspired to encode pages with lower RBER. The original bit sequence is separated into even bit sequence (EBS) and odd bit sequence (OBS) for pages with higher RBER. eLDPC is used to encode EBS and OBS independently. By utilizing optimized soft information, EBS and OBS are eLDPC decoded. eLDPC can significantly improve error correction capability of LDPC hard decoding, effectively eliminating soft decoding processes and lowering decoding latency. The results of simulations show that eLDPC can greatly decrease decoding iterations and time.

Optimal Busy-Node Repair of (k+4,k,4) MDS Codes With Small Sub-Packetization Level

Maximum distance separable array codes with small sub-packetization level (MDS-SSL) are of practical importance in distributed storage systems. This letter addresses their repair of a single failed node in the case that there exists a busy node during the repair. Additional check relations among codeword symbols excluding those in the busy node are formed to compensate for the absence of information. Then, it allows us to repair the failed node without symbols in the busy node. A lower bound of the busy-node repair bandwidth is derived for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$(k+4,k,4)$ </tex-math></inline-formula> MDS-SSL codes, consisting of four groups of nodes. It indicates that its achievability requires a cubic constraint among elements in the parity-check matrix. Then, an explicit busy-node repair scheme is proposed to achieve a lower bound in the case of the failed node and the busy node being in different groups.

A Review of Modern and Recent Studies on the Low-Density Parity-Check Technology Approach

Data theory coding is an excellent and well-known branch of study that has produced various crucial solutions to the insoluble challenges of safe data transfers. Last improvements in detecting error techniques have resulted in a significant increase in the use of low-density parity-check (LDPC) code to address critical concerns connected to secure data transfer. Until now, decent efforts have been performed on LDPC codes that target low complexity, high performance, and low bit error rate goals. The final aim of this review is to provide a recent literature understanding of modern improvements previously mentioned and in LDPC encoding and decoding (applicative and theoretical) techniques. A comparative scan of many remarkable LDPC decoding algorithms, 5G standard requirements, popular power management methods, and low-energy LDPC design studies is also shown. Lastly, conclusions are presented by outlining key study results, current concerns, and general thoughts on new research directions possibilities. Index Terms— low-density parity-check encoder/decoder (LDPC), error correction codes (ECC), forward error correction codes (FEC), parity check matrix(PCM).

FPGA-based burst-error performance analysis and optimization of regular and irregular SD-LDPC codes for 50G-PON and beyond.

We evaluate the burst-error performance of the regular low-density parity-check (LDPC) code and the irregular LDPC code that has been considered for ITU-T's 50G-PON standard via experimental measurements in FPGA. By using intra codeword interleaving and parity-check matrix rearrangement, we demonstrate that the BER performance can be improved under ∼44-ns-duration burst errors for 50-Gb/s upstream signals.

A Unified, SNR-Aware SC-LDPC Code Design With Applications to Magnetic Recording

Spatially coupled (SC)-low-density parity-check (LDPC) codes are known to have outstanding error-correction performance and low decoding latency, which make them an excellent choice for high-density magnetic recording (MR) technologies. Whereas previous works on LDPC and SC-LDPC codes mostly take either an asymptotic or a finite-length design approach, we propose a unified framework for jointly optimizing the codes’ thresholds and cycle counts to address both regimes. We focus on circulant-based (CB) SC-LDPC code family as a representative, high-performance exemplar of structured SC-LDPC codes. The framework is based on efficient traversal and pruning of the code search space, building on the fact that the performance of a CB SC-LDPC code depends on some characteristics of the code’s partitioning matrix, which by itself is much smaller than the code’s full parity-check matrix. We then propose an algorithm that traverses all non-equivalent partitioning matrices and outputs a list of codes, each offering an attractive point on the trade-off between asymptotic and finite-length performance. Our simulations show that our framework results in SC-LDPC codes that outperform the state-of-the-art constructions, over both additive white Gaussian noise (AWGN) and partial response (PR) channel models, and that it offers the flexibility to choose low-signal-to-noise ratio (SNR), high-SNR, or in- between SNR region considering system requirements, e.g., that of the MR device.

A Low-Complexity Ordered Statistic Decoding of Short Block Codes

This letter is concerned with a generalized ordered statistic decoding (OSD) algorithm, called locally constrained OSD (LC-OSD). Instead of order- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$t$ </tex-math></inline-formula> reprocessing on the most reliable independent bits, the LC-OSD searches for test error patterns using the serial list Viterbi algorithm (SLVA) over a trellis specified by a local parity-check matrix. We derive several early stopping criteria that can be used to reduce the number of searches. Numerical results show that the LC-OSD algorithm with the proposed stopping criteria has much lower time complexity than the original OSD but incurs negligible performance loss.