Parasitic Wire Research Articles

Design of Single Input Multiple Output Buck Converter with Light Load Efficiency

The major demand for portable electronics devices such as pagers, laptops, cellular phones etc. Single input multiple output (SIMO) converter will be proposed to give different supply voltages while keep up prolong battery life. A single-discharge (SDC) control scheme is introduce to simplify the Single inductor multiple output design, attain to low cross regulation, and to support board range of loads with decent efficiency of power. A Single discharge control single input multiple output buck converter with 4 outputs composed of comparators, phased-locked loop, finite state machine (FSM) controller, and an output stage. In addition to the basic switching functions, the FSM controller provides a state skipping feature to allow no-load regulation. Single input multiple output converter is available for less cost and used for maintaining long battery life and they are growing in vast range with rich feature portable electronic device. The design of converter is designed for limited range for prolonged battery life. The SIMO converters are used for the reduction of cost and switching losses, hence improve system efficiency. In our study, we proposed buck converter topology with single input of 24v and multiple output of 12v and 5v. The 12v voltage is used for electric vehicles. In electric vehicles it is used in horns and headlights. 5v voltage is used for small signal and stability analysis. The simulated conversion efficiency for peak power is 86% the power ranging for output is 50 to 300mW. The ICs exhibit has a low measured peak efficiency of 73% and cross regulation of 0.24 mV/mA because of parasitic bond wire resistance. The proposed system is simulated in MATLAB/Simulink software.

Efficiency Enhancement in a Wireless Power Transmission System Using Parasitic Components

In this paper, we present a rigorous optimization method to design a wireless power transmission (WPT) system. In order to enhance the power received by the receiver, parasitic components are integrated into the system. Our analysis shows that a system with square parasitic wire actually gives better performance than its circular counterpart. From our results, it can be seen that the presence of square parasitic wires in the system improves considerably the efficiencies, as well as the distance of effective power transfer. By implementing two square parasitic wires and using an optimization algorithm to carefully select the positions of the receiving antennas, we show that power coupled to one receiver can be significantly enhanced; while the other suppressed – the peak power at the receiving antenna is improved to 15.7% and the power detected by the adjacent antenna is minimized to as low as 2.6%. This result is important as it shows that the parasitic components do not only enhance the power coupled to the receiving antenna, it also effectively reduces crosstalk in adjacent antennas. Indeed, it can be observed that the peak efficiency obtained using two parasitic wires (with the transmitter sandwiched in between the two wires) is almost twice of that using a single wire.

Gain enhancement for circularly polarized double layered printed hemispherical helical antenna arrays

To improve the performance of mobile satellite communications, such as for INMARSAT-M mobile vehicles, antenna with high gain and circular polarization over a wide angular range is important. With only 3-elements circularly polarized double-layered printed hemispherical helical antenna arrays that incorporated with parasitic helical wire in the structure, the array can produce significant improvement where it has been demonstrated that the gain and the 3 dB axial ratio (AR) bandwidth and beam width can be increased by properly adjusting the relative angular displacement δ1, δ2, δ3, and the inter-element spacing dx and dy. Experimental and theoretical results demonstrate that the array can produce a gain of 11 dBi, the 3 dB AR bandwidth of more than 11% with AR beam width of ~136°, and the mutual couplings between each element less than −23 dB at required 3 dB AR bandwidth frequency range. The antenna design is performed in computer simulation technology and verified by measurement.

Circularly Polarized Double Layered Printed Hemispherical Helical Antenna with a Parasitic Wire for Bandwidth Enhancement

Circularly Polarized Double Layered Printed Hemispherical Helical Antenna with a Parasitic Wire for Bandwidth Enhancement

Evolutionary Design of Wide-Band Parasitic Dipole Arrays

An innovative antenna design technique, based on evolutionary programming, has been devised and applied to the design of broadband parasitic wire arrays for VHF-UHF bands with a significant gain. The chosen fitness function includes far-field requirements, as well as wideband input matching specifications. The latter requirements, which must be present in every useful antenna design, allow to stabilize the algorithm, and to design both optimal and robust antennas. The designed antennas show significant improvements over existing solutions (Yagi and LPDA) for the same frequency bands.

Multi-Functional, Magnetically-Coupled, Electrically Small, Near-Field Resonant Parasitic Wire Antennas

Several electrically small antenna systems that utilize the magnetic couplings between a coaxially-fed semi-loop antenna and capacitively-loaded loop (CLL)-based near-field resonant parasitic (NFRP) elements are presented. Both one and two gap CLL elements are considered; their impact on the system performance, particularly their effects of the resonance frequencies and the corresponding Q values, is evaluated. By integrating multiple NFRP CLL elements with the coaxially-fed semi-circular loop antenna, electrically small multi-band systems are achieved. They can be designed for a broad range of frequencies by tuning the NFRP elements separately. Dual band designs are reported that achieve operation at the GPS LI (1.5754 GHz) and L2 (1.2276 GHz) frequencies. Their operational modes and performance characteristics are studied. These lead to additional electrically small antenna designs, which feature only one driven loop antenna and two NFRP CLL elements and which achieve circularly polarized (CP) operation. A CP antenna whose electrical size is ka = 0.495 at the GPS LI frequency is presented in detail. Its simulated bandwidth and beamwidth, for which the axial ratio (AR) is less than 3 dB, are, respectively, 7.8 MHz and 76°.

Short backfire antenna with microstrip Clavin feed

A single short backfire antenna has an enclosed structure with no sharp projections and approximately 15 dBi gains, making it attractive for handheld radio monitoring and other man-portable applications. However, a microstrip patch fed short backfire antenna had a broad E -plane radiation pattern main lobe, leading to a loss of gain and low aperture efficiency. The antenna was studied using a commercially available method of moment's software. Adding eight parasitic wires inside the cavity of a short backfire was found to narrow the E -plane radiation pattern main lobe, making it more like the H -plane radiation pattern and increasing the peak gain by 1.5 dB. A single proof of concept antenna was built at 1.49 GHz, which had a bandwidth of 2.3%, aperture efficiency of 78% and was shown to have equalized principal plane main lobes.

Axial mode elliptical helical antenna with parasitic wire for CP bandwidth enhancement

Elliptical helical antenna using parasitic helix to enhance the axial ratio (AR) bandwidth is presented. The parasitic wire increases the AR bandwidth (AR<3 dB) from 13.6 to 25%, and enhances the directivity by 2 dB in the frequency band interested, while maintaining the simple single feeding system. The simulated results and experimental results including AR, impedance and radiation patterns are given, and some good agreements are observed.

Battery Protection IC Integrating Bi-directional Trench Lateral Power MOSFETs

We developed a battery protection IC integrating a low specific on-resistance bi-directional trench lateral power MOSFET (BTLPM). In the bi-directional switches, two MOSFETs share a drain region and there is neither drain contact nor drain metal wire. The developed bi-directional switches have a breakdown voltage of 23V and a specific on-resistance of 6.8mΩmm2 per one side MOSFET. Wafer-level Chip Size Package (W-CSP) is utilized, and the chip mounting area can be reduced to 3mm2, which is less than one-third of conventional multi-chip system. Parasitic wire resistance is also reduced to 5.3mΩ, which is about one-seventh of that of conventional package without thick copper layer.

Analysis of intrachip electrical and optical fanout

We examine the benefits of electrical isolation in intrachip optical signaling. We calculate the delay and energy metrics of an optical interconnect with fanout driving an electrical load. By examining fanout and including load drivers into delay equations, we make a shift from the general trend of looking at optical interconnects as a replacement for long parasitic wires. Our calculations show that optical fanout provides a large improvement in an Etau2 (energy delay squared) metric and improves performance even at very short intrachip distances. The break-even length corresponds to the wiring length of 250 minimum-size inverters that are compactly laid out. These results provide a compelling reason to further examine the implementation of optical interconnects.

Small Planar Monopole Antenna With a Shorted Parasitic Inverted-L Wire for Wireless Communications in the 2.4-, 5.2-, and 5.8-GHz Bands

A low-profile planar monopole antenna with a shorted parasitic inverted-L wire fed using a microstrip feedline for wireless communications in the wireless local-area network (WLAN) bands is studied. The driven monopole element and shorted parasitic wire can separately control the operating frequencies of two excited resonant modes, which cover the 2.4-, 5.2-, and 5.8-GHz WLAN bands. This antenna design is not only suitable as a monopole antenna but also as a diversity antenna for 2.4-, 5.2-, and 5.8-GHz band operations. The lower mode of the proposed antenna has an impedance bandwidth (2:1 VSWR) of about 188 MHz (2313-2501 MHz), which covers the required bandwidth for 2.4 GHz WLAN band (2400-2484 MHz); on the other band, the upper mode has a bandwidth of about 2843 MHz (3930-6773 MHz) covering the HIPERLAN band (5150-5350 MHz) and 5.8-GHz WLAN band (5725-5852 MHz). For frequencies across the three operating bands, the proposed antenna shows similar monopole-like radiation patterns, and good antenna gain across the operating bands is obtained. Details of the design considerations for the proposed antenna are described, and the experimental results of the antenna performances obtained are presented and discussed.

Wide-band sleeve-cage and sleeve-helical antennas

A sleeve-cage monopole has parasitic wire elements that form a sleeve around the driven cage antenna. Appropriate placement and dimensions of the wire parasites lead to bandwidth enhancement. Genetic algorithms and an integral equation solver are employed to determine the position and lengths of the parasitic wires in order to minimize voltage standing wave ratio (VSWR) over a band. The cage is replaced by a normal-mode quadrifilar helix for height reduction and the resulting structure is referred to as a sleeve helix. Measured VSWR and input impedance data are in good agreement with computed data. A fabricated sleeve-cage monopole has a bandwidth ratio of 4.4:1 and a sleeve helix has a bandwidth ratio of 3.5:1 for measured VSWR less than 3.5.

A novel process and thermodynamic mechanisms of air gap formation for ULSI application

In this study, a novel process to fill the gap between the metal lines on a wafer with air is developed. Reduction of the parasitic wire capacitance in ULSI has become an important issue for future high-speed and low-power applications. Use of low dielectric constant material as inter-level dielectric (ILD) can overcome this problem. Many new low dielectric constant materials are under study and lower dielectric constant and feasibility are the two goals of these researches. The gas-dielectric process has the lowest dielectric constant, 1.0, and its conceptual feasibility is demonstrated. Basic process characterization data, thermodynamic mechanism and requirements for air gap formation are also discussed. We calculated the relationship among the surface tension, the vaporization rate and atmospheric pressure to construct a model of the process window to show that this process is feasible and reproducible. Scanning electron microscope data show that a large area of air gap can be obtained. Basic electrical characteristics data such as I–V and C–V, measured and compared with the conventional PECVD process, show that the air gap has better isolation than PECVD process.

An Outer-Fed Spiral Antenna Array Radiating a Circularly Polarized Conical Beam

An array composed of spiral elements, each having a small number of turns, is numerically analyzed. The spiral elements are circularly arrayed above a ground plane and are excited by a single vertical feed wire. As the number of the spiral elements increases, the copolarization component of the radiation becomes omnidirectional. The maximum variation in the copolarization component as a function of azimuth angle is 0.8 dB for four spiral elements. Attention is also paid to an improvement in the axial ratio. A technique of using parasitic wires around the feed wire is presented. Calculations show that, when the distance between the feed wire for four spiral elements and the parasitic wires is appropriately chosen, the axial ratio is improved. The 3-dB axial ratio frequency bandwidth evaluated in the maximum beam direction is found to be 10%. Within this bandwidth, the gain is more than 5 dB.

Transient analysis of two coupled horizontal wires over a real ground

Transient behaviour of two coupled wires immersed in a two-media configuration is analysed. The active wire is excited by a time-dependent voltage source. As the wires are identical, the symmetry of the configuration is expoited, and two coupled wires are considered as two single-wire problems. Each mode is represented by the corresponding space–time integral equation of the Hallen type. The effect of real ground is taken into account by the space–time reflection coefficient appearing within integral-equation kernels. The set of decomposed Hallen integral equations is solved by the direct time-domain finite-element technique, and the corresponding transient response is obtained. The computed numerical results are compared with the time-domain data obtained by solving the frequency-domain electric field integral equation for thin wires and with the aid of the Fourier transform approach. The mathematical model is applicable to an arbitrary ground, and numerical implementation and calculations are presented for lossless cases. Illustrative numerical results for transient current along the active and the parasitic wire are shown for the case of a perfectly conducting half-space and a dielectric half-space.

A novel GaAs flip-chip power MODFET with high gain and efficiency

A novel GaAs flip-chip power MODFET with a spike-gate structure has been developed for high-gain and high-efficiency operation under extremely low supply voltages. The spike-gate MODFET is featured by a unique gate structure that has almost zero effective gate length. The spike gate provides both a low on-resistance of 1.5 Ω mm and a high transconductance of 280 mS/mm without increasing the drain conductance. The flip-chip bonding, with an Au–Sn alloy system, has been used for mounting of the spike-gate power MODFET on an AlN substrate. The thermal resistance of the flip-chip power MODFET is 12°C/W which is lower than that of a conventional wire-bonded MODFET. The power-added efficiency (PAE) of 71% at the output power of 30.0 dBm can be obtained even when the supply voltage is reduced to 1.5 V. By eliminating parasitic wire inductance, the linear gain of the MODFET is 2 dB higher and the PAE is 5% higher than that of the conventional wire-bonded MODFET.

A layout-based schematic method for very high-speed CMOS cell design

In very high-speed CMOS cell design, the result of schematic simulation is inaccurate because of missing parasitic components, such as diodes and parasitic capacitances. Designer cannot pass enough information to the simulator by conventional transistor symbols, therefore, simulation error occurs. In this paper, we address a layout-based schematic (LBS) method for high-speed CMOS cell design. In this method, we introduce several types of MOS transistors and estimate parasitic wire capacitances by using layout knowledge. The simulation results show that the difference between LBS and real layout is much smaller, less than 3% in rise time, compared to in the worst case of up to 65% in the original schematic. This method can be applied to both digital and analog circuits and it is helpful for layout automation. Time and cost will be reduced in high-speed circuit design.

Slot antenna with parasitic elementfor dual band operation

The authors introduce three types of dual band antenna combining a slot and a parasitic wire. The slot and the parasitic wire are designed to become resonant at two different bands. The antenna characteristics are calculated by the method of moments; calculated VSWRs are in good agreement with measured data.

Comments, with reply, on "A simplification of the synthesis of parallel wire antenna arrays" [with reply

The commenter calls attention to earlier work by K. Hirasawa and D.H. Sinnott (see ibid., vol.AP-20, p.661-3, Sept. 1972) and S.M. Sanzgiri and J.A. Cummins (see ibid., vol.AP-21, p.380-2, May 1973), in which the relationship between point source array theory and a method of moments formulation of a parallel wire array antennas was clearly described. He points out that the above-titled paper by K. Siakavara and J.N. Sahapos (see ibid., vol.AP-37, p.936-40, July 1989) should have referenced this work and identified in what way their own work contributed something new. One of the authors replies, thanking the commenter for drawing attention to the earlier papers and providing the comparison requested. It is pointed out that in the paper under consideration, emphasis was given to the engineering applications, where an improvement in the design was found by using parasitic wire antennas.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Surface-wave phenomena in phased slot arrays with parasitic wire arrays

Blind spots observed in structures consisting of a slot array and parasitic straight wire arrays are investigated. Each blind spot is found to be associated with either a pattern null or the excitation of a surface wave on the corrugated structure consisting of the parasitic wires and conducting screen, with the slots shorted. The plane-wave-expansion technique is used to evaluate the coupling between arrays. It is shown analytically that for structures consisting of a single wire array, the blind spot can exist only at broadside, where there is a pattern null for the parasitic wires. For structures with two-wire arrays, such as an array of Clavin elements, a surface wave can be excited at a particular scan angle provided a certain uniformity condition in the structure is satisfied. The information presented is relevant to the incorporation of parasitic wire arrays for scan compensation. >