Parasitic Parameters Research Articles

Design and analysis of power decoupling based microinverter considering parasitic parameters

With fossil energy reducing year by year, more and more attention to the new energy sources greatly promotes the development of the distributed power generation system, especially the low-power photovoltaic system. However, the power injected into the single-phase grid is time-varying, an electrolytic capacitor with large bulk should be paralleled with PV to balance the input and output power ripple. But the electrolytic capacitor has a very short lifetime, which could shorten the whole inverter’s lifetime. In this paper, the operational principle of the power decoupling based microinverter considering parasitic parameters is proposed, in which a film capacitor with small capacitance value replaces the electrolytic capacitor to improve the lifetime of the inverter. Further, the operating mode of the transformer and the decoupling capability is analyzed, and obtains the reasons affecting the inverter steady-state performance. Finally, the simulation and experiment validation of the proposed microinverter have been accomplished. Base on the analysis method proposed in this paper, a more accurate device selection can be provided for industrial design.

High‐Gain Boost Converter Based Energy Harvesting Method for the Ultra‐Low Voltage Difference of HVDC Transmission Line

ABSTRACTOnline monitoring sensors are crucial for ensuring the long‐term stable operation of high‐voltage direct current (HVDC) transmission systems. However, ensuring a sustainable and reliable energy supply for these sensors in the HVDC transmission line is extremely challenging. Energy harvesting is an efficient solution to meet the energy supply needs of self‐powered online monitoring sensors. This work proposes a novel method for harvesting energy from the ultra‐low voltage difference of HVDC transmission line using a high‐gain boost converter. Firstly, the structure of the energy harvesting system is proposed. Then, the mechanism by which the gain of the boost converter is easily affected by parasitic parameters of the circuit and device under ultra‐low input voltage is analyzed. A method for automatically stabilizing the output voltage of the boost converter using a post‐stage energy management circuit is proposed. This method avoids the use of closed‐loop control circuits, which would otherwise increase losses. Finally, the boost converter with high gain is designed to elevate the ultra‐low voltage difference to a higher voltage, providing sufficient power for the online monitoring sensors. The effectiveness of the proposed method has been verified through simulations and experiments, demonstrating that the energy harvesting system can extract energy from a voltage difference as low as 35 mV. Additionally, the system can produce a stable output power of up to 128 mW when the voltage difference is 100 mV.

Differences of in vitro immune responses between patent and pre-patent Litomosoides sigmodontis-infected mice are independent of the filarial antigenic stimulus used.

Lymphatic filariasis and onchocerciasis are neglected tropical diseases and cause significant public health problems in endemic countries, especially in sub-Saharan Africa. Since the human parasites are not viable in immune-competent mice, animal models have been developed, among them Litomosoides sigmodontis which permits a complete life cycle in BALB/c mice, including the development of patent infections with circulating microfilariae (Mf, the worm's offspring). To investigate the immunomodulatory properties of helminths in vitro, antigenic extracts can be prepared from different life cycle stages of the L. sigmodontis model, including adult worms, but the methods to prepare these antigens differ between research groups. This study analyzed whether different centrifugation methods during the preparation of an antigenic extract, the gender of used worms, or the different fractions (soluble or pellet) altered filarial-specific CD4+ Tcell responses. These cells were isolated from pre-patent or patent/chronic infected mice, hence those without and those with Mf, respectively. Ex vivo immune responses were compared at these two different time points of the infection as well as the parasitic parameters. Worm burden and cell infiltration were elevated in the thoracic cavity (TC) and draining mediastinal lymph nodes at the pre-patent stage. Within the TC, eosinophils were significantly up-regulated at the earlier time point of infection which was further reflected by the eosinophil-related eotaxin-1 levels. Regarding the production of cytokines by re-stimulated CD4+ T cells in the presence of different antigen preparations, cytokine levels were comparable for all used extracts. Our data show that immune responses differ between pre-patent and patent filarial infection, but not in response to the different antigenic extracts themselves.

Design and fabrication of integrated negative feedback resistor for InGaAs/InP avalanche photodiode

The serial resistor of alloy material can be integrated on negative feedback avalanche diodes to reduce afterpulsing effect. In this work, the influence of parasitic capacitance on the avalanche quenching resistor was theoretically analyzed. By using simulation model of device & circuit mixed-mode, the quenching capability of integrated resistors was evaluated with the parasitic parameters. For the material growth of feedback quenching resistor, thin film based on CrSi alloy was prepared by ion beam sputtering process, realizing the sheet resistance of 3 kΩ/square. The resistor material were sufficiently investigated by characterizing the morphology and element component. CrSi pattern of spiral shape was fabricated on sapphire substrate, realizing a resistor of the order of 500 kΩ in area of diameter 40 μm, which was equivalent to the active area of avalanche diodes. The electrical measurement indicated the excellent temperature stability of this integrated resistor, showing the promising application prospect for preparing high-performance negative feedback avalanche diodes.

An ultra-high gain boost converter with low switching stress for integrated multi-energy storage systems

In this paper, a high-gain low-switching-stress coupled-inductor with high voltage step-up voltage multiplier cells quadratic boost converter (VMC-QBC) is proposed. The turn ratio of the coupled inductors and the switch duty cycle increase the dynamic gain, and the two degrees of freedom adjustment and modularity of the voltage multiplier cells (VMC) make the structure more flexible. The use of the same drive signal for both switches makes control easier. While achieving multi-stage boosting and multiplication boosting from low to medium duty cycle, the passive clamping circuit absorbs the energy leaked by the coupled inductor, thus reducing the stress on the switching tube and alleviating the diode reverse recovery problem. A non-ideal model with parasitic parameters is developed to analyse the real voltage gain and the converter losses to give design guidelines. A 300 W prototype is designed and tested. The state space model of the converter is established and the working principle is analysed. Compared to other high-gain quadratic boost converters, the proposed converter has continuous input current, common ground characteristics, and high voltage gain at low to medium duty cycles to accommodate integrated multi-energy storage systems.

Smart-CX – Method of extraction of parasitic capacitances in ICs

This paper proposes a novel rule-based parasitic capacitance extraction methodology, integrated into Smart-CX, to enhance the accuracy of SPICE simulations and physical verification of ICs. This methodology is crucial during the microchip design phase, particularly in preparation for fabrication on mature to advanced process nodes. The proposed enhanced analytical method addresses the accuracy/time tradeoffs between numerical and analytical extraction techniques. This study validates the accuracy of the methodology by comparison of the extracted parasitic parameters with foundry-provided 2D-models. The parasitic capacitances that are extracted within this method include: area capacitances (Ca), coupling capacitances (Cc), including via-to-via capacitances (Cmv), contact-to-gate capacitances (Cmg), contact-to-active capacitances (Cmc) and fringe type capacitances with the top (Cft) and bottom (Cfb) conductive layers.

Research on Gate Charge Degradation of Multi-Chip IGBT Modules in Power Supply for Unmanned Aerial Vehicles

In recent years, with the burgeoning application of high voltage in various industrial sectors, the deployment of unmanned equipment, such as industrial heavy-load Unmanned Aerial Vehicles (UAVs), incorporating high-capacity Insulated-Gate Bipolar Transistors (IGBTs), has become increasingly prevalent. The demand for high-voltage IGBT modules in UAV is continuously growing; therefore, exploring methods to predict fault precursor parameters of multi-chip IGBT modules is crucial for the operational health management of unmanned equipment like UAVs. This paper analyzes the gate charge degradation in multi-chip IGBT modules after thermal cycling, which can be used to evaluate the operational state of these modules. Furthermore, to delve into the electrical response of a gate drive circuit caused by local damage within the IGBT module, an RLC model incorporating parasitic parameters of the gate drive circuit is established, and a sensitivity analysis of the peak current in the gate charge circuit is provided. Additionally, in the experimental circuit, an open sample of an IGBT module with partial bond wires lifted off is used to simulate actual faults. The analysis and experimental results indicate that the peak current of the gate charge is closely related to L and C. The significant deviation in the gate current, influenced by the partial bond wires lift-off, can provide a basis for the development of predictive methods for IGBT modules.

Evaluation of the power loss in IGBT single transistor device under the condition of pulse duration of 100 ns

The improvement in the reliability and lifespan of insulated gate bipolar transistor (IGBT) devices and the enhancement of system efficiency under high-frequency pulse conditions are receiving increasingly wide attention, and all of these are closely related to the evaluation of the power loss of the IGBT. The traditional method for assessing the power loss of the IGBT is through curve fitting of the dual-pulse experimental results, without delving into the conduction process of the IGBT and without considering the IGBT model itself and the parasitic parameters present in the test circuit. In response to the condition of a pulse duration of 100 ns for IGBT single devices, a universal test circuit has been designed to measure the collector-emitter voltage waveform and the collector current waveform. A method based on Computer Simulation Technology for field-circuit co-simulation to evaluate the power loss of the IGBT has been proposed, which takes into account the parasitic parameters in the actual circuit. In this method, the 3D model of the IGBT device, as well as the circuit model of the test circuit, is established. The power loss curve of the IGBT was obtained from the evaluation model, and the results agree well with the power loss curve obtained from experiments. This method provides guidance for seeking lower power loss in order to improve the reliability and lifespan of the IGBT, as well as enhance system efficiency. It also provides theoretical guidance for further research on the thermal damage mechanism of the IGBT.

Junction temperature monitoring of silicon carbide MOSFET based on turn‐off voltage spike

AbstractBecause of the advantages of high switching speed, silicon carbide (SiC) devices are widely used in high‐power power electronic equipment. Real‐time monitoring of junction temperature is very important for the safe operation of equipment. There have been many studies on traditional junction temperature monitoring methods based on Si IGBT, but the dynamic characteristics of SiC MOSFETs are changed due to their different physical structure and parasitic parameters, which make the traditional methods no longer applicable. In this paper, the junction temperature can be extracted from the switching process of SiC MOSFET by using the turn‐off voltage spike as the index of thermosensitive electrical parameter (TSEP). In addition, the effect of working voltage, current, and different materials on turn‐off voltage spike is also studied. The simulation platform of Ansys/Simplorer and the experimental test platforms are built, and the theory of junction temperature detection based on turn‐off voltage spike is verified. The simulation and experimental results show that turn‐off voltage spike is a feasible TSEP, which can be used to extract junction temperature of SiC MOSFET with good linearity and instantaneity.

Critical and Parasitic Parameters Identification and Frequency Regulation Strategies for UWPT Systems

Critical and Parasitic Parameters Identification and Frequency Regulation Strategies for UWPT Systems

Improved Design of a SiC MOSFET Gate Drive with Crosstalk Suppression Capability

For high-frequency switching applications, silicon carbide (SiC) devices are more suitable than silicon-based devices, which is conducive to improving the efficiency and power density of power electronic equipment. However, as the switching frequency increases, the influence of parasitic parameters on the switching characteristics of devices becomes increasingly apparent. When SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) are applied in bridge circuits, the crosstalk problem easily occurs with the complementary conduction of upper and lower transistors, which seriously limits the promotion of SiC MOSFETs. However, the existing crosstalk suppression drive circuit tends to increase the switching loss, switching delay, and control complexity; therefore, a gate drive with crosstalk suppression capability is proposed. In this paper, the gate drive has two features: a negative voltage to shut down the SiC MOSFET; and an adjustment of the gate-source equivalent impedance. To accomplish this goal, the mechanism of crosstalk voltage generation is analyzed. Furthermore, the operation principle of the gate drive is analyzed, and the parameters of the gate drive are designed. Eventually, the proposed gate drive is verified by an LTspice simulation and experimental platform. The results prove that the gate drive can suppress the crosstalk voltage without affecting the switching speed.

Security Control for a Fuzzy System under Dynamic Protocols and Cyber-Attacks with Engineering Applications

The objective of this study is to design a security control for ensuring the stability of systems, maintaining their state within bounded limits and securing operations. Thus, we enhance the reliability and resilience in control systems for critical infrastructure such as manufacturing, network bandwidth constraints, power grids, and transportation amid increasing cyber-threats. These systems operate as singularly perturbed structures with variables changing at different time scales, leading to complexities such as stiffness and parasitic parameters. To manage these complexities, we integrate type-2 fuzzy logic with Markov jumps in dynamic event-triggered protocols. These protocols handle communications, optimizing network resources and improving security by adjusting triggering thresholds in real-time based on system operational states. Incorporating fractional calculus into control algorithms enhances the modeling of memory properties in physical systems. Numerical studies validate the effectiveness of our proposal, demonstrating a 20% reduction in network load and enhanced stochastic stability under varying conditions and cyber-threats. This innovative proposal enables real-time adaptation to changing conditions and robust handling of uncertainties, setting it apart from traditional control strategies by offering a higher level of reliability and resilience. Our methodology shows potential for broader application in improving critical infrastructure systems.

Analysis of Parasitic Parameters and Winding Loss Characteristics of High-Frequency Transformer under Different Winding Structures

Abstract With the development of the smart grid and the increasing access of renewable energy to the distribution grid, the traditional AC power grid puts forward an urgent demand for power electronic transformer (PET). The high-frequency transformer (HFT) serves as the core equipment of PET, and its electromagnetic structure and parasitic parameters are the hot spot of study in the field of power electronics. In this paper, the parasitic parameters, winding loss, and leakage magnetic field characteristics of the 20 kHz, 20 kVA HFT are investigated under different winding structures. The results show that the higher the degree of crossover of HFT winding, the lower the leakage magnetic field. The cross winding reduces winding loss and leakage inductance, and also attenuates the impact of frequency variations. The higher the winding height, the lower the leakage inductance. As the insulation thickness increases, the leakage inductance rises. The distribution capacitance varies opposite to the leakage inductance. Based on the analysis of winding loss and parasitic parameters, as well as the consideration of insulation, the final winding layout, the height of winding and the thickness of insulation of the HFT are determined.

A new winding structure with low common‐mode current in input series output parallel planar transformer LLC converter

AbstractMHz switches and integrated magnetic planar transformers (PT) promote the high density and miniaturization of DC/DC converters. The parasitic parameters of the PT at high frequency significantly affect the performance of converters, resulting in severe electromagnetic interference (EMI) problems. Firstly, this paper proposes a new common‐mode (CM)‐suppression winding structure for the input series output parallel (ISOP) matrix transformer LLC converter. The sources and conduction principle of CM noise are analyzed. Furthermore, this optimization based on winding shape and position is simple and feasible, suppressing the CM noise significantly. Compared with conventional multilayer winding structure, this optimization increases the current‐carrying area by 2.8%–5.9%, effectively improving the primary current distribution. In addition, the proposed structure makes the best planar windings in footprint with expanded windings, bringing the simplest layout in the primary winding. Finally, a 1 MHz 400 V/12 V 300 W LLC converter is constructed to verify the effect of this winding structure. The results show that a 40% reduction in CM current can be achieved while maintaining the current balance.

Sigmoid function model of parallel-connected DC-DC converters and analysis of their dynamic characteristics.

Because of the manufacturing variations of circuit elements and the effects of parasitic parameters, the switching elements of parallel-connected modules cannot be synchronously switched. Consequently, the characteristics of these converters, which are multi-mode, high-order systems, cannot be comprehensively described using reduced-order models based on the symmetry of circuit topology and parameters. It is also difficult to fully describe the characteristics of these systems using discrete mapping models and averaged models. Therefore, we developed a smooth, sigmoid function-based continuous-time model for systems comprising parallel-connected buck converters with average current-sharing control. The proposed model provides a unified description of the continuous and discontinuous conduction modes of the system. The criteria for ensuring the stability of the system were derived based on the Floquet theory. The nonlinear dynamic behavior of the system and the effects of the key parameters on the stability of the system were investigated. The results showed that the system may undergo period doubling bifurcation, border collision bifurcation, and Neimark-Sacker bifurcation as the system parameters varied. The theoretical analysis and simulation results were verified experimentally. Our results provide a basis for the configuration of controller parameters.

FEATURES OF ENSURING ELECTROMAGNETIC COMPATIBILITY OF UNINTERRUPTIBLE POWER SYSTEMS

An overview of the main structures of uninterruptible power systems is provided. The impact on internal-system and external-system electromagnetic compatibility of these devices is determined. Contemporary standards and requirements for ensuring electromagnetic compatibility of uninterruptible power systems are analyzed. Features of the structures of uninterrupted power systems such as online, offline and line interactive by the conductive path of propagation of interference are given. The main advantages of eco uninterrupted power supply are summarized. A generalized approach is proposed for the application of radiofrequency interference filters depending on the electromagnetic environment and features of uninterruptible power systems. Refined limitations on the possibilities of adjusting the basic and influence parasitic parameters of the filter links by symmetric and asymmetric propagation of conductive disturbances. The possibility of using remote control of the effectiveness of means of reducing conductive disturbances was assessed. The expediency of localization of control parameters of smart radiofrequency interference filters with the use of artificial intelligence is determined. References 10, figures 6, tables 2.

A 7.2‐mW 0.5–7.5‐GHz ultra‐wideband low‐noise amplifier with 4 dB noise figure and 20 dB gain using 40 nm CMOS technology

AbstractThe technology, design procedure, and measurements of an ultra‐wideband (UWB) push–pull high‐performance complementary metal‐oxide semiconductor (CMOS) low‐noise amplifier (LNA) are presented in this letter. While the push–pull LNA exhibits commendable direct current (DC) power consumption, its operational bandwidth is often limited by the inherent parasitic parameters of the transistors. To exploit the parasitic parameters of the transistors, a multipole‐tuning circuit that utilizes pole‐tuning inductors and parasitic capacitors of the MOS to extend the operational bandwidth is proposed. A UWB LNA is implemented using a commercial 40‐nm CMOS process, and the measurement results demonstrate a peak gain of 20.2 dB, an exceptionally wide bandwidth of 0.5–7.5 GHz, a noise figure of 4 dB, and an output power of 3.5 dBm at OP1 dB with 7.2 mW DC power consumption. The chip area of the LNA is a compact 0.26 mm2. Experimental results closely align with simulations, confirming the validity of the concept and showcasing its competitive performance.

Parasitic-Based Model for Characterizing False Turn-On and Switching-Based Voltage Oscillation in Hybrid T-Type Converter

High frequency and high voltage switching converters utilizing wide bandgap semiconductors are gaining popularity thanks to their compactness and improved efficiency. However, the faster switching requirements gives rise to new challenges. A key issue is the increased oscillation of the drain–source voltage caused by the switching action of the complementary switch in the same phase or change of state of the other phase switches. The voltage stress caused by these oscillations can damage the switch. Furthermore, the high dv/dt during turning-on of one switch might result in false turn-on of the complementary switch due to the miller effect. In this paper, these issues are investigated in a T-type converter through analytical and experimental analysis. Based on the proposed analytical approach, simple and cost-wise solutions utilizing an optimum design of gate driver circuits and circuit layout modifications can be developed to cope with the aforementioned issues. A comprehensive analytical model of the converter with consideration of parasitic capacitances and inductances is developed. By performing sensitivity analysis on the model, the effect of the parasitic parameters on the drain–source voltage oscillation and gate–source voltage amplitude in case of false turn-on is studied. The validity of the model is then assessed through numerical simulations and experimental results.

Year-round monitoring of three water sources in Québec, Canada, reveals site-specific differences in conditions for Cryptosporidium and Giardia contamination.

Cryptosporidium and Giardia are protozoan parasites responsible for gastrointestinal illnesses in humans and in animal species. The main way these parasites are transmitted is by ingestion of their (oo)cysts in drinking water. Monitoring (oo)cysts in water sources is beneficial to evaluate the quality of raw water supplying treatment plants. Currently, the only standardized protocol to enumerate these parasites from water samples is United States Environmental Protection Agency (USEPA) Method 1623.1. With this method, we monitored three major water sources in Quebec over a year to assess temporal and geographical variations of these parasite (oo)cysts. These three water sources have independent watersheds despite being in the same region. We found a general pattern for Giardia, with high concentrations of cysts during cold and transition periods, and significantly lower concentrations during the warm period. Cryptosporidium's concentration was more variable throughout the year. Statistical correlations (Pearson's correlation coefficients) were established between the concentration of each parasite and various environmental parameters. The three study sites each showed unique factors correlating with the presence of both protozoa, supporting the idea that each water source must be seen as a unique entity with its own particular characteristics and therefore, must be monitored independently. Although some environmental parameters could be interesting proxies to the parasitic load, no parameter was strongly correlated throughout the whole sampling year and none of the parameters could be used as a single proxy for all three studies sources.

A multichannel thermal bubble-actuated impedance flow cytometer with on-chip TIA based on CMOS-MEMS

Electrochemical impedance spectroscopy (EIS) flow cytometry offers the advantages of speed, affordability, and portability in cell analysis and cytometry applications. However, the integration challenges of microfluidic and EIS read-out circuits hinder the downsizing of cytometry devices. To address this, we developed a thermal-bubble-driven impedance flow cytometric application-specific integrated circuit (ASIC). The thermal-bubble micropump avoids external piping and equipment, enabling high-throughput designs. With a total of 36 cell counting channels, each measuring 884 × 220 μm2, the chip significantly enhances the throughput of flow cytometers. Each cell counting channel incorporates a differential trans-impedance amplifier (TIA) to amplify weak biosensing signals. By eliminating the parasitic parameters created at the complementary metal-oxide-semiconductor transistor (CMOS)-micro-electromechanical systems (MEMS) interface, the counting accuracy can be increased. The on-chip TIA can adjust feedback resistance from 5 to 60 kΩ to accommodate solutions with different impedances. The chip effectively classifies particles of varying sizes, demonstrated by the average peak voltages of 0.0529 and 0.4510 mV for 7 and 14 μm polystyrene beads, respectively. Moreover, the counting accuracies of the chip for polystyrene beads and MSTO-211H cells are both greater than 97.6%. The chip exhibits potential for impedance flow cytometer at low cost, high-throughput, and miniaturization for the application of point-of-care diagnostics.