Parasitic Impedance Research Articles

Modeling of distributed parasitics in power FETs

A distributed circuit analysis of power FETs accounting for the lateral source parasitic impedance in addition to the lateral drain and gate parasitic impedances is presented. Both a numerical solution and an exact analytic solution are derived. Using the exact analytic solution, approximate equivalent circuits are derived for FETs of short gate width for two common types of boundary conditions. When the gate and drain terminals are located on opposite sides of the distributed FET, the lateral source parasitic impedance can be represented for short gate width FETs by an equivalent circuit with a negative series impedance in series with the source terminal. The practical consequences on parameter extraction for device modeling are discussed. The availability of an exact analytic solution for the distributed FET should also assist with the synthesis of traveling wave FETs.

Design of a 150 kV 300 A 100 Hz Blumlein coaxial pulser for long-pulse operation

Blumlein pulse generators have been used with great success for high voltage pulse generation. They are capable of producing pulses in the nanosecond or microsecond ranges depending on the transmission line length and on the topology used. The main problem with this type of generators relates to the presence of stray lines that degrade the overall gain of the device. In this paper, we are proposing a design method of a 150 kV/300 A coaxial Blumlein pulser with pulse duration of 1 /spl mu/s in which the parasitic effects are minimized by winding the transmission lines on coil formers. Also we have developed a model that estimates the pulser voltage gain from just two parameters: the number of stages and the impedance ratio of the transmission line characteristic impedance and the parasitic secondary mode impedance. The model can be applied to other types of Blumlein generators with different geometries such as those made of strip transmission lines.

Artificial-line-division distributed ICs with 0.1-μm-gate-length GaAs MESFET and three-dimensional transmission lines

0.1-/spl mu/m-gate-length GaAs MESFET distributed baseband integrated circuits (ICs) that utilize an artificial-line-division technique and three-dimensional transmission lines are described. The technique reduces return loss of the distributed circuits at high frequencies, and four-layer transmission-line structure reduces parasitic impedance caused by the IC pattern shape and is suitable for the flip-chip bonding module format. A gate-line-division distributed baseband amplifier IC achieved input return loss of less than -13 dB and gain of 11.7 dB in the 0-56 GHz band. A source-line-division distributed level-shift IC achieved output return loss of less than -9.6 dB at high frequencies and insertion loss of 2.7 dB in the 0-79 GHz band. Both results better the performance of all reported GaAs MESFET distributed ICs.

2 GHz controlled current conveyorin standard 0.8 µm BiCMOS technology

A new controlled current conveyor operating in class A and implemented using a low-cost industrial BiCMOS 0.8 µm process is described. Its electrical characteristics (voltage and current transfers, parasitic impedances) have been measured. With a bias current of 500 µA and supplied under ±2.2 V, the measurement results show that the circuit exhibits very large –3 dB bandwidths: from DC to 4.5 GHz for the voltage transfer (between Y and X) and from DC to 2 GHz for the current transfer (between X and Z).

Measurements and analyses of substrate noise waveform in mixed-signal IC environment

A transition-controllable noise source is developed in a 0.1-/spl mu/m P-substrate N-well CMOS technology. This noise source can generate substrate noises with controlled transitions in size, interstage delay and direction for experimental studies on substrate noise properties in a mixed-signal integrated circuit environment. Substrate noise measurements of 100 ps, 100-/spl mu/s resolution are performed by indirect sensing that uses the threshold voltage shift in a latch comparator and by direct probing that uses a PMOS source follower. Measured waveforms indicate that peaks reflecting logic transition frequencies have a time constant that is more than ten times larger than the switching time. Analyses with equivalent circuits confirm that charge transfer between the entire parasitic capacitance in digital circuits and an external supply through parasitic impedance to supply/return paths dominates the process, and the resultant return bounce appears as the substrate noise.

Effects of inductance on the propagation delay and repeater insertion in VLSI circuits

A closed-form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range of RLC loads. It is shown that the error in the propagation delay if inductance is neglected and the interconnect is treated as a distributed RC line can be over 35% for current on-chip interconnect. It is also shown that the traditional quadratic dependence of the propagation delay on the length of the interconnect for RC lines approaches a linear dependence as inductance effects increase. On-chip inductance is therefore expected to have a profound effect on traditional high-performance integrated circuit (IC) design methodologies. The closed-form delay model is applied to the problem of repeater insertion in RLC interconnect. Closed-form solutions are presented for inserting repeaters into RLC lines that are highly accurate with respect to numerical solutions. RC models can create errors of up to 30% in the total propagation delay of a repeater system as compared to the optimal delay if inductance is considered. The error between the RC and RLC models increases as the gate parasitic impedances decrease with technology scaling. Thus, the importance of inductance in high-performance very large scale integration (VLSI) design methodologies will increase as technologies scale.

Equivalent electrical circuit representations of AC quantized Hall resistance standards

We use equivalent electrical circuits to analyze the effects of large parasitic impedances existing in all sample probes on four-terminal-pair measurements of the ac quantized Hall resistance RH. The circuit components include the externally measurable parasitic capacitances, inductances, lead resistances, and leakage resistances of ac quantized Hall resistance standards, as well as components that represent the electrical characteristics of the quantum Hall effect device (QHE). Two kinds of electrical circuit connections to the QHE are described and considered: single-series “offset” and quadruple-series. (We eliminated other connections in earlier analyses because they did not provide the desired accuracy with all sample probe leads attached at the device.) Exact, but complicated, algebraic equations are derived for the currents and measured quantized Hall voltages for these two circuits. Only the quadruple-series connection circuit meets our desired goal of measuring RH for both ac and dc currents with a one-standard-deviation uncertainty of 10−8 RH or less during the same cool-down with all leads attached at the device. The single-series “offset” connection circuit meets our other desired goal of also measuring the longitudinal resistance Rx for both ac and dc currents during that same cool-down. We will use these predictions to apply small measurable corrections, and uncertainties of the corrections, to ac measurements of RH in order to realize an intrinsic ac quantized Hall resistance standard of 10−8 RH uncertainty or less.

RF flip-module BGA package

We recently described a flip-chip package with integrated thin-film inductors and capacitors in a VCO tank circuit of a single chip GSM transceiver integrated circuit (IC). By embedding the passive components in a Si-on-Si substrate, we eliminated spurious resonances that were caused by the parasitics of the original 64-TQFP IC package. However, compared with the bare die, the resultant Si-on-Si structure is larger in all dimensions due to the inclusion of a flip-chip mounted transceiver IC and a surface-mount varactor. We have developed a novel BGA package structure with a hole milled in the center to accommodate the silicon-on-silicon assembly. The interconnections rely exclusively on flip-chip solder technology. To verify that the package does not degrade the performance of the RF circuits, we have performed electromagnetic field simulations to extract critical inductance and capacitance parameters. Parasitic inductances of the original TQFP and the new packages are comparable due to their similar dimensions. None the less, a major advantage of the new package structure is that it permits the integration of key passive components inside the package where they are unaffected by package parasitic impedances.

Problems of Power Feeding in Large Area PECVD of Amorphous Silicon

AbstractThe production of amorphous silicon, e.g. for solar cells, requires large area, high-deposition rate plasma reactors. Increasing the radio frequency from the conventional 13.56MHz up to VHF has demonstrated higher deposition and etch rates and lower particle generation, a reduced ion bombardement and lower breakdown, process and bias voltages.But otherwise the use of VHF leads to some problems. The non-uniformity of deposition rate increase due to the generation of standing waves (TEM wave) and evanescent waveguide modes (TE waves) at the electrode surface.Increasing the frequency and/or the deposition area the plasma impedance, the capacitic stray impedance of the RF electrode and other parasitic capacitive impedances decrease. Increasing the frequency and/or the RF power, the phase angle of the discharge and of the impedance at every point at the lines between the RF matching network an the RF electrode tends more and more towards -90°. This results in increasing currents and standing waves with extremly high local current maximas. Increasing resistances of lines and contacts due to the skin effect and loss-caused heating up of the lines the power losses increase extremely, up to 90% and more. In spite of the increasing of the coupled power, the plasma power does not increase. Thermal destructions of the lines due to extreme expansion or melting are possible.Some solutions to reduce the non-uniformity of the deposition rate like multipower feeding, central backside power feeding, electrode segmentation, use of load impedances, published in former publications, will be discussed in connection with several reactor types (coaxial, large area, long plasma source) in view of the efficiency of power coupling and the practical realization. Solutions to minimize the power losses at the lines will be presented.

Analog Universal Active Device: Theory, Design and Applications

This paper introduces the concept of what we call analog Universal Active Device (UAD), as a step forward from Operational Amplifiers and other recently proposed active devices. The model for such a device is nothing but a two port classically known as Nullor. To obtain practical implementations of the UAD, or Nullor, a unified aproach is proposed. The basis of the approach is the use of a single cell consisting of a voltage and current buffer, also known as negative second-generation Current Conveyor (CCII –). We obtained the four most simple implementations for the UAD as a paradigm of more complex ones. Non ideal effects of these practical implementations are theoretically analysed, particularly parasitic impedances associated to the interconnections of the CCII – cells, and then their influence in some simple amplifier stages. It is demonstrated that while any UAD implementation can be used in a given application, its performance is strongly dependent on its implementation. Also, a novel floating structure for a General Impedance Converter (GIC) type impedance, containing two UADs, is suggested. Simulation results are given supporting the ideas presented here.

Formation of semi-insulating 6H-SiC layers by vanadium ion implantations

Vanadium ion (V+) implantation has been successfully applied to the formation of semiinsulating 6H-SiC layers. The resistivity of V+-implanted layers strongly depended on the conduction type of initial 6H-SiC crystals. The resistivity at room temperature exceeded 1012 Ω cm and 106 Ω cm for p- and n-type samples, respectively. Compensation mechanism is discussed based on the temperature dependence of resistivity. This technique will be useful for device isolation, edge termination, and reduction of parasitic impedance of SiC devices.

Magneto-dielectric anisotropy in magnetic fluids determined from magneto-optical measurements

Magneto-optical measurements on magnetic fluids have been utilized to determine the magneto-dielectric anisotropy effect in magnetic fluids. Our results show that the dielectric constant, ε| ∗ , seen by light polarized in the direction of the applied magnetic field increases with the field, while ε ⊥ ∗ seen by light polarized normal to the field decreases with the field. Moreover, the results also show that ε | ∗ exhibits a peak with temperature while ε ⊥ ∗ exhibits a minimum. Our calculated results are in good agreement with those obtained using conventional impedance measurement techniques, with the advantage that this method is not affected by the electrode effect, parasitic impedances, skin depth and accuracy-related problems that are typical of conventional impedance measurement techniques.

On the frequency limitations of the circuits based on second generation current conveyors

An equivalent circuit for the translinear implementation of the second generation current conveyors with positive or negative current transfer is given. This circuit takes into account the various parasitic elements of the conveyor which induce frequency limitations (gain values, poles of the transfers, and parasitic impedances). The methods allowing the determination of the values for these parasitic elements are indicated and discussed. The effect of each element on the frequency responses of the circuits using the conveyors are studied in every detail. The frequency behavior of two circuits are analyzed as examples: a voltage amplifier without feedback and two configurations for a second order biquad filter operating in current-mode. All the theoretical results of the analysis are well confirmed from SPICE simulations.

Parasitic impedance analysis of double bonding wires for high-frequency integrated circuit packaging

Double bonding wires separated by an internal angle have been characterized in a wide range of frequencies using the Method of Moments with the incorporation of the ohmic resistance. For a 30/spl deg/ internal angle, the calculated total reactance is more than 35% less than that of a single bonding wire due to the negative mutual coupling effect of different current directions. The radiation effect at high frequencies has been observed decreasing the mutual inductance between the angled bonding wires, whereas for parallel bonding wires it greatly increases the mutual inductance. >

Comparison of RC op.-amp. and RC current conveyor filters

Abstract Voltage mode filters implemented using (non-ideal) current conveyors are compared with the corresponding filters implemented using (non-ideal0 op.-amp. and current conveyor niters are found to perform similarly although the parasitic impedances of the non-ideal current conveyor sometimes complicate the design of current conveyor filters.

A transimpedance converter for low-frequency, high-impedance measurements

A straightforward but unique current to voltage converter is described which, in conjunction with a standard frequency response analyser (FRA), allows impedance measurements to be performed. The circuit topology minimizes the effects of parasitic impedance components enabling the quantitative measurements of high-impedance elements into the gigohm region-a feature not found on standard impedance bridges. This capability has application in areas such as measurements on ion selective electrodes. The combined facility provides a generally useful impedance analyser. However, its immediate utility was in the study of low-frequency electrode-electrolyte systems, to which the data presented relate. The circuit provides accuracy and stability, and is inexpensive to construct from readily available components.

Effect of capacitative imbalance on common-mode rejection of balanced photodetector pairs

The Letter shows that the common-mode rejection ratio of balanced photodetector pairs, as used for coherent lightwave reception, is insensitive to capacitance differences between the detectors in the absence of parasitic series impedance. These results indicate that balanced performance can be achieved in high-speed detector pairs, even when a capacitance imbalance occurs. The effect of detector series resistance or inductance on common mode rejection is quantitatively analysed.

Electrical characterization of radio-frequency discharges in the Gaseous Electronics Conference Reference Cell

Measurements of the electrical characteristics of radio-frequency (rf) discharges can be subject to large errors due to limitations in the measurement instruments and the stray impedance of the discharge cell. This study reports electrical measurements of argon discharges in the GEC Reference Cell in which special care has been taken to identify and minimize these sources of error. Careful calibration of current and voltage probes was found to be essential. In addition, parasitic impedances in the cell were found to be large, sensitive to minor changes in electrical connections, and not adequately described by simple a priori models. A general technique for characterizing the stray impedance, including an analysis of the propagation of errors, is presented here. This technique assures accurate results with specified uncertainties. Error analysis demonstrated that large gains in the precision of the measurements can be obtained using an inductive shunt circuit. Together, these techniques should improve the utility of electrical measurements for gauging the reproducibility of plasma conditions among rf discharge cells, for testing theoretical results, and for monitoring plasma processing.

Load-adaptive frequency tracking control implementation of two-phase resonant inverter for ultrasonic motor

The basic driving and control principles and the operating characteristics of a newly-developed ultrasonic motor (USM) are described. The two-phase resonant inverter for driving the USM, which includes a variable-frequency PWM (pulse width modulation) control scheme and a phasor control function between inverters, is discussed. A novel automatic resonant frequency tracking strategy using the PLL (phase-locked loop) technique is presented. It uses both sensor and sensorless interfaces to operate at a certain optimum point. The two-phase high-frequency inverter using parasitic resonant impedances incorporated in the ultrasonic motor, which is represented in terms of an electrical resonant tank circuit model, is proposed as a high-power density switching mode ultrasonic power amplifier. Experimental results obtained with this inverter-drive USM system with frequency timing control are illustrated. >

Mechanical cooler-to-Dewar interfacing in a long-lifetime, hybrid stored cryogen system

The cryogenic subsystem for the Advanced X-Ray Astrophysics Facility (AXAF) X-Ray Spectrometer (XRS) represents a new breed of long-lifetime, hybrid stored cryogen system. The design achieves a predicted lifetime of 5 years with only 480 I of superfluid helium by using mechanical coolers to limit the parasitic heating into the Dewar. The system uses two momentum-compensated pairs of split, Stirling-cycle coolers to cool the Dewar outer vapour-cooled shield. Use of the 80 K coolers can reduce the helium loss rate by about a factor of 3. This paper primarily addressed the means for making efficient use of the coolers. Thermal efficiency is achieved by minimizing the parasitic heating and thermal impedance of the cooler-to-Dewar interface within the mechanical constraints. The important issues related to compatibility with the instrument system are also briefly discussed. Parasitic heating from the non-operating (reserved or failed) cooler pair can be reduced with an active thermal switch that isolates the cooler cold tips from the cold finger. Analysis was performed to determine optimal switch operating characteristics for this application. Requirements associated with use of the coolers, analyses performed and the interface design concept are discussed. Component development is continuing.