Paralleled SiC MOSFETs Research Articles

A Dynamic Current Balancing Method for Paralleled SiC MOSFETs With Gate-Branch Full-Coupled Inductors

A Dynamic Current Balancing Method for Paralleled SiC MOSFETs With Gate-Branch Full-Coupled Inductors

A Dynamic Current Sharing Model of Multichip Parallel SiC MOSFETs Considering Layout-Dominated Mutual Inductance Coupling

A Dynamic Current Sharing Model of Multichip Parallel SiC MOSFETs Considering Layout-Dominated Mutual Inductance Coupling

Analysis of Electrothermal Imbalance of Hard-Switched Parallel SiC MOSFETs through Infrared Thermography

This paper provides an experimental investigation through infrared thermography of the steady-state temperature imbalance arising in parallel SiC MOSFETs. A switched-mode boost power converter based on two arrays of 4 parallel 1.2 kV MOSFETs is selected as a case-study. The analysis aims at proving that a proper device arrangement can minimize the thermal imbalance in the absence of circuit layout optimization.

Dynamic Current Balancing for Paralleled SiC MOSFETs With Circuit Mismatches Considering Circulating Current in Drive Circuit

Dynamic Current Balancing for Paralleled SiC MOSFETs With Circuit Mismatches Considering Circulating Current in Drive Circuit

Digital Close-Loop Active Gate Driver for Static and Dynamic Current Sharing of Paralleled SiC MOSFETs

SiC power devices have been extensively for the high-power density application scenarios. To increase the current rating, SiC devices are usually connected in parallel. However, the mismatching current brought by unbalanced electrical parameters can increase the current stress of a device and pose reliability concern of the converter system. Aiming at addressing the current imbalance for paralleled SiC devices, this paper reports the application of an improved active gate driver (AGD) on the paralleled SiC MOSFETs to address the current imbalance problems. The three-level driver voltage can minimize the overshoot voltage and current. The adjustable turn-on voltage and gate signal delay time can realize the current sharing of both static and dynamic process. Current sensors and a digital controller are utilized for close-loop control. The functionality of the proposed AGD is validated in continuous operating experiment.

Mitigating Gate Oscillations of Parallel SiC MOSFETs for Enhanced Performance in DC Solid-State Circuit Breaker

Mitigating Gate Oscillations of Parallel SiC MOSFETs for Enhanced Performance in DC Solid-State Circuit Breaker

Design of Half-Bridge Switching Power Module Based on Parallel-Connected SiC MOSFETs for LLC Resonant Converter with Symmetrical Structure and Low Parasitic Inductance

SiC MOSFETs are used in many power conversion applications because of their superior characteristics, such as fast switching speed, low on-resistance, and high operating temperature. In certain high-power systems, SiC MOSFETs are connected in parallel to enhance their current capacity and power efficiency. However, compared with Si-based devices, the current imbalance caused by the parasitic inductance difference becomes more severe when driving SiC MOSFETs in parallel, owing to the fast switching speed. Furthermore, the power loop inductance imbalance that occurs when constructing a half-bridge with parallel SiC MOSFETs has rarely been addressed in previous studies. In this study, a half-bridge switching power module based on parallel-connected SiC MOSFETs is proposed to solve the current imbalance through a symmetric structure of the gate and power loops. The effects of the magnitude and imbalance of the gate and power loop inductances in the half-bridge structure based on parallel-connected devices are also explained. A detailed printed circuit board layout of the proposed switching power module is provided, and the inductance symmetry is verified through simulations. A double-pulse test is conducted to verify the current-balancing capability of the proposed switching power module. In addition, an LLC resonant converter is designed using the proposed switching power module, and the power loss between parallel SiC MOSFETs is compared. The experimental results indicate the total power loss error between the parallel-connected SiC MOSFETs of the proposed power module is only 1.94%.

Surge Current Distribution in Paralleled SiC MOSFETs under Third-quadrant Operation

Surge Current Distribution in Paralleled SiC MOSFETs under Third-quadrant Operation

Parallel SiC MOSFETs Marx Pulse Generator Based on Magnetic Induction Current Balance

Parallel SiC MOSFETs Marx Pulse Generator Based on Magnetic Induction Current Balance

A Negative-Feedback Gate-Loop for Current Balancing Paralleled SiC MOSFETs Based on a Differential Mode Inductor

A Negative-Feedback Gate-Loop for Current Balancing Paralleled SiC MOSFETs Based on a Differential Mode Inductor

A Current Balancing Gate Driver for Dynamic Current Sharing of Paralleled SiC MOSFETs with Kelvin-Source Connection

A Current Balancing Gate Driver for Dynamic Current Sharing of Paralleled SiC MOSFETs with Kelvin-Source Connection

Comprehensive Analysis of Paralleled SiC MOSFETs Current Imbalance Under Asynchronous Gate Signals

Comprehensive Analysis of Paralleled SiC MOSFETs Current Imbalance Under Asynchronous Gate Signals

Output Curves Based Hierarchical Clustering Screening Method With Static/Dynamic Current Balancing for Paralleled SiC MOSFETs

Output Curves Based Hierarchical Clustering Screening Method With Static/Dynamic Current Balancing for Paralleled SiC MOSFETs

A Dynamic Current Balancing Method for Paralleled SiC MOSFETs Using Monolithic Si-RC Snubber Based on a Dynamic Current Sharing Model

The dynamic current imbalance between paralleled SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s will cause unbalanced losses and reduce current capacity. The existing current balancing methods will make the circuit more complex or hard to design and implement. Hence, this article proposes a dynamic current balancing method by connecting monolithic Si- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> snubber between paralleled <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s, which maintains a simple circuit structure and is easy to implement. Balanced dynamic currents can be achieved by adjusting the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> snubber connecting location. Meanwhile, low voltage spike and low switching oscillation can be achieved by using <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> snubber. First, an analytical current sharing model is established for paralleled SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s. The key parameter affecting the balance of the drive circuit and then affecting the dynamic current sharing is obtained for the first time. Based on the conclusions of the model, this article then presents the current balancing method using <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> snubber. Then, a power module with monolithic Si- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> snubber is designed, fabricated, and tested. Experimental results verify the current sharing model and the current balancing method. The current difference of the optimized module is reduced by more than 50% under different conditions. Finally, the effectiveness of this method in the module with more paralleled <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s is verified.

Influence of parasitic coupling on current sharing in paralleled SiC MOSFET devices

This paper comprehensively investigates the current distribution behaviours of paralleled SiC MOSFET devices under the parasitic coupling between gate and power loops. Three types of connection that are commonly adopted in actual applications, comprising common source connection (CSC), Kelvin source connection (KSC) and hybrid source connection (HSC), are thoroughly discussed. The influence mechanism of mismatch in values for three parasitic inductances on current sharing during different switching periods is studied in theory. Simulations and experiments are also carried out and results are used to validate the theoretical analysis. Parasitic capacitance, common source and quasi common source parasitic inductance couplings are the three main coupling modes between gate loop and power loop in a circuit with paralleled SiC MOSFETs. The current imbalance is mainly due to the variation of gate-source voltage generated by the mismatch in the parasitic inductances through the three coupling paths. This paper aims to provide an insight into current sharing mechanism of paralleled devices with circuit parasitic mismatches. Influence of every parasitic inductance under each of the three coupling modes is investigated and recommendation made on choice of coupling mode and viable switching speed and current balance tradeoff that can be adopted in a practical system design.

Effect of common branch impedance coupling and mutual inductance on current sharing of paralleled SiC MOSFETs with different layouts

Overcurrent failure caused by imbalanced current distribution is one of the universal failure forms of the SiC MOSFET module. The current sharing of parallel SiC MOSFETs is an important guarantee for the safe and reliable operation of parallel devices even the whole system. The existence of current coupling has a significant influence on the current sharing among paralleled SiC MOSFETs. Here, the mechanism of dynamic and static current imbalance under the different layouts resulting from current coupling generated by common branch impedance coupling and mutual inductance is comprehensively investigated by theoretical analysis and simulation validations. It is concluded that dynamic current imbalance is more serious when the drain confluence point and power source confluence point are on both sides than they are on the one side. While, the influence of the arrangement of two confluence points on the static current distribution is in reverse. Finally, a flexible and adjustable test bench is designed to verify the current sharing performance on the different layouts. The experimental results validate the correctness of the theoretical analysis. Based on these results, some guidelines are provided for the parallel-connected application of SiC MOSFETs.

A passive compensator for imbalances in current sharing of parallel‐siC MOSFETs based on planar transformer

SiCMOSFETs are widely employed in power converters due to their high switching speed and low switching loss. However, their low current rating due to the limited active area restricts their high power applications. To apply SiC MOSFETs in high power applications, providing parallel connection is an inevitable choice. To tackle the challenge of imbalanced current sharing problem between parallel SiC MOSFETs, a new passive compensator based on planar transformer (PT) is proposed here. Compared with the conventional transformer compensators, parasitic elements are adjustable and predictable in PT compensators, which is especially important for mass production aims. After explaining the concept of the physical operation of the PT compensator, the whole parasitic elements of the PT compensator are formulated. Based on estimated parasitic elements and using the finite element method (FEM), an optimum PT structure is extracted for imbalances in current sharing of parallel SiC MOSFETs. Afterward, the PT design is discussed in detail and then, a boost converter is constructed. Finally, the experimental results are presented to verify the reliability, accuracy, and effectiveness of the theoretical results.

A Method to Balance Dynamic Current of Paralleled SiC MOSFETs With Kelvin Connection Based on Response Surface Model and Nonlinear Optimization

Multichip SiC power modules with Kelvin-source connection are popular in applications with large capacity and high switching frequency. However, dynamic current imbalance among paralleled dies due to asymmetric layout limits the available capacity. Thus, this article proposes a method to mitigate the mismatched dynamic current by adjusting the connection points of bonding wires and copper traces. The response surface models and nonlinear constrained optimization algorithms are introduced for the first time to help determine the optimized positions for the connection points. By this method, the dynamic current imbalance can be well suppressed under various working conditions. Besides, the method is cost-efficient and well compatible with the conventional manufacturing technologies because there need no additional efforts but some modifications on bonding wires. At first, the optimization guidelines are obtained after analyzing the mechanism of dynamic current imbalance among paralleled SiC MOSFETs with Kelvin-source connection. Based on the optimization guidelines and response surface models of parasitic inductance, the dynamic current sharing problem can be transformed into a nonlinear constrained optimization issue in mathematics. According to the solution of the mathematic problem, the optimized positions for connection points of bonding wires and copper traces can be determined. Finally, some simulations and experiments are conducted to verify the effectiveness of the proposed method.

A Comprehensive Analysis for High-Power Density, High-Efficiency 60 kW Interleaved Boost Converter Design for Electrified Powertrains

High-power boost converters offer significant benefits to hybrid and electric vehicles, because higher-voltage propulsion power equates to lower motor losses. However, the converters themselves must have high efficiency and high power density in order to make the system-level trade-off beneficial. Thus, this paper presents an optimized design process of high power multi-phase interleaved bidirectional boost converters. In order to achieve a fast and accurate analysis and design, a generalized method is developed for the calculations of required phase inductance and output capacitance. In addition, a genetic algorithm (GA) optimization method is implemented for the inductor design. Using the proposed design process, a 3-phase 60 kW interleaved converter is designed and tested using paralleled SiC MOSFETS. The converter achieves peak efficiency of 99.2% at 10 kW and is >98% efficiency from 5% to 100% load. The resulting power density is 9.4 kW/L, which can be further improved to 12.2 kW/L with alternate terminal connectors.

Gate driver for parallel connection SiC MOSFETs with over-current protection and dynamic current balancing scheme

In this paper, a SiC MOSFETs gate driver for parallel connections is proposed and implemented. The proposed design enhances the reliability of parallel-connected SiC MOSFETs in high-frequency applications. High-speed over-current protections are applied for both over-voltage and under-voltage situations. In addition, a dynamic balancing current sharing scheme for SiC MOSFETs is proposed for high-speed parallel applications by current feedback and switching delay time compensation. With the proposed design, parallel-connected SiC MOSFETs can work at an operation frequency of 1 MHz with over-current protections. In addition, with the dynamic current balancing scheme, the operation temperature decreases from 115 to 86.9 °C, while the temperature difference for paralleled devices drops from 25.8 to 1.8 °C.