Parallel Update Research Articles

Synchronous and asynchronous updates of active Ising spins in one dimension

How do update rules affect the dynamical and steady state properties of a flock? In this study, we have explored the active Ising spins (s=±1) in one dimension, where spin updates its orientation according to the Metropolis algorithm (based on the neighbours) via two different update rules. (i) Parallel, and (ii) Random-sequential. We explore the effect of Parallel and Random-sequential updates on the dynamical properties of flocks in one dimension. Due to the inherent asynchronous nature of the Random-sequential update, the directional switching of the flock is increased compared to the Parallel one. The nature of phase transition is affected by the difference in the updating mechanism: discontinuous for Parallel and continuous for Random-sequential updates.

Dimensional tolerance optimization of SAR antennas with uncertainty quantification and reliability analysis based on structural-electromagnetic coupling model

The dimensional tolerances greatly impact the structural-electromagnetic performance of spaceborne synthetic aperture radar (SAR) antenna. However, few works have conducted the tolerance allocation of the extendible support structure to guarantee system reliability. To bridge the above gap, an integrated optimization methodology is proposed to design the dimensional tolerances with the structural-electromagnetic coupling model in this study. First, the absolute nodal coordinate formulation is developed to predict the structural deformation triggered by the dimensional deviations. Then, the coupling relationship between the displacement field and the electromagnetic field is elucidated for the SAR system. Subsequently, taking advantage of the surrogate model and the parallel update criterion, the interval uncertainty quantification stemming from dimensional tolerances is executed to quickly identify the worst-case scenarios of structural response. Moreover, a multi-point selection strategy is incorporated into the adaptive Bayesian probabilistic integration with active learning, which significantly improves the computational efficiency of electromagnetic reliability. Based on the above tolerance analysis, the inverse optimization design of the dimensional tolerance is realized by the particle swarm algorithm. Finally, the effectiveness and superiority of the proposed methods are validated in the case study. Our innovative framework and analytical methodology not only furnish a comprehensive structural-electromagnetic coupling model but also transition the design paradigm from experiential to robust tolerance allocation.

RGMU: A High-flexibility and Low-cost Reconfigurable Galois Field Multiplication Unit Design Approach for CGRCA

Finite field multiplication is a non-linear transformation operator that appears in the majority of symmetric cryptographic algorithms. Numerous specified finite field multiplication units have been proposed as a fundamental module in the coarse-grained reconfigurable cipher logic array to support more cryptographic algorithms; however, it will introduce low flexibility and high overhead, resulting in reduced performance of the coarse-grained reconfigurable cipher logic array. In this article, a high-flexibility and low-cost reconfigurable Galois field multiplication unit (RGMU) is proposed to balance the tradeoffs between the function, delay, and area. All the finite field multiplication operations, including maximum distance separable matrix multiplication, parallel update of Fibonacci linear feedback shift register, parallel update of Galois linear feedback shift register, and composite field multiplication, are analyzed and two basic operation components are abstracted. Further, a reconfigurable finite field multiplication computational model is established to demonstrate the efficacy of reconfigurable units and guide the design of RGMU with high performance. Finally, the overall architecture of RGMU and two multiplication circuits are introduced. Experimental results show that the RGMU can not only reduce the hardware overhead and power consumption but also has the unique advantage of satisfying all the finite field multiplication operations in symmetric cryptography algorithms.

Customized FPGA Implementation of Authenticated Lightweight Cipher Fountain for IoT Systems

Authenticated Encryption with Associated-Data (AEAD) can ensure both confidentiality and integrity of information in encrypted communication. Distinctive variants are customized from AEAD to satisfy various requirements. In this paper, we take a 128-bit lightweight AEAD stream cipher Fountain as an example. We provide a general cryptographic solution with three Fountain variants. These three variants are for encryption, message authentication code (MAC) generation, and authenticated encryption with associated data, respectively. Besides, we propose area-saved and throughput-improved strategies for the FPGA implementation of Fountain. The conventional paralleled hardware implementation leads to much resource-consuming with higher parallel width. We propose a hybrid architecture with parallel and serial update modes simultaneously. We also analyze the trade-off between area occupation and authentication latency for those two architectures. According to our discussion, hybrid architectures can perform efficiently with higher throughput than most ciphers, including Grain-128 x32. Our Fountain keystream generator occupies 46 slices on Spartan-3 FPGAs, smaller than most ciphers with the same security level, and even smaller than the 80-bit security level cipher Trivium. In summary, the customized Fountain with optimized implementations on FPGA is suitable for various applications in the field of IoT.

Administrative Procedure in the Field of Public Health

The relevance of the proposed study is due to the parallel significant update of medical legislation and the entry into force of the Law of Ukraine "On Administrative Procedure". The purpose of the proposed research is to assess the quality of legal regulation of certain administrative proceedings in the field of public health, which has undergone significant changes in the last months of 2023. The results of the study, on the one hand, will help to identify shortcomings and legal conflicts that have formed, and on the other hand, to develop and suggest ways to overcome some of them. The research methodology consists of the following methods of scientific cognition: dialectical, theoretical-prognostic, comparative-legal, system-structural, formal-logical, analysis, legal modeling, and others. In the course of the work, the importance of proper legal regulation and effective public administration in the field of public health is emphasized. The place of administrative bodies in the system has been establishedsubjects of relations in the field of public health. A classification of measures used by specialized administrative bodies in their activities has been proposed. The significance of administrative proceedings and administrative acts used in the process of public administration of public health is disclosed and the most significant among them are highlighted: control and supervision, on the application of termination measures, registration. The essence of each of these proceedings has been investigated and the shortcomings of their regulation have been identified, due to the inconsistency of the norms of the Laws of Ukraine "On the Public Health System" and "On the Administrative Procedure". Significant shortcomings in the legal regulation of administrative proceedings on the application of temporary measures to stop violations of the requirements of sanitary legislation are noted and possible problems in its application are indicated. Attention is also focused on the shortcomings of the terminology used in the Law "On the Public Health System". The results of the study can contribute to the improvement of legislation in the field of public health, as well as to improve the quality of formation law enforcement practice of administrative bodies that are subjects of the public health system.

An Efficient Data Structure for Dynamic Graph on GPUs

There is a growing interest to offload dynamic graph computation to GPU and resort to its high parallel processing ability and larger memory bandwidths compared with CPUs. The existing GPU graph systems usually use compressed sparse row (CSR) as the de-facto structure. However, CSR has a critical weakness for dynamic change due to the large overhead of re-balance process after update. GPMA+ is a state-of-art dynamic PMA-based structure that uses PMA structure and segment-oriented parallel update procedure to address the dynamic weakness of CSR, but it still has a bottleneck on the array expansion. In this paper, we propose an leveled structure (called LPMA) instead of continue array to retain low time complexity and high parallel update and lift the expansion bottleneck of GPMA+. More specifically, we propose a series of optimization techniques, including bottom-up update, top-down update and on-demand hybrid update strategies as well as consistence-guaranteed parallel processing for update-query mixed workloads. We theoretically analyze the benefits of LPMA compared in terms of re-balance cost during updates. Extensive experiments on four large real-life graphs prove the superiority of LPMA compared with the-state-of-arts.

Accurate Weight Update in an Electrochemical Random‐Access Memory Based Cross‐Point Array Using Channel‐High Half‐Bias Scheme for Deep Learning Accelerator

AbstractRecently cross‐point arrays of synaptic memory devices have been intensively studied to accelerate deep neural network computations. Among various synaptic devices, electrochemical random‐access memory (ECRAM) is emerging as a promising non‐volatile memory candidate owing to its superior synaptic characteristics. However, an optimized update scheme for a three‐terminal ECRAM‐based cross‐point array is yet to be developed. In this study, a metal‐oxide‐based ECRAM (MO‐ECRAM) shows superior synaptic characteristics and the weight update of devices in the MO‐ECRAM cross‐point array is analyzed using the half‐bias (HB) scheme. Additionally, A channel‐high half‐bias (CHB) scheme is proposed to overcome the degraded selectivity of the weight update caused by the three‐terminal configuration of the ECRAM device. In the CHB scheme, the conductance change in the selected device can be increased considerably by applying a calculated additional voltage to the channel. Using the CHB scheme, parallel and selective updates are successfully performed in a 2 × 2 MO‐ECRAM cross‐point array. Finally, an experimental demonstration of the training algorithm shows the impact of selective updates when using the CHB scheme. This new update scheme is expected to improve training accuracy in ECRAM cross‐point array‐based deep learning accelerators.

An Ising Model-Based Annealing Processor With 1024 Fully Connected Spins for Combinatorial Optimization Problems

This brief presents a novel annealing processor (AP) design with 1024 fully-connected spins based on a modified Ising model annealing algorithm for combinatorial optimization problems. By adopting the proposed Turbo code-based interleaved random sequence generator (TCSG) and multi-spin update method, the memory usage is made considerable reduction and multi-spin parallel update is supported. The prototype is implemented using FPGA with the operation frequency of 100 MHz. We tested our design on various G-set problems with an average cut accuracy of 99.19% achieved. The proposed design outperforms the CPU-based method by achieving a max speedup of 1099×.

A Network-on-Chip-Based Annealing Processing Architecture for Large-Scale Fully Connected Ising Model

Combinatorial optimization problems are prevalent in many different fields. Most of these problems are NP-hard and challenging for computers with conventional Von-Neumann architecture. Ising machines with a number of spins have the potential to solve these problems by emulating the natural annealing process of solid matter. Recent research has explored some hardware implementation methods of Ising machines to accelerate the convergence process of such problems at room temperature. However, most of them are suffering from low scalability and low parallel processing capability due to the huge hardware cost and high complexity. In this paper, a novel network-on-chip-based annealing processing architecture (NoCAPA) for a large-scale Ising processor is described to address these issues with a NoC computing paradigm, a distributed storage scheme, and a fully pipelined structure design. Several techniques are developed to further increase convergence speed and reduce hardware resource consumption, including a dynamic multithread parallel update algorithm, a router with merge and deflection abilities, and a unique multiply-accumulate operation. The prototype is implemented in FPGA with the maximum operation frequency of 200MHz, achieving up to 120.5 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> faster than conventional simulated annealing method when solving the max-cut problem while supporting high scalability.

Efficient Training Method for Memristor-Based Array Using 1T1M Synapse

In this brief, an efficient training method for memristor-based array (crossbar) with one transistor and one memristor (1T1M) synapse is proposed, which enables parallel update of memristor-based arrays trained by stochastic gradient descent within two steps. Voltage ThrEshold Adaptive Memristor (VTEAM) model is utilized to describe memristor characteristics for simulations. On this basis, circuit parameters optimization method compensating the asymmetric and nonlinear weight update is provided for better training results. The effectiveness of proposed training method is evaluated on OR, AND functions and digit recognition task. Simulation results demonstrate the robustness of proposed training method to electrical noise and imperfections of memristors.

MRVs: Enforcing Numeric Invariants in Parallel Updates to Hotspots with Randomized Splitting

Performance of transactional systems is degraded by update hotspots as conflicts lead to waiting and wasted work. This is particularly challenging in emerging large-scale database systems, as latency increases the probability of conflicts, state-of-the-art lock-based mitigations are not available, and most alternatives provide only weak consistency and cannot enforce lower bound invariants. We address this challenge with Multi-Record Values (MRVs), a technique that can be layered on existing database systems and that uses randomization to split and access numeric values in multiple records such that the probability of conflict can be made arbitrarily small. The only coordination needed is the underlying transactional system, meaning it retains existing isolation guarantees. The proposal is tested on five different systems ranging from DBx1000 (scale-up) to MySQL GR and a cloud-native NewSQL system (scale-out). The experiments explore design and configuration trade-offs and, with the TPC-C and STAMP Vacation benchmarks, demonstrate improved throughput and reduced abort rates when compared to alternatives.

Coalition Formation Game for Cost-Efficient Multiparty Payment Channel in Payment Channel Networks.

Blockchain has introduced a new era for online payment services and its economy with tamper-proof cryptocurrencies. However, blockchain, which is based on global peer-to-peer networks, has its limitations due to payment delays from global consensus and transaction costs for maintenance. Thus, payment channel networks (PCN) have been proposed as one of the most promising off-chain solutions, allowing users to pay directly through payment channels (PC), with minimal blockchain involvement. However, payment delays and cost problems still exist, especially given the large size of the PCN. This study proposes a multiparty payment channel (MPC) that enables multiple users to join the same PC and exchange payment transactions, compared to the legacy PC. To avoid a consensus procedure among users in the PC, we introduce sequential and parallel updates for the PC status. Since increasing the MPC size limits the advantages in terms of the delay and cost, we propose a distributed coalition formation algorithm to form the MPC group, in which each user has the choice to join or leave the group. Simulations show that the proposed algorithm establishes MPCs successfully, considering the trade-off between the payoff gain and the MPC delay cost.

FAST: A Fully-Concurrent Access SRAM Topology for High Row-Wise Parallelism Applications Based on Dynamic Shift Operations

Compute-in-memory (CiM) is a promising approach to improving the computing speed and energy efficiency in dataintensive applications. Beyond existing CiM techniques of bitwise logic-in-memory operations and dot product operations, this paper extends the CiM paradigm with FAST, a new shift-based inmemory computation technique to handle high-concurrency operations on multiple rows in an SRAM. Such high-concurrency operations are widely seen in both conventional applications (e.g. the table update in a database), and emerging applications (e.g. the parallel weight update in neural network accelerators), in which low latency and low energy consumption are critical. The proposed shift-based CiM architecture is enabled by integrating the shifter function into each SRAM cell, and by creating a datapath that exploits the high-parallelism of shifting operations in multiple rows in the array. A 128-row 16-column shiftable SRAM in 65nm CMOS is designed to evaluate the proposed architecture. Postlayout SPICE simulations show average improvements of 4.4x energy efficiency and 96.0x speed over a conventional fully-digital memory-computing-separated scheme, when performing the 8-bit weight update task in a VGG-7 framework.

Smoothed particle hydrodynamics method for free surface flow based on MPI parallel computing

In the field of computational fluid dynamics (CFD), smoothed particle hydrodynamics (SPH) is very suitable for simulating problems with large deformation, free surface flow and other types of flow scenarios. However, traditional smoothed particle hydrodynamics methods suffer from the problem of high computation complexity, which constrains their application in scenarios with accuracy requirements. DualSPHysics is an excellent smoothed particle hydrodynamics software proposed in academia. Based on this tool, this paper presents a largescale parallel smoothed particle hydrodynamics framework: parallelDualSPHysics, which can solve the simulation of large-scale free surface flow. First, an efficient domain decomposition algorithm is proposed. And the data structure of DualSPHysics in a parallel framework is reshaped. Secondly, we proposed a strategy of overlapping computation and communication to the parallel particle interaction and particle update module, which greatly improves the parallel efficiency of the smoothed particle hydrodynamics method. Finally, we also added the pre-processing and post-processing modules to enable parallelDualSPHysics to run in modern high performance computers. In addition, a thorough evaluation shows that the 3 to 120 million particles tested can still maintain more than 90% computing efficiency, which demonstrates that the parallel strategy can achieve superior parallel efficiency.

Practical reusable garbled circuits with parallel updates

The central contribution of the current paper is to establish a practical and effective reusable garbled circuit scheme with parallel updates, where each update is applied to the circuit in parallel. First of all, we present a strengthened notion of inner product functional encryption (IPE) called simulation-based security (SIM-security) for multi-instance and show that a secret-key IPE scheme is multi-instance SIM-secure. Then we put forward a reusable garbled circuit scheme based on the IPE scheme. The idea is a reduction from re-randomizable garbled circuits in which the distribution of the original garbled circuit is computationally indistinguishable from the re-randomized garbled circuit. Finally, we implemented reusable garbled circuits and validate the practicality of our reusable garbled circuit scheme. Experimental results demonstrate that our reusable garbled circuit scheme is suitable for a wide range of real-world scenarios.

Modelling of transport processes: Theory and simulations

The transport processes, being a non-equilibrium system, have been a point of interest for physicists since many years revealing and explaining several unexpected effects. Such systems are often dealt with an archetypal model, known as totally asymmetric simple exclusion process, with two different types of boundary conditions: open and periodic. Moreover, these models are analyzed in two varieties of dynamics, random sequential and parallel updates, even at the micro level which play an important role in the global dynamics of the system. On contrary to the random sequential rule, the parallel updates introduce correlations in the system. Using theoretical and numerical methods in the framework based on mean-field approaches, the system properties are analyzed in both transient and steady state.•Both the updating rules are realized using Monte Carlo simulations.•In simplest form, mean-field approach ignores all the correlations and the results coincide with the random sequential update.•Correlations are induced in the system due to parallel update, therefore, a cluster mean-field theory is also discussed to handle them.

Analysis of electro-chemical RAM synaptic array for energy-efficient weight update

While electro-chemical RAM (ECRAM)-based cross-point synaptic arrays are considered to be promising candidates for energy-efficient neural network computational hardware, array-level analyses to achieve energy-efficient update operations have not yet been performed. In this work, we fabricated CuOx/HfOx/WOx ECRAM arrays and demonstrated linear and symmetrical weight update capabilities in both fully parallel and sequential update operations. Based on the experimental measurements, we showed that the source-drain leakage current (ISD) through the unselected ECRAM cells and resultant energy consumption—which had been neglected thus far—contributed a large portion to the total update energy. We showed that both device engineering to reduce ISD and the selection of an update scheme—for example, column-by-column—that avoided ISD intervention via unselected cells were key to enable energy-efficient neuromorphic computing.

Analytical investigation on totally asymmetric simple exclusion process with Langmuir kinetics and a parallel update with two sub-steps

Motivated by the fact that parallel update rules need to be employed to study the traffic dynamic of vehicles and pedestrians with bulk on-off ramps. This paper studies the totally asymmetric simple exclusion process (TASEP) with Langmuir kinetics and a parallel update with two sub-steps. Moreover, this new model can be analyzed analytically. Based on the mean-field method, the phase diagrams are obtained and the influences of model parameters are investigated. Compared to the system under the random update, there do not exist the phases related to the maximum current phase and Meissner phase in the system under the parallel update.

TASEP and generalizations: method for exact solution

The explicit biorthogonalization method, developed in [arXiv:1701.00018] for continuous time TASEP, is generalized to a broad class of determinantal measures which describe the evolution of several interacting particle systems in the KPZ universality class. The method is applied to sequential and parallel update versions of each of the four variants of discrete time TASEP (with Bernoulli and geometric jumps, and with block and push dynamics) which have determinantal transition probabilities; to continuous time PushASEP; and to a version of TASEP with generalized update. In all cases, multipoint distribution functions are expressed in terms of a Fredholm determinant with an explicit kernel involving hitting times of certain random walks to a curve defined by the initial data of the system. The method is further applied to systems of interacting caterpillars, an extension of the discrete time TASEP models which generalizes sequential and parallel updates.

Low-Complexity Resource-Shareable Parallel Generalized Integrated Interleaved Encoder

Generalized integrated interleaved (GII) codes nest a set of linear block codewords to generate codewords belonging to stronger codes. They are among the best error-correcting codes for next-generation hyper-speed digital communications and storage. Serial encoders for GII codes based on BCH codes have been previous investigated. They consist of BCH encoders whose inputs and outputs are multiplied by vectors decided by the nesting scheme. However, parallel GII encoders for high-speed systems cannot be designed by directly extending serial encoders due to the unique feature that BCH codes of different error-correcting capabilities are involved. Moreover, GII decoder complexity and latency can be greatly reduced by sharing the encoder to compute short remainders for syndrome computation. Although previous resource-shareable BCH encoders can be utilized to implement resource-shareable GII encoders, they are all serial. This paper first proposes a low-complexity scheme to handle the different error-correcting capabilities of the involved codes and align the input and parity symbols for parallel processing. Then two efficient parallel resource-shareable BCH encoder architectures to be used as GII encoder components are developed. The first design is achieved by deriving parallel register state update formulas for concatenated linear-feedback shift registers (LFSRs). Through reformulating the remainder polynomial divisions, the second design allows the inputs to be added to different LFSR taps, and accordingly reduces the complexity by a significant portion. For an example 160-parallel GII-BCH encoder considered for Flash memory applications, the second proposed design requires 14% smaller area compared to the first one. Besides both of them lead to around 50% latency reduction in the nested syndrome computation with small area overheads compared to the best possible alternative design.