Parallel Turbo Decoder Research Articles

Design of high‐speed data transfer turbo code for body channel communication transceivers

SummaryIn this work, a digital differential transmitter based on low‐power wireless compensation transceiver for body channel communication (BCC) is proposed. Further, the proposed transceiver is composed of Touch Status Detection Unit (TSDU), Wireless Status Compensation Unit (WSCU), and a reconfigurable preamplifier. Initially, the human body channel environment for wireless communication is investigated based on properties from 1 to 100 MHz. Further, the turbo code‐based encoding scheme is used to encode the data before transferring the data on the transmitter side. Also, the proposed error‐correcting parallel turbo decoder using a modified step‐by‐step algorithm is presented. The turbo code‐based decoding scheme is used to recover the error‐free transmitted data at the receiver side. Results demonstrate that the proposed BCC transceiver is designed using 90 nm CMOS technology and it is observed that the proposed BCC transceiver has utilized an area of 600mm2. Also, the maximum data rate achieved by a proposed BCC transceiver was 100 Mbps, and the overall transceiver power consumption is 0.42 mW, and energy for communication is 0.02 nj/b.

A Parallel Turbo Decoder Based on Recurrent Neural Network

A neural network-based decoder, based on a long short-term memory (LSTM) network, is proposed to solve the problem that large decoding delay and performance degradation under non-Gaussian noise due to poor parallelism of existing turbo decoding algorithms. The proposed decoder refers to a unique component coding concept of turbo codes. First, each component decoder is designed based on an LSTM network. Next, each layer of the component decoder is trained, and the trained weights are loaded into the turbo code decoding neural network as initialization parameters. Then, the turbo code decoding network is trained end-to-end. Finally, a complete turbo decoder is realized. The structural advantage of turbo code component coding is fully considered in the design process, and the problem of decoding delay caused by the existence of interleaver is cleverly avoided. The introduction of deep learning technology provides a new idea to solve the traditional communication problems. Simulation results show that the performance of the proposed decoder is improved by 0.5–1.5 dB compared with the traditional serial decoding algorithm in Gaussian white noise and t-distribution noise. When BER performance is close, the LSTM decoder requires half or even less than that of BCJR. Moreover, the results demonstrate that the proposed decoder is adaptive and can be applied to communication systems with various turbo codes. The LSTM decoder shows lower bit error rate, computational complexity and higher decoding efficiency under the same conditions. Therefore, it is necessary to study the turbo code decoding technology based on deep learning combined with the actual channel environment.

Research and Implementation of Turbo Coding Technology in High-Speed Underwater Acoustic OFDM Communication

It is demonstrated that the fully parallel turbo decoding algorithm can achieve an approximate error correction decoding performance when 36 iterations are used and when the log-map algorithm with 6 iterations is used. By comparison, it is shown that it can achieve much higher decoding rates than the log-map algorithm for various frame lengths of LTE standard turbo codes at the cost of higher hardware resource requirements. According to the fully parallel turbo decoding algorithm, this paper proposes a scheme for implementing a fully parallel turbo decoder on FPGA, detailing the overall structure and processing of the decoder hardware implementation, the design of the algorithm block processing unit, and the interleaving module. The performance of the decoder is tested by fixed-point simulation for different frame lengths of turbo coding in LTE standard, and it is proved that the fully parallel turbo decoder can be applied to turbo coding of various frame lengths. Both simulation and experimental results show that the distributed cancellation method and the joint estimation cancellation method have good results for both time-domain impulse noise and large-amplitude single frequency noise cancellation, while the joint estimation cancellation method of large-amplitude single frequency noise cancellation first has better performance.

Simplified on-The-Fly IAG QPP Interleaver for Turbo Channel Coding Scheme

Interleaver is an indispensable component in the design of Turbo encoder and Turbo Decoder. QPP interleaver is a 3GPP specified conflict free interleaver for turbo channel coding scheme for all code block sizes of 40 to 6144. Thus the efficient design of a conflict free reconfigurable QPP interleaver for turbo encoder and turbo decoder is a pre-eminent task in turbo channel coding scheme. In this article, Design of a simplified reconfigurable (40 to 6144 block sizes) Recursive QPP interleaver for computation of address locations to minimize the computational complexity and to avoid storage of interleaver tables has been presented. The proposed interleaver will be further integrated in the design and implementation of high throughput parallel turbo decoder. The proposed design is synthesized and implemented using 28nm CMOS technology Zynq Zed FPGA and achieved low processing timing constraints, utilization and power constraints compared with other conventional designs.

Arbitrarily Parallel Turbo Decoding for Ultra-Reliable Low Latency Communication in 3GPP LTE

In order to meet the latency requirements of the ultra-reliable low latency communication (URLLC) mode of the third-generation partnership project’s long term evolution (LTE) mobile communication standard, this paper proposes a novel turbo decoding algorithm that supports an arbitrarily high degree of parallel processing, facilitating significantly higher processing throughputs and substantially lower processing latencies than the state-of-the-art (SOTA) LTE turbo decoder. As in conventional turbo decoding algorithms, the proposed Arbitrarily Parallel Turbo Decoder (APTD) decomposes each frame of information bits into a sequence of windows, where the bits within different windows are processed simultaneously using forward and backward recursions in a serial manner. However, in contrast to conventional turbo decoding algorithms, the APTD does not require different windows to be composed of an identical number of bits, which allows the use of an arbitrary number of windows and hence an arbitrary degree of parallelism, when decoding information bits of an arbitrary frame length. Furthermore, conventional turbo decoding algorithms alternate between simultaneously processing the windows in the upper decoder and those in the lower decoder. By contrast, the APTD processes the odd-indexed windows in the upper decoder at the same time as the even-indexed windows in the lower decoder and alternates between this and the reversed arrangement, hence further improving the decoding throughput and latency. Furthermore, the APTD achieves a reduced hardware resource requirement by calculating the extrinsic information based only on the outputs of the forward recursions, rather than based on both the forward and backward recursions of conventional turbo decoding algorithms. We demonstrate that the proposed APTD achieves superior latency, throughput, and computational efficiency than the SOTA LTE turbo decoder at all frame lengths, but particularly at the short frame lengths that are typically used in URLLC approaches. For example, at a frame length of $N={504}$ bits, the proposed APTD achieves an FER of 10−5 at the same $E_{b}/N_{0}$ as $I=8$ iterations of a conventional turbo decoder but with a computational efficiency that is 6 times higher than that of the SOTA turbo decoder, while achieving a latency and throughput that are 0.7 and 1.4 times those of the SOTA decoder, respectively.

Parallel access by butterfly networks for any degree permutation polynomial and ARP interleavers

Using more processors for parallel turbo decoding is an important issue to speed up the processing at the receiver of a communication system. Butterfly networks used to map the addresses of extrinsic values represent an elegant and simple solution in parallel turbo decoding. Recently, it has been shown that quadratic permutation polynomial (QPP) interleavers allow an easy way to compute the control bits for a butterfly network. In this paper we show that not only QPP interleavers, but any degree permutation polynomial (PP) interleavers and almost regular permutation (ARP) interleavers also allow the same easy way to compute the control bits required in butterfly networks. As a consequence, it is useful to apply the butterfly networks in parallel turbo decoding when using these performant algebraic interleavers.

An efficient CPU‐GPU hybrid parallel implementation for DVB‐RCS2 receiver

SummaryThe second‐generation digital video broadcasting return channel via satellite (DVB‐RCS2) is a promising real‐time wireless protocol that has been widely used in many applications, such as video conferences, video feeds, and video multicasting. However, the receiver end of DVB‐RCS2 is time consuming and should be accelerated by high‐performance processing systems. Today, graphic processing units (GPUs) have been applied in communication systems due to high parallel capability and processing throughput. In this study, we design a novel pipeline of the receiver on the CPU‐GPU platform. Moreover, we propose a CPU‐GPU hybrid strategy to fully utilize resources and reduce communication latency. Compared with the parallel turbo decoder proposed in other work on the same platform, our parallel implementation achieves higher throughput. For the entire DVB‐RCS2 receiver, compared with the non‐pipelined serial and non‐pipelined parallel algorithms, our proposed pipeline obtains 20 times and 6 times speedup, respectively. In addition, the latency of our implementation is lower than that of non‐pipelined CPU‐GPU implementation, which is equal to 1.06 ms.

Analysis and power evaluation of window‐stopped parallel turbo decoding for LTE rate matching

Long-term evolution (LTE) adopts rate matching (RM) to reach high-speed data transmission. According to the LTE hybrid automatic repeat request scheme, the receiver can correct multiple transmission data with distinct code rates. Here, the window-stopped (WS) criterion is reinvestigated for the single-binary (SB) turbo code in LTE RM. The parallel SB WS turbo decoding for LTE RM with distinct parameters is analysed in terms of window stopping rate, kernel stopping rate, and correcting performance. Experimental results reveal that the early termination technique does not work well for high-code-rate decoding. However, the SB WS criterion significantly achieves up to 19% window stopping for decoding large codeword blocks and 37% kernel stopping for decoding small codeword blocks. Moreover, the SB WS criterion is implemented within a parallel turbo decoder for LTE RM using a 90 nm CMOS process. The evaluation results show that the power dissipation of the implemented WS parallel turbo decoder can be significantly reduced by 17% with a 0.7% area overhead for high-code-rate decoding and high channel quality.

Low Latency Parallel Turbo Decoding Implementation for Future Terrestrial Broadcasting Systems

As a class of high-performance forward error correction codes, turbo codes, which can approach the channel capacity, could become a candidate of the coding methods in future terrestrial broadcasting (TB) systems. Among all the demands of future TB system, high throughput and low latency are two basic requirements that need to be met. Parallel turbo decoding is a very effective method to reduce the latency and improve the throughput in the decoding stage. In this paper, a parallel turbo decoder is designed and implemented in field-programmable gate array (FPGA). A reverse address generator is proposed to reduce the complexity of interleaver and also the iteration time. A practical method of modulo operation is realized in FPGA which can save computing resources compared with using division operation. The latency of parallel turbo decoder after implementation can be as low as 23.2 us at a clock rate of 250 MHz and the throughput can reach up to 6.92 Gbps.

A High-Throughput FPGA Architecture for Joint Source and Channel Decoding

In the wireless transmission of multimedia information, the achievable transmission throughput and latency may be limited by the processing throughput and latency associated with source and channel coding. Ultra-high throughput and ultra-low latency processing of source and channel coding are required by the emerging new video transmission applications, such as the first-person remote control of unmanned vehicles. The recently proposed unary error correction (UEC) code facilitates the joint source and channel coding (JSCC) of video information at transmission throughputs that approach the capacity of the wireless channel. In this paper, we propose the first hardware implementation of the UEC code that achieves the high processing throughputs as well as ultra-low processing latencies required. This is achieved by extending the application of the recently proposed fully parallel turbo decoder (FPTD) from pure stand-alone channel coding to JSCC. This paper also proposes several novel improvements to the FPTD, in order to increase its hardware efficiency and supported frame length. We demonstrate the application of these improvements to both the long term evolution turbo code and the UEC code. We synthesize the proposed fully parallel design on a mid-range field programmable gate array, achieving a throughput of 450 Mbps, as well as a factor of 2.4 hardware efficiency improvement over previous implementations of the FPTD.

A multi-core-based heterogeneous parallel turbo decoder

A multi-core-based heterogeneous parallel turbo decoder

Design of QPP Interleavers for the Parallel Turbo Decoding Architecture

Parallel interleaver is an indispensable component for the parallel turbo decoder. The ever increasing data rates motivated by throughput-intensive applications result in higher parallelism of turbo decoder design, rendering the efficient realization of the interleaver a highly challenging work. This paper addresses the design of quadratic permutation polynomial (QPP) interleaver for the symbol-based serial MAP (SMAP) and the cross MAP (XMAP) parallel decoding. To circumvent the access conflicts incurred by the randomness of the interleaving function, the stratssonably position soft outputs of maximum a-posteriori (MAP) decoders in memory instances is firstly investigated. On this basis, a hardware-friendly parallel interleaver architecture is proposed by utilizing the algebraic properties of QPP function. Theoretical evaluation and experimental results demonstrate that the proposed design gains boosted hardware efficiency compared to existing schemes, and is applicable to both SMAP and XMAP decoding with arbitrary parallelism.

1.5 Gbit/s FPGA Implementation of a Fully-Parallel Turbo Decoder Designed for Mission-Critical Machine-Type Communication Applications

In wireless communication schemes, turbo codes facilitate near-capacity transmission throughputs by achieving reliable forward error correction. However, owing to the serial data dependencies imposed by the underlying logarithmic Bahl–Cocke-Jelinek–Raviv (Log-BCJR) algorithm, the limited processing throughputs of conventional turbo decoder implementations impose a severe bottleneck upon the overall throughputs of real-time wireless communication schemes. Motivated by this, we recently proposed a fully parallel turbo decoder (FPTD) algorithm, which eliminates these serial data dependencies, allowing parallel processing and hence offering a significantly higher processing throughput. In this paper, we propose a novel resource-efficient version of the FPTD algorithm, which reduces its computational resource requirement by 50%, which enhancing its suitability for field-programmable gate array (FPGA) implementations. We propose a model FPGA implementation. When using a Stratix IV FPGA, the proposed FPTD FPGA implementation achieves an average throughput of 1.53 Gb/s and an average latency of 0.56 $\mu \text{s}$ , when decoding frames comprising ${N}=720$ b. These are, respectively, 13.2 times and 11.1 times superior to those of the state-of-the-art FPGA implementation of the Log-BCJR long-term evolution (LTE) turbo decoder, when decoding frames of the same frame length at the same error correction capability. Furthermore, our proposed FPTD FPGA implementation achieves a normalized resource usage of 0.42 (kALUTs/Mb/s), which is 5.2 times superior to that of the benchmarker decoder. Furthermore, when decoding the shortest $N=40$ -b LTE frames, the proposed FPTD FPGA implementation achieves an average throughput of 442 Mb/s and an average latency of 0.18 $\mu \text{s}$ , which are, respectively, 21.1 times and 10.6 times superior to those of the benchmarker decoder. In this case, the normalized resource usage of 0.08 (kALUTs/Mb/s) is 146.4 times superior to that of the benchmarker decoder.

VLSI Implementation of Fully Parallel LTE Turbo Decoders

Turbo codes facilitate near-capacity transmission throughputs by achieving a reliable iterative forward error correction. However, owing to the serial data dependence imposed by the logarithmic Bahl–Cocke–Jelinek–Raviv algorithm, the limited processing throughputs of the conventional turbo decoder implementations impose a severe bottleneck upon the overall throughputs of real-time communication schemes. Motivated by this, we recently proposed a floating-point fully parallel turbo decoder (FPTD) algorithm, which eliminates the serial data dependence, allowing parallel processing and hence significantly reducing the number of clock cycles required. In this paper, we conceive a technique for reducing the critical datapath of the FPTD, and we propose a novel fixed-point version as well as its very large scale integration (VLSI) implementation. We also propose a novel technique, which allows the FPTD to also decode shorter frames employing compatible interleaver patterns. We strike beneficial tradeoffs amongst the latency, core area, and energy consumption by investigating the minimum bit widths and techniques for message log-likelihood ratio scaling and state metric normalization. Accordingly, the design flow and design tradeoffs considered in this paper are also applicable to other fixed-point implementations of error correction decoders. We demonstrate that upon using Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm low-power technology for decoding the longest long-term evolution frames (6144 b) received over an additive white Gaussian noise channel having $E_{b}/N_{0}=1~ \text {dB}$ , the proposed fixed-point FPTD VLSI achieves a processing throughput of 21.9 Gb/s and a processing latency of $0.28~ \mu \text {s}$ . These results are 17.1 times superior to those of the state-of-the-art benchmarker. Furthermore, the proposed fixed-point FPTD VLSI achieves an energy consumption of $2.69~ \mu \text {J}$ /frame and a normalized core area of $5~ \text {mm}^{\vphantom {R^{'}}2}/\text {Gb/s}$ , which are 34% and 23% lower than those of the benchmarker, respectively.

Implementation of a Fully-Parallel Turbo Decoder on a General-Purpose Graphics Processing Unit

Turbo codes comprising a parallel concatenation of upper and lower convolutional codes are widely employed in the state-of-the-art wireless communication standards, since they facilitate transmission throughputs that closely approach the channel capacity. However, this necessitates high processing throughputs in order for the turbo code to support real-time communications. In the state-of-the-art turbo code implementations, the processing throughput is typically limited by the data dependences that occur within the forward and backward recursions of the Log-BCJR algorithm, which is employed during turbo decoding. In contrast to the highly serial Log-BCJR turbo decoder, we have recently proposed a novel fully parallel turbo decoder (FPTD) algorithm, which can eliminate the data dependences and perform fully parallel processing. In this paper, we propose an optimized FPTD algorithm, which reformulates the operation of the FPTD algorithm so that the upper and lower decoders have identical operation, in order to support single instruction multiple data operation. This allows us to develop a novel general purpose graphics processing unit (GPGPU) implementation of the FPTD, which has application in software-defined radios and virtualized cloud-radio access networks. As a benefit of its higher degree of parallelism, we show that our FPTD improves the higher processing throughput of the Log-BCJR turbo decoder by between 2.3 and 9.2 times, when employing a high-specification GPGPU. However, this is achieved at the cost of a moderate increase of the overall complexity by between 1.7 and 3.3 times.

Low‐complexity CRC‐aided early stopping unit for parallel turbo decoder

A low-complexity distributed cyclic redundancy check (CRC) architecture for the CRC-aided early stopping unit is proposed. In the previous distributed CRC unit, the general high-order Galois field (GF) multiplier occupies almost the area of the CRC unit and requires high-hardware cost and long critical path-delay. Accordingly, a computation algorithm based on GF arithmetic is analysed and an optimal CRC unit with the small order of the GF multiplier and newly designed linear feedback shift register is proposed. The proposed CRC architecture is implemented in 65 nm CMOS process for radix-22 and radix-24 parallel turbo decoders based on LTE-Advanced. In the radix-22 system, reductions of about 57.1% of gate count, 31.7% of critical path-delay and 44.1% of power consumption are achieved compared with the previous work.

Memory-Reduced Maximum A Posteriori Probability Decoding for High-Throughput Parallel Turbo Decoders

Wireless communication standards make use of parallel turbo decoder for higher data rate at the cost of large hardware resources. This paper presents a memory-reduced back-trace technique, which is based on a new method of estimating backward-recursion factors, for the maximum a posteriori probability (MAP) decoding. Mathematical reformulations of branch-metric equations are performed to reduce the memory requirement of branch metrics for each trellis stage. Subsequently, an architecture of MAP decoder and its scheduling based on the proposed back trace as well as branch-metric reformulation are presented in this work. Comparative analysis of bit-error-rate (BER) performances in additive white Gaussian noise channel environment for MAP as well as parallel turbo decoders are carried out. It has shown that a MAP decoder with a code rate of 1/2 and a parallel turbo decoder with a code rate of 1/3 have achieved coding gains of 1.28 dB at a BER of 10$$^{-5}$$-5 and of 0.4 dB at a BER of 10$$^{-4}$$-4, respectively. In order to meet high-data-rate benchmarks of recently deployed wireless communication standards, very large scale integration implementations of parallel turbo decoder with 8---64 MAP decoders have been reported. Thereby, savings of hardware resources by such parallel turbo decoders based on the suggested memory-reduced techniques are accounted in terms of complementary metal oxide semiconductor transistor count. It has shown that the parallel turbo decoder with 32 and 64 MAP decoders has shown hardware savings of 34 and 44 % respectively.

Distributed CRC Architecture for High-Radix Parallel Turbo Decoding in LTE-Advanced Systems

This brief presents two types of distributed cyclic redundancy check (CRC) architecture for a high-radix parallel turbo decoder in LTE/LTE-advanced communication systems. The conventional CRC architecture in the parallel turbo decoder requires both huge timing overhead and energy waste since the CRC of the message is calculated after completion of the soft-input soft-output (SISO) decoding process or concurrently with the next SISO decoding, even though the message is already confirmed for its integrity. The distributed CRC architecture proposed in this brief computes the CRC while the message is decoded separately, and it can provide the stopping signal to the decoder with negligible computing latency after completion of the SISO decoding process. The two proposed architectures are based on Galois field arithmetic and implemented in a 65-nm CMOS process where various block sizes, degrees of parallelism, and radix numbers of the high-radix SISO decoder are supported.

High performance parallel turbo decoder with configurable interleaving network for LTE application

In this paper, a high performance parallel turbo decoder is designed to support 188 block sizes in the 3rd generation partnership (3GPP) long term evolution (LTE) standard. A novel configurable quadratic permutation polynomial (QPP) multistage network and address generator are proposed to reduce the complexity of interleaving. This 2n-input network can be configured to support any 2i-input (0≤i≤n) network. Furthermore, it can flexibly support arbitrary contention-free interleavers by cascading an additional specially designed network. In addition, an optimized decoding schedule scheme is presented to reduce the performance loss caused by high parallelism. Memory architecture and address mapping method are optimized to avoid memory access contention of small blocks. Moreover, a dual-mode add–compare–select (ACS) unit implementing both radix-2 and radix-4 recursion is proposed to support the block sizes that are not divided by 16. Implemented in 130nm CMOS technology, the design achieves 384.3Mbps peak throughput at clock rate of 290MHz with 5.5 iterations. Consuming 4.02mm2 core area and 716mW power, the decoder has a 1.81bits/cycle/iteration/mm2 architecture efficiency and a 0.34nJ/bit/iteration energy efficiency, which is competitive with other recent works.

Generation of New Collision Free S-Random Interleavers of Turbo Codes

For high data rate transmission, the parallel turbo decoding can guarantee high communication reliability as well as reduce the decoding latency greatly. A challenge in the design of parallel turbo decoder is the design of collision-free interleavers in order to avoid the memory access collision in the decoding process. In this letter, a novel algorithm for the generation of collision free S-random interleavers of turbo codes is proposed. The proposed algorithm can obtain larger spreading factor, S, and better average code distance than the existing collision free row column S-random interleavers.