Parallel SystemC Research Articles

Standard-compliant parallel SystemC simulation of loosely-timed transaction level models: From baremetal to Linux-based applications support

To face the growing complexity of System-on-Chips (SoCs) and their tight time-to-market constraints, Virtual Prototyping (VP) tools based on SystemC/TLM2.0 must get faster while maintaining accuracy. However, the ASI SystemC reference implementation remains sequential and cannot leverage the multiple cores of modern workstations. In this paper, we present SCale 2.0, a new implementation of a parallel and standard-compliant SystemC kernel, reaching unprecedented simulation speeds. By coupling a parallel SystemC kernel with shared resources access monitoring and process-level rollback, we can preserve SystemC atomic thread evaluation while leveraging the available host cores. We also generate process interaction traces that can be used to replay any simulation deterministically for debug purpose. Evaluation on baremetal applications shows × 15 speedup compared to the ASI SystemC kernel using 33 host cores reaching speeds above 2300 Million simulated Instructions Per Second (MIPS). Challenges related to parallel simulation of full software stack with modern operating systems are also addressed with speedup reaching × 13 during recording run and × 24 during the replay run.

Seven Obstacles in the Way of Standard-Compliant Parallel SystemC Simulation

The IEEE 1666-2011 standard defines SystemC based on traditional discrete event simulation (DES) and sequential co-routine semantics, despite explicit parallelism in the model and ample parallel processor cores available in today’s host computers. In order to evolve the SystemC standard toward faster parallel DES, substantial hurdles must be overcome. This letter identifies seven obstacles in the standard that stand in the way of efficient parallel SystemC simulation, namely the co-routine semantics, simulator state, lack of thread safety, the role of channels, TLM-2.0, sequential mindset, and temporal decoupling. For each obstacle, we discuss the problem and propose a potential solution toward truly parallel SystemC. This letter to the editor is meant to identify difficulties with IEEE SystemC and stimulate fruitful discussion in the community.

Adaptive algorithm and tool flow for accelerating SystemC on many-core architectures

Within this article an adaptive approach for parallel simulation of SystemC RTL models on future many-core architectures like the Single-chip Cloud Computer (SCC) from Intel is presented. It is based on a configurable parallel SystemC kernel that preserves the partial order defined by the SystemC delta cycles while avoiding global synchronization as far as possible. The underlying algorithm relies on a classification of existing communication relations between parallel processes. The type and topology of communication relations determines the type and number of causality conditions that need to be fulfilled during runtime. The parallel kernel is complemented by an automated tool flow that allows detecting relevant model-specific properties, performing a fine-grained model partitioning, classifying communication relations and configuring the kernel. Experiments by means of a MPSoC model show that pure local synchronization can provide significant performance gains compared to global synchronization. Furthermore, the combination of local synchronization with fine-grained partitioning provides additional degrees of freedom for optimization.

LegaSCi

Architects and developers use virtual prototypes of computer systems to receive early feedback on hardware design decisions as well as to develop and debug system software. This is facilitated by the comprehensive inspection capabilities virtual prototypes offer. For virtual prototypes, execution speed is crucial to support the users' productivity. Parallel simulation techniques are employed to offset the speed impact of the increasing number of cores that need to be simulated in virtual prototypes of parallel and embedded systems. SystemC is the de facto industry standard library for virtual platform modeling. Since currently no parallel SystemC library is commonly available, typical SystemC models are coded for execution in sequential simulation environments. Simply putting such models into parallel simulators may lead to thread-safety issues and may additionally cause nondeterministic simulator behavior. This article proposes a methodology to support simulation creators to face the challenge of integrating such legacy models into parallel SystemC environments. The feasibility of the proposed method is evaluated by parallelizing the latest instance of the EU FP7 project EURETILE embedded platform simulator. Using legaSCi , on four host processor cores a speedup of 2.13× is demonstrated, without having to change the individual models of the simulator.