Subtractor Research Articles

A miniature design of binary subtractor using 2-D photonic crystal structure for high-speed applications

The expansion of the digital market is accelerating, and for faster communication, optical technologies have been developed. The binary subtractor is a combinational circuit that can compute the subtraction operations in arithmetic logic unit (ALU). The desired design is depicted as a 2-D structure with two T-shaped waveguides, and it is operates at a wavelength of 1550nm. The design is verified and analyzed using finite-difference-time-domain (FDTD) method. It is also verified using MATLAB software. The identical design has been computed and simulated numerous times in this work, but with different lattice constants, refractive indices, and silicon rod radii. In this study, photonic crystals are used to construct a binary subtractor that is both compact and capable of producing a high contrast ratio (5.185dB for difference and 17.78dB for borrow). Moreover, the transmission efficiency is achieved 89.3%, insertion loss is 0.49dB, and the response time and bit rate are achieved by 0.0204Ps and 49.01Tbps respectively.

Design of a Novel Signed Binary Subtractor Using Quantum Gates

Design of a Novel Signed Binary Subtractor Using Quantum Gates

Quantum Circuit Realization of Morphological Gradient for Quantum Grayscale Image

In this paper, based on the principle of classical morphology operations, the flat grayscale dilation and erosion operations are proposed for NEQR quantum image model. Furthermore, through combining these two morphology operations, we further realize the morphological gradient operation. As the basis of designing of grayscale morphology operations, a series of quantum circuit designs arepresented, which includes special add one operation UA1(n) and special subtract one operation US1(n) both for an n-length qubits sequence, quantum unitary operation UC, parallel subtractor (PS) module, quantum comparator output the large QCOL and quantum comparator output the small QCOS modules. When designsthe concrete quantum circuit, a sequence of UA1(n) and US1(n) modules are used to obtain the quantum image sets based on the shape of specific structuring element. Then, the searching for maximaor minima in a certain space is involved, which can be solved by cascading a series of QCOL and QCOS modules in certain order. Finally, the PS module can be used to calculate the difference of the maxima and minima for producing the morphological gradient. The circuit’s complexity analysis illustrate that our scheme is very lower to the classical morphology operations.

A FHD 1080, 120 fps CMOS image sensor with two step SS-ADC

This paper presents a full high definition 1920 × 1080 pixel, 120 frames/s CMOS image sensor with two-step single-slope (TS-SS) ADC. The column-parallel TS-SS ADC and binary subtractor are used to convert photodiode voltage to the final 10-bit digital data. Therefore, there is no need for the pixel readout, noise suppression or comparator offset cancellation circuits to be used in the columns. A new ramp signal generator is proposed to generate 32 concurrent and identical ramp signals. TS-SS ADC improves the conversion speed while reducing the power consumption level as well. The proposed image sensor has been designed using TSMC 0.18 μm 1-poly 4-metal standard process. The simulation results show that the total comparator referred noise to the FD node in 1 Hz–100 MHz range is 0.574 mV and, also the total power consumption is about 100 mW.

Investigations with All Optical Binary Subtractor Network at 100Gbps

Investigations with All Optical Binary Subtractor Network at 100Gbps

Quantum realization of the bilinear interpolation method for NEQR

In recent years, quantum image processing is one of the most active fields in quantum computation and quantum information. Image scaling as a kind of image geometric transformation has been widely studied and applied in the classical image processing, however, the quantum version of which does not exist. This paper is concerned with the feasibility of the classical bilinear interpolation based on novel enhanced quantum image representation (NEQR). Firstly, the feasibility of the bilinear interpolation for NEQR is proven. Then the concrete quantum circuits of the bilinear interpolation including scaling up and scaling down for NEQR are given by using the multiply Control-Not operation, special adding one operation, the reverse parallel adder, parallel subtractor, multiplier and division operations. Finally, the complexity analysis of the quantum network circuit based on the basic quantum gates is deduced. Simulation result shows that the scaled-up image using bilinear interpolation is clearer and less distorted than nearest interpolation.

Pipelined Quadratic Equation Based Novel Multiplication Method for Cryptographic Applications

Digital number system in a computer performs the basic arithmetic operation using multiplier. The functionality of this multiplier can be obtained through addition, subtraction and right shift operations but the utilization of adders, subtractors and shift registers components to perform multiplication is huge. So we proposed the multiplication algorithm for computer by altering the existing booth methodology, which reduces the component and complexity of the multiplication process. The novel algorithm is implemented on pipeline quadratic equations and verified through the simulation result. The arithmetic circuit is written in VHDL and synthesized with Xilinx using Spartan 3 FPGA kit.

High performance FPGA architecture for dual mode processor of Integer Haar Lifting-based Wavelet Transform

Discrete Wavelet Transform (DWT) becomes a major part for many applications. Fast, low area, and low power consumption hardware for DWT is necessary for some new technologies such as OFDM transceiver and wireless multimedia sensor networks. This paper presents efficient dual mode (decomposition and reconstruction) Integer Haar Lifting Wavelet Transform (IHLWT) architecture. The proposed architecture reduces the hardware requirements by exploiting the arithmetic operations redundancy which is involved in IHLWT computations. It is multiplier-free and it performs IHLWT with only a single adder and subtractor which have reconfigurable input buses to perform decomposition and reconstruction transformations. IEEE standard VHDL has been used to develop the proposed processor. This makes the design vendor independent and therefore easily portable across FPGA devices from multiple vendors. The generic design is flexible and can perform any arbitrary signal length. The synthesis of the processor showed that it requires low number of CLB-slices and low power consumption with high operating-frequency for various Xilinx FPGA devices. The processor has been successfully implemented and tested on Xilinx Spartan6-SP601 Evaluation Board. The implemented hardware has been tested in real time by using many recording audio signals. All the implemented hardware results were identical 100% with IHLWT software results.

Nonlinear Material Based All-Optical Parallel Subtraction Scheme: an Implementation

Non-linear material based all-optical switching mechanism is utilized here to implement the all-optical paral- lel subtraction scheme. Optical tree architectures here convert analog optical signal to the corresponding digital one. A two bit all-optical binary parallel subtractor has been proposed and which may be elevated to a higher bit parallel subtractor in course using all-optical half-subtractor and a full-subtractor. These are constructed by a composite slab of linear medium (LM) and non-linear medium (NLM) and it is the building block of our proposed subtructor circuit. These circuits are all-optical and fully parallel in nature. It can also gear up to the highest ability of optical performance in high-speed all-optical computing system.

Molecular solutions of the RSA public-key cryptosystem on a DNA-based computer

The RSA public-key cryptosystem is an algorithm that converts a plain-text to its corresponding cipher-text, and then converts the cipher-text back into its corresponding plain-text. In this article, we propose five DNA-based algorithms—parallel adder, parallel subtractor, parallel multiplier, parallel comparator, and parallel modular arithmetic—that construct molecular solutions for any (plain-text, cipher-text) pair for the RSA public-key cryptosystem. Furthermore, we demonstrate that an eavesdropper can decode an encrypted message overheard with the linear steps in the size of the encrypted message overheard.

Constructing Bio-molecular Parallel Subtractor and Divider with Basic Bio-logic Operations in the Adleman-Liption Model

Constructing Bio-molecular Parallel Subtractor and Divider with Basic Bio-logic Operations in the Adleman-Liption Model

Fast Parallel DNA-Based Algorithms for Molecular Computation: The Set-Partition Problem

This paper demonstrates that basic biological operations can be used to solve the set-partition problem. In order to achieve this, we propose three DNA-based algorithms, a signed parallel adder, a signed parallel subtractor and a signed parallel comparator, that formally verify our designed molecular solutions for solving the set-partition problem.

Fast Parallel Molecular Algorithms for DNA-Based Computation: Factoring Integers

The RSA public-key cryptosystem is an algorithm that converts input data to an unrecognizable encryption and converts the unrecognizable data back into its original decryption form. The security of the RSA public-key cryptosystem is based on the difficulty of factoring the product of two large prime numbers. This paper demonstrates to factor the product of two large prime numbers, and is a breakthrough in basic biological operations using a molecular computer. In order to achieve this, we propose three DNA-based algorithms for parallel subtractor, parallel comparator, and parallel modular arithmetic that formally verify our designed molecular solutions for factoring the product of two large prime numbers. Furthermore, this work indicates that the cryptosystems using public-key are perhaps insecure and also presents clear evidence of the ability of molecular computing to perform complicated mathematical operations.

A "subtractor" for radio-frequency bridges

A "subtractor" for radio-frequency bridges