Paralleled Silicon Carbide MOSFETs Research Articles

Junction temperature balance control for paralleled SiC MOSFETs based on active gate control

Power devices operating in parallel often experience thermal stress imbalances, which can lead to failures, especially in silicon carbide (SiC) MOSFETs. To enhance their reliability, controlling the junction temperature becomes crucial. Existing research focuses on addressing current imbalances in parallel devices, neglecting the issue of junction temperature imbalances. It is worth noting that even with balanced currents, the junction temperatures may still vary. To address this challenge, we propose a novel active gate control-based method for achieving junction temperature balance in parallel devices. This method not only ensures junction temperature balance but also effectively suppresses dynamic current peaks. To validate the effectiveness of our approach, we conducted experimental tests on a BUCK converter utilizing two parallel SiC MOSFETs. The experimental results demonstrate the achievement of junction temperature balance and excellent suppression of dynamic current peaks through the proposed method.

Active Auto-Suppression Current Unbalance Technique for Parallel-Connected Silicon Carbide MOSFETs

Nowadays, medium- and high-power applications make use of silicon carbide (SiC) MOSFETs, and many times their parallelization is necessary. Unfortunately, this requirement causes an inevitable current unbalance between power devices, affecting the performance of power switches. Over the last decade, numerous studies have been conducted, proposing various techniques with the capability of mitigating current unbalance for a number of discrete parallel SiC MOSFETs. However, the realization of most methods requires knowledge of the technical characteristics of power devices, adding extra cost to the system, since screening is a time-consuming and costly process. This necessity reduces the possibilities of such a technique being implemented in power electronics applications, preventing the exploitation of the exceptional features of SiC MOSFETs. In addition, most of these techniques can suppress only the current unbalance, which occurs during turn-on and turn-off transitions. In this paper, an active auto-suppression current unbalance technique is proposed, requiring no device screening. The active method is a closed-loop system capable of sensing and eliminating the entire current unbalance between parallel SiC MOSFETs automatically, actively, and independently of the cause. Simulation results are presented to demonstrate the feasibility and effectiveness of the proposed technique.

Accurate Modeling of the Effective Parasitic Parameters for the Laminated Busbar Connected With Paralleled SiC MOSFETs

Silicon Carbide (SiC) MOSFETs are usually paralleled to increase the current capability for high power applications. While, the asymmetrical parasitic parameters of the wide-used laminated busbar can cause current imbalance for paralleled MOSFETs. The fast switching of SiC devices can further deteriorate the imbalance. However, the complex current paths and their mutual effects are seldom considered and effectively modeled for the parasitics of the busbar, which is not accurate enough to evaluate the current imbalance for the busbar connected with SiC devices. This paper proposes accurate modeling of the effective parasitic parameter of laminated busbars with paralleled SiC MOSFETs. The model incorporates not only the self-inductance and resistance but also the complex mutual coupling effect of all the current paths. Moreover, a switching period is divided into two durations for accurate effective parasitic models, in which the busbar can have different effective models regarding one physical structure. Furthermore, for easy evaluation of the current balance, a single effective model, namely equivalent model, is derived for a physical structure by replacing the complex mutual network. A specific laminated busbar for EV inverter is analyzed to prove the above theory, which is validated by simulation and experiment separately.

Effect of Asymmetric Layout and Unequal Junction Temperature on Current Sharing of Paralleled SiC MOSFETs With Kelvin-Source Connection

Parallel connection of silicon carbide (SiC) mosfets is a popular solution for high-capacity applications. In order to improve the switching speed of paralleled SiC mosfets, Kelvin-source connection is widely employed. However, the influences of asymmetric layout and unequal junction temperature on current sharing of paralleled SiC mosfets with Kelvin-source connection are not clear. This article addresses the issue for the first time by theoretical analysis and experimental verifications. The mechanism of current imbalance resulting from asymmetric layout and unequal junction temperature in the case with Kelvin-source connection is comprehensively investigated. Then, some significant discoveries are obtained. The static current sharing performance can be affected by drain and power source parasitic inductance, which is seldom mentioned before. Besides, this article first points out that the effect of power source parasitic inductance on dynamic current sharing is dominant compared with other parasitic inductance. What is more, the thermal-electric analyzing results suggest that there is a risk of thermal runaway for paralleled SiC mosfets with Kelvin-source connection at high switching frequency due to positively temperature-dependent dynamic current and switching losses. Based on the discoveries, some guidelines are provided for layout design and application of paralleled SiC mosfets with Kelvin-source connection.

Current Balancing of Paralleled SiC mosfets for a Resonant Pulsed Power Converter

Paralleling silicon carbide (SiC) mosfets is a cost-effective solution for increasing pulse current rating. However, the device SiC mosfets mismatch and asymmetrical circuit layout would lead to imbalance current of the paralleled SiC mosfets . In this letter, we propose a passive approach, that is, a coupled inductor instead of the conventional resonant inductor, which is used for a resonant pulsed power converter. The coupled inductor enables even current sharing of the parallel SiC mosfet s, and also helps with pulsewidth adjustment, which leads to a simplified system without complex control circuit compared with the active solution. The configuration of the proposed topology, operating principle, imbalance current limitation mechanism, and design guidelines are fully discussed and presented. Additionally, experiments are carried out to verify the analysis and effectiveness of the proposed solution. The proposed method can be extended to the scenario with more than two parallel.

Imbalance Current Analysis and Its Suppression Methodology for Parallel SiC MOSFETs with Aid of a Differential Mode Choke

Parallel connection of silicon carbide (SiC) MOSFETs is a cost-effective solution for high-capacity power converters. However, transient imbalance current, during turn- on and - off processes, challenges the safety and stability of parallel SiC MOSFETs. In this paper, considering the impact factors of device parameters, circuit parasitics, and junction temperatures, in-depth mathematical models are created to reveal the electrothermal mechanisms of the imbalance current. Moreover, with the incorporation of a differential mode choke (DMC), an effective approach is proposed to suppress the imbalance current among parallel SiC MOSFETs. Physics concepts, operation principles, and design guidelines of the DMC-based suppression method are fully presented. Besides, to reduce the equivalent leakage inductance and equivalent parallel capacitance of the DMC, winding patterns of the DMC are comparatively studied and optimized to suppress turn- off over-voltage and switching ringing. Concerning the influence of winding patterns, load currents, gate resistances, and junction temperatures, experimental results are comprehensively demonstrated to confirm the validity of theoretical models and the function of the proposed DMC-based suppression method. It is turned out the low-cost DMC is easy to design and utilize without complex feedback circuits or control schemes, which is a cost-effective component to guarantee consistent and synchronous on–off trajectories of parallel SiC MOSFETs.