Parallel Routing Algorithm Research Articles

Network Coding with Parallel Path Protection for Multiple Link Failure in WOBAN

Background: WOBAN is a high-speed network and hence any kind of failure results in huge data loss. Using the proposed network coding technique with parallel path protection can handle multiple link failures, the performance of the network can be improved. Aims: This study aims to improve network performance using network coding with parallel path protection routing algorithm (NC-PPR) for multiple link failures in WOBAN. Objective: We investigated the multiple link failures in WOBAN by the proposed approach namely Coded Path Protection Algorithm, which enhances the survivability of the WOBAN against multiple link failures in the front end and eliminates the need of backup resources. Methods: Extensive simulation is carried out to implement proposed work. A simulation model and code is developed in MATLAB to get the performance enhancement of WOBAN. Results: We compared the performance of proposed algorithm with existing algorithm. The obtained results show that the proposed algorithm has superior performance than the existing algorithm. Conclusion: In this paper, a new routing approach, which works in three phases namely path finding, encoding, and decoding, using random linear network coding (RLNC) is introduced to address the survivability issue of the WOBAN. The proposed approach also enhances the network performance in terms of PDR, overhead, and delay.

Exploring Josephus Interconnection Networks : Unveiling Architecture, Applications, and Recent Advancements

This abstract delves into the distinctive features, applications, challenges, and future directions of Josephus Interconnection Networks. These networks, characterized by a circular topology and deterministic communication paths, present a novel approach to interconnected systems, promising advancements in parallel computing, routing algorithms, and fault tolerance. The recapitulation of key findings highlights ongoing developments in dynamic node management, routing algorithm optimization, and adaptive fault tolerance mechanisms. Implications for interconnected systems encompass efficient parallel processing, rendering Josephus networks apt for distributed and edge computing. The challenges in implementation, notably hardware complexity, underscore the necessity for continual research. Future applications envision roles in distributed computing, edge computing, and potential integration with quantum computing. The abstract concludes by emphasizing the exciting prospects for Josephus networks as they navigate historical inspiration and modern computational challenges in the evolving landscape of interconnected systems.

A Fast FPGA Connection Router Using Prerouting-Based Parallel Local Routing Algorithm

Routing is one of the most time-consuming steps in the FPGA design process. Even if unceasing efforts have been made to accelerate FPGA routing, the existing work seldom pays attention to the underlying FPGA connection router. In this paper, we present a fast FPGA connection router called PRoute which implements a novel pre-routing based parallel local routing algorithm. Basically, PRoute pre-computes the potential routing solutions for various connection patterns on FPGAs, which can be directly used in the later practical routing. On the whole, PRoute is composed of A-star maze expansion and parallel local search. In the first part, PRoute gradually expands the maze wavefront towards the lowest-cost node to search for the target sink. For a wire-type node, PRoute invokes a fast parallel local search instead taking advantage of the pre-routing results, and hence the time-expensive maze expansion can be reduced. Particularly, it allows PRoute to call one another between A-star maze expansion and parallel local search. This enables the runtime efficiency of PRoute while ensuring its global search ability. In addition, we put forward an engineering improvement to further speed up PRoute by avoiding the exploration of block output pins. To our best knowledge, this work is the first to apply the idea of pre-routing for FPGAs. Experimental results show that PRoute achieves speedups of 1.8×, 2.4×, 3.2×, 4.1× and 5.1× with 1, 4, 8, 16 and 32 threads relative to the baseline VPR’s connection router respectively, without degrading the quality of results.

Construction and Realization Path Analysis of Cross-Border E-Commerce Logistics Collaboration Model

In order to improve the synergy effect of cross-border e-commerce slogistics, this paper combines intelligent logistics communication technology to construct a cross-border e-commerce collaborative logistics model. Moreover, this paper proposes a parallel energy-efficient routing algorithm based on 3D cell space to improve the system operation effect. In addition, this paper deeply analyzes the data fusion function performed by MA when accessing nodes and proposes a data fusion criterion to judge the necessity of data fusion on nodes. Finally, this paper balances the energy consumption of e-commerce logistics data fusion and data transmission so that the sum of the two is minimized. The data simulation analysis shows that the cross-border e-commerce logistics collaboration model proposed in this paper has certain effects, and it can be applied to the actual operation of cross-border e-commerce.

Parallel Route Optimization and Service Assurance in Energy-Efficient Software-Defined Industrial IoT Networks

In recent years, the Industrial world has been embracing new digital technology, including the internet of things (IoT) paradigm that promises revolutionizing-prospects in numerous industrial applications. However, many deployment challenges related to real-time big data analytics, service assurance, resource optimization, energy consumption, and security awareness are raised. In this work, we focus on service assurance and resource optimization, including energy consumption challenges over Industrial Internet of Things (IIoT)-based environments since the existing network routing algorithms cannot meet the strict heterogeneous quality of service (QoS) requirements of industrial communications while optimizing resources. We take advantage of the flexibility and programmability offered by the promising software-defined networking paradigm, and we propose a centralized route optimization and service assurance scheme, named ROSA, over a multi-layer programmable industrial architecture. The proposed solution supports a wide range of heterogeneous flows, such as ultra-reliable low-latency communications (URLLC) and bandwidth-sensitive services. The routing optimization problems are formulated as multi-constrained shortest path problems. The Lagrangian Relaxation approach is used to solve the . Hence, we deploy a pair of parallel routing algorithms run according to the flow type to ensure QoS requirements, efficiently allocate constrained resources, and enhance the overall network energy consumption. We conduct extensive simulations to validate the proposed ROSA scheme. The experimental results show promising performance in terms of reducing bandwidth utilization by up to 22%, end-to-end delay at least by 21%, packet loss by more than 19%, flow violation by about 16%, and energy consumption up to 14% as compared to well-known benchmarks in QoS provisioning and energy-aware routing problem.

Protection and Activation of Cultural Heritage Based on Cloud Computing Platform

Cultural heritage is the crystallization of the wisdom of peoples of all countries. Its value is inestimable, and countries and regions around the world have reached a consensus on protecting cultural heritage. The digital museum uses virtual reality technology, three-dimensional scanning technology, computer network technology and other display technologies to present the physical museum in a three-dimensional manner in the network application in the real world. The challenges facing the construction of digital museums mainly come from two aspects: Technically, digital museums can be regarded as a combination of a large-scale distributed information resource database and a multimedia broadband network, and a unified platform resource for cultural heritage natural resource information sharing and services. In terms of management, there are a series of problems in the management of digital museums in all stages of data collection, storage, transmission, and display. Based on the above background, the research content of this article is the protection and activation of cultural heritage based on cloud computing platform. This article analyzes the technical problems facing digital museums. Based on the in-depth study of Hadoop cloud computing, a digital museum construction plan based on Hadoop and a distributed multi-QoS parallel routing algorithm based on TCP / IP are proposed. This paper mainly adopts multi-QoS distributed parallel routing algorithm to improve the data transmission efficiency, thereby improving the query response speed of the system. This paper analyzes the theoretical foundation of Hadoop and the feasibility of building a digital museum, and builds the module implementation of the digital museum. Finally, the construction of Hadoop experimental environment is introduced. Simulation results show that compared with traditional algorithms, the improved algorithm can balance network load and improve network resource utilization. The performance analysis of the system verifies that the model proposed in this paper meets the requirements of security and integrity.

Multi-stage Interconnection networks CLOS/BENES Parallel Routing Algorithms for circuit switching system

This article approaches the design of parallel routing Clos and Benes switching networks in Communication Technology. In communication, the transmission of data with less traffic and low latency are the biggest challenges. The conventional packet switching circuits takes the more power and high area to overcome this problem parallel routing algorithms are proposed. Clos and Benes networks are designed for the circuit switching systems where the switching configuration will be rearranged and it’s relatively low speed. Most of the existing parallel routing algorithms are not practical those are fail to interconnects the inputs with the matched outputs with less traffic. In this article, we designed Clos and Benes network. Clos and Benes networks are the Non-blocking switching Networks. Clos Switching network provides the better results like low area and less delay when compare with the Benes Switching Network. Clos and Benes non-blocking switching circuits are designed by Verilog HDL, Synthesized and simulated by XILINX 12.1 tool

Study of Parallel Algorithms for IP Switches

Abstract Owing to the increase in the internet traffic, any calculation that requires more than linear time would be considered unreasonably moderate for constant applications. One cure is to utilize numerous processors to build up associations in parallel and the other is to construct low cost, high speed, large capacity non-blocking switching architecture. In this paper, our focus is on developing parallel algorithms for routing which will ensure high-speed internet connectivity and at the same time making the system to be cost effective.

Parallel Routing Algorithm for Call Centers Based on Local Mutual Exclusion

Parallel Routing Algorithm for Call Centers Based on Local Mutual Exclusion

Hardware design of parallel switch setting algorithm for Benes networks

Benes/Clos networks have been used in many areas, such as interconnection network in parallel computers, multiprocessors system, and networks-on-chip. The parallel switch setting algorithm is the key to satisfy the requirements of high performance switching networks. The Lee's routing algorithm is by far the most efficient parallel routing algorithm for Benes networks. However, there is no hardware implementation for this algorithm. In this paper, the Lee's routing algorithm is fully implemented in RTL and synthesised. We have refined the algorithm in data structure and initialisation/updating of relation values to make it suitable for hardware implementation. The simulation and synthesis results of the switching setting circuits for 4 × 4 to 64 × 64 Benes networks confirm that the timing, area, and power consumption of the circuit is consistent with the complexity of the Lee's algorithm. To the best of our knowledge, this is the first complete hardware implementation of the parallel switch setting algorithm which can handle all types of permutations including partial ones.

Hardware design of parallel switch setting algorithm for Benes networks

Benes/Clos networks have been used in many areas, such as interconnection network in parallel computers, multiprocessors system, and networks-on-chip. The parallel switch setting algorithm is the key to satisfy the requirements of high performance switching networks. The Lee's routing algorithm is by far the most efficient parallel routing algorithm for Benes networks. However, there is no hardware implementation for this algorithm. In this paper, the Lee's routing algorithm is fully implemented in RTL and synthesised. We have refined the algorithm in data structure and initialisation/updating of relation values to make it suitable for hardware implementation. The simulation and synthesis results of the switching setting circuits for 4 × 4 to 64 × 64 Benes networks confirm that the timing, area, and power consumption of the circuit is consistent with the complexity of the Lee's algorithm. To the best of our knowledge, this is the first complete hardware implementation of the parallel switch setting algorithm which can handle all types of permutations including partial ones.

Application of the Hamiltonian circuit Latin square to a Parallel Routing Algorithm on Generalized Recursive Circulant Networks

A generalized recursive circulant network(GR) is widely used in the design and implementation of local area networks and parallel processing architectures. In this paper, we investigate the routing of a message on this network, that is a key to the performance of this network. We would like to transmit maximum number of packets from a source node to a destination node simultaneously along paths on this network, where the i th packet traverses along the i th path. In order for all packets to arrive at the destination node securely, the i th path must be node-disjoint from all other paths. For construction of these paths, employing the Hamiltonian Circuit Latin Square(HCLS), a special class of (n x n) matrices, we present O(n 2 ) parallel routing algorithm on generalized recursive circulant networks.

Integrating Transactions into the Data-Driven Multi-threading Model Using the TFlux Platform

The introduction of multi-core processors has renewed the interest in programming models which can efficiently exploit general purpose parallelism. Data-Flow is one such model which has demonstrated significant potential in the past. However, it is generally associated with functional styles of programming which do not deal well with shared mutable state. There have been a number of attempts to introduce state into Data-Flow models and functional languages but none have proved able to maintain the simplicity and efficiency of pure Data-Flow parallelism. Transactional memory is a concurrency control mechanism that simplifies sharing data when developing parallel applications while at the same time promises to deliver affordable performance. In this paper we report our experience of integrating Transactional Memory and Data-Flow within the TFlux Platform. The ability of the Data-Flow model to expose large amounts of parallelism is maintained while Transactional Memory provides simplified sharing of mutable data in those circumstances where it is important to the expression of the program. The isolation property of transactions ensures that the exploitation of Data-Flow parallelism is not compromised. In this study we extend the TFlux platform, a Data-Driven Multi-threading implementation, to support transactions. We achieve this by proposing new pragmas that allow the programmer to specify transactions. In addition we extend the runtime functionality by integrating a software transactional memory library with TFlux. To test the proposed system, we ported two applications that require transactional memory: Random Counter and Labyrinth an implementation of Lee's parallel routing algorithm. Our results show good opportunities for scaling when using the integration of the two models.

A Parallel Disjointed Multi-path Routing Algorithm based on OLSR and Energy in Ad Hoc Networks

Aiming at the instability and uncertainty of mobile nodes and low-power wireless communications links in Ad hoc networks, a parallel disjointed multi-path routing algorithm called DMP_EOLSR is proposed in the paper. It is based on the OLSR routing algorithm, and considers the living time of nodes and links according to the energy consumption and moving mode of nodes. At the same time, to find different node-disjointed or link-disjointed paths, an iterative algorithm is used in the multi-path selecting processes based on modified Dijkstra' algorithm, and a method of route recovering is also given in the end. The simulation results show that the DMP_EOLSR algorithm has good performances on parameters of packet delivery ratio ， , loads of route, and end-to-end delay. It effectively reduces the number of the interrupted network nodes and links, and can improve obviously the stabilities and transmitting efficiency of parallel paths.

An Investigation on the Effect of Migration Strategy on Parallel GA-Based Shortest Path Routing Algorithm

Genetic algorithm (GA) is one of the alternative approaches for solving the shortest path routing problem. In previous work, we have developed a coarse-grained parallel GA-based shortest path routing algorithm. With parallel GA, there is a GA operator called migration, where a chromosome is taken from one sub-population to replace a chromosome in another sub-population. Which chromosome to be taken and replaced is subjected to the migration strategy used. There are four different migration strategies that can be employed: best replace worst, best replace random, random replace worst, and random replace random. In this paper, we are going to evaluate the effect of different migration strategies on the parallel GA-based routing algorithm that has been developed in the previous work. Theoretically, the migration strategy best replace worst should perform better than the other strategies. However, result from simulation shows that even though the migration strategy best replace worst performs better most of the time, there are situations when one of the other strategies can perform just as well, or sometimes better.

Hydroinformatics advances for operational river forecasting: using graphs for drainage network descriptions

Distributed hydrologic models provide accurate river streamflow forecasts and a multitude of spatially varied products on basin scales. The distributed elements of the basins are pieced together using drainage networks. An efficient representation of drainage networks in computer code is necessary. Graph theory has long been applied in many engineering areas to solve network problems. In this paper we demonstrate that adjacent list graph is the most efficient way of presenting the drainage network in terms of development and execution. The authors have implemented drainage networks using the adjacency-list structure in both the research and operational versions of the US National Weather Service (NWS) distributed model. A parallel routing algorithm based on Dijsktra's shortest path algorithm was also developed using the MPI library, which was tested on a cluster using the Oklahoma Illinois River basin dataset. Theoretical analysis and test results show that inter-processor communication and unbalanced workload among the processors limit the scalability of the parallel algorithm. The parallel algorithm is more applicable to computers with high inter-processor bandwidth, and to basins where the number of grid cells is large and the maximum distance of the grid cells to the outlet is short.

Evaluation of Spatial Parallel Genetic Algorithms for Real Time Routing in Geographic Information System

In this study, two developed shortest path algorithms that run fast on the real large volume road networks have been identified. The first one is heuristic genetic algorithm implemented with approximate buckets in scalar computing environment and the second one is parallel genetic processing which is run in the alternative space. At first, these two algorithms were reviewed and summarized and their data structures and procedures are presented. Continually, in this effort genetic algorithm is used to solve the shortest path problem, because the limitation of traditional optimization methods. Finally, present result demonstrates that parallel heuristic processing can produce better speed up performance for real-time transportation applications. Services

A multipopulation parallel genetic simulated annealing-based QoS routing and wavelength assignment integration algorithm for multicast in optical networks

In this paper, we propose an integrated Quality of Service (QoS) routing algorithm for optical networks. Given a QoS multicast request and the delay interval specified by users, the proposed algorithm can find a flexible-QoS-based cost suboptimal routing tree. The algorithm first constructs the multicast tree based on the multipopulation parallel genetic simulated annealing algorithm, and then assigns wavelengths to the tree based on the wavelength graph. In the algorithm, routing and wavelength assignment are integrated into a single process. For routing, the objective is to find a cost suboptimal multicast tree. For wavelength assignment, the objective is to minimize the delay of the multicast tree, which is achieved by minimizing the number of wavelength conversion. Thus both the cost of multicast tree and the user QoS satisfaction degree can approach the optimal. Our algorithm also considers load balance. Simulation results show that the proposed algorithm is feasible and effective. We also discuss the practical realization mechanisms of the algorithm.

A parallel routing algorithm on recursive cube of rings networks employing Hamiltonian circuit Latin square

Recursive cube of rings (RCR) networks [Y. Sun, P. Cheung, X. Lin, Recursive cube of rings: a new topology for interconnection networks, IEEE Trans. Parallel Dist. Syst. 11 (3) (2000) 275–286] can be widely used in the design and implementation of parallel processing architectures. In this paper, we investigate the routing of a message on RCR networks, that is a key to the performance of this network. We would like to transmit k + 1 packets from a source node to a destination node simultaneously along paths on RCR networks, the ith packet will traverse along the ith path ( 1 ⩽ i ⩽ k + 1 ) . In order for all packets to arrive at a destination node quickly and securely, the ith path must be node-disjoint from all other paths. For construction of these paths, employing Hamiltonian circuit Latin square (HCLS), we present O ( n 2 ) parallel routing algorithm on RCR networks.

A parallel routing algorithm on circulant networks employing the Hamiltonian circuit latin square

Double-loop [J. Bermond, F. Comellas, D. Hsu, Distributed Loop Computer Networks: A Survey, J. Parallel and Distributed Computing, Academic Press, 24 (1995) 2–10] and 2-circulant networks (2-CN) [J. Park, Cycle Embedding of Faulty Recursive Circulants, J. of Korea Info. Sci. Soc. 31 (2) (2004) 86–94] are widely used in the design and implementation of local area networks and parallel processing architectures. In this paper, we investigate the routing of a message on circulant networks, that is a key to the performance of this network. We would like to transmit 2 k packets from a source node to a destination node simultaneously along paths on G( n; ± s 1, ± s 2, … , ± s k ), where the ith packet traverses along the ith path (1 ⩽ i ⩽ 2 k). In order for all packets to arrive at the destination node quickly and securely, the ith path must be node-disjoint from all other paths. For construction of these paths, employing the Hamiltonian circuit latin square (HCLS), a special class of ( n × n) matrices, we present O( n 2) parallel routing algorithm on circulant networks.