Multiprocessor Systems Research Articles

Adaptive Switching Redundant-Mode Multi-Core System for Photovoltaic Power Generation

As maximum power point tracking (MPPT) algorithms have developed towards multi-task intelligent computing, processors in photovoltaic power generation control systems must be capable of achieving a higher performance. However, the challenges posed by the complex environment of photovoltaic fields with regard to processor reliability cannot be overlooked. To address these issues, we proposed a novel approach. Our approach uses error rate and performance as switching metrics and performs joint statistics to achieve efficient adaptive switching. Based on this, our work designed a redundancy-mode switchable three-core processor system to balance performance and reliability. Additionally, by analyzing the relationship between performance and reliability, we proposed optimization methods to improve reliability while ensuring a high performance was maintained. Finally, we designed an error injection method and verified the system’s reliability by analyzing the error rate probability model in different scenarios. The results of the analysis show that compared with the traditional MPPT controller, the redundancy mode switchable multi-core processor system proposed in this paper exhibits a reliability approximately 5.58 times that of a non-fault-tolerant system. Furthermore, leveraging the feature of module switching, the system’s performance has been enhanced by 26% compared to a highly reliable triple modular redundancy systems, significantly improving the system’s reliability while ensuring a good performance is maintained.

Reliability Assessment of Multiprocessor System Based on Exchanged Crossed Cube Networks

ABSTRACTWith the increasingly widespread application of multiprocessor systems, some processors in multiprocessor systems are inevitably prone to malfunctions. The reliability and effectiveness of the system are key issues. As a standard for measuring system fault tolerance, connectivity, and edge connectivity have many drawbacks. Therefore, Haray proposed conditional connectivity by restricting the connected components in disconnected subgraphs to satisfy certain properties, where and represent the interconnection network and its set of faulty vertices, respectively. Restricted connectivity is a special type of conditional connectivity. Exchanged crossed cube, as a deformation of hypercube, has more favorable properties, such as smaller diameter, smaller link size, and lower cost. We prove that the 2‐restricted connectivity of the exchanged crossed cubes is for .

Double declined subnetwork reliability analysis in bubble-sort networks under node fault model

The n-dimensional bubble-sort network Bn is a competitive interconnection network that could be used to construct large-scale multiprocessor computer systems. Let p be the reliability of each node in Bn and let Rn,n−2(p) be the Bn−2-subnetwork reliability (i.e., double declined subnetwork reliability) in Bn under the equiprobability node fault model. In this paper, the bounds on Rn,n−2(p) are derived for n≥4, and an algorithm is given to further verify the accuracy of the lower and upper bounds. The MTTFs that maintain the healthy state of different numbers of disjoint Bn−2's in Bn under different partition patterns are calculated. Simulations are also carried out to verify the MTTFs. Both the theoretical result and the simulating result show that using the flexible partition pattern will make the network more reliable in the sense of double declined subnetwork availability.

Fault diagnosability of (K 4 – e)-free multiprocessor systems under the PMC and HPMC model

Faulty diagnosability of multiprocessor systems is one of the important evaluating index in the design and maintenance of multiprocessor systems. To address the fault diagnosis problem in processor fault or hybrid fault circumstances the Preparata, Metze and Chien (PMC) model and the hybrid PMC (HPMC) model have been proposed. In this paper, we discuss the t-diagnosability of (K 4 − e)-free multiprocessor systems under the PMC model, the h-restricted vertex diagnosability and the r-restricted edge diagnosability under the HPMC model. Furthermore, we determine the h-restricted vertex diagnosability and the r-restricted edge diagnosability of somewell-known networks under the HPMC model.

Enabling high reliability via matroidal connectivity and conditional matroidal connectivity on arrangement graph networks

Connectivity indicators are commonly used to evaluate system fault tolerance and reliability. However, with the high demand for multi-processor systems in high-performance computing and data center networks, the number of processors is getting larger, and the network is getting more complex. Thus, traditional connectivity and other indicators are hardly competent in assessing the reliability of complex networks. The matroidal connectivity and conditional matroidal connectivity are novel connectivity metrics that measure the actual fault-tolerant capability based on the constraints of each network dimension. In this paper, we study matroidal connectivity and conditional matroidal connectivity of the (n,k)-arrangement graph network An,k from the natural perspective of the partition of edge dimension and obtain their theoretically accurate values. Moreover, we conduct numerical analysis to compare matroidal connectivity with other conditional edge connectivities in An,k. Additionally, we explore the distribution pattern of edge failure through simulation experiments in An,k and attain the relation of conditional matroidal connectivity related to network scales. Our investigations include two famous network classes: alternating group graphs and star graphs.

Connectivity and diagnosability of the complete Josephus cube networks under h-extra fault-tolerant model

The h-extra connectivity and the h-extra diagnosability are key parameters for evaluating the reliability and fault-tolerance of the interconnection networks of the multiprocessor systems, and play an important role in designing and maintaining interconnection networks. Recently, various self-diagnostic models have emerged to assess the fault-tolerance in interconnection networks. These interconnection networks are typically expressed by a connected graph G(V,E). For a non-complete graph G and h≥0, the h-extra cut signifies a vertex subset R of G, whose removal results in G−R disconnected, with each remaining component containing at least h+1 vertices. And the h-extra connectivity of G is defined as the minimum cardinality of all h-extra cuts of G. The h-extra diagnosability for a graph G denotes the maximum number of detectable faulty vertices when focusing on these h-extra faulty sets only. The complete Josephus cube CJCn, a variant of Qn, exhibits superior properties compared to hypercube Qn, and also boasts higher connectivity. In this study, with the help of the exact value of the h-extra connectivity of CJCn, the explicit expression of h-extra diagnosability of CJCn under both the PMC model for n≥5 and 1≤h≤⌊n−32⌋ and the MM* model for n≥5 and 2≤h≤⌊n−32⌋ are identified to share the same value (h+1)n−(h−12)+1.

Comparing in silico flowsheet optimization strategies in biopharmaceutical downstream processes.

The challenging task of designing biopharmaceutical downstream processes is initially to select the type of unit operations, followed by optimizing their operating conditions. For complex flowsheet optimizations, the strategy becomes crucial in terms of duration and outcome. In this study, we compared three optimization strategies, namely, simultaneous, top-to-bottom, and superstructure decomposition. Moreover, all strategies were evaluated by either using chromatographic Mechanistic Models (MMs) or Artificial Neural Networks (ANNs). An overall evaluation of 39 flowsheets was performed, including a buffer-exchange step between the chromatography operations. All strategies identified orthogonal structures to be optimal, and the weighted overall performance values were generally consistent between the MMs and ANNs. In terms of time-efficiency, the decomposition method with MMs stands out when utilizing multiple cores on a multiprocessing system for simulations. This study analyses the influence of different optimization strategies on flowsheet optimization and advices on suitable strategies and modeling techniques for specific scenarios.

Method of determining timing parameters of real time systems

Real-time systems are widely used and actively implemented in advanced developments across many industries, from medicine to aerospace. Research and modelling of real-time systems are crucial tasks at the design stage, as they help in the determination of whether the system being modelled meets the specified timing characteristics and, accordingly, assess the system's ability to satisfy timing requirements. After all, the success of a real-time system depends not only on their logical correctness but also on the time it takes for the system to generate a result. Considering the various types of tasks, such as synchronous and asynchronous, parallel and sequential, determining their timing characteristics at the design stage is quite a complex problem. It is also essential to consider the sequence of tasks and their arrival times since there are cases where one task depends on the result of another task, and thus, the arrival time of a new task to the scheduler's queue depends on the completion time of the previous task. Previous studies have investigated methods for evaluating the timing characteristics of tasks in real-time systems by analyzing data obtained from modeling the distribution of processor time among tasks according to selected scheduler algorithms using Petri net models in both single-processor and multi-processor systems. These methods ensured the acquisition of task timing characteristics when choosing a specific type of processor and scheduler, which is necessary for the initial technical design of a real-time system. However, the methods have not considered the dynamic nature of task yielding, which is an essential component of modern real-time systems. This paper proposes a method for determining the timing characteristics of real-time systems at the design stage. The proposed method helps to identify the arrival time of tasks, taking into account various types of tasks and their dependencies. The identified timing characteristics can subsequently be used for modelling the system's operation and determining the optimal task scheduling algorithm.

Graph-logical models for (n, f, k) – and consecutive - k-out-of-n – systems

The article is devoted to methods of constructing graph-logical models of fault-tolerant multiprocessor systems. In particular, systems of the type (n, f, k), linear consecutive-k-out-of-n and circular consecutive-k-out-of-n are considered, which are characterized by the failure of the system when a certain number of consecutive processors fail. Graph-logical models can be used to estimate the reliability parameters of fault-tolerant multiprocessor systems by conducting statistical experiments with models of their behavior in the failure flow. The graph-logical models under construction are based on the basic models with a minimum of lost edges. It is determined that to build a graph-logical model of systems of this type, it is sufficient to calculate the maximum possible number of failed processors at which the system remains in operation. A graph-logical model of a basic system that can handle this number of failures is built, without taking into account the sequence of these failures. The next step is to identify all possible consecutive failures that cause the system to fail. Then, the base model is modified in such a way as to reflect the failure of the system when consecutive failures occur. This means weakening the base model on the previously determined vectors. The proposed methods of model construction can be used both for linear and circular consecutive-k-out-of-n systems and for (n, f, k) systems. A minor difference will be in the calculation of some parameters. The paper describes the calculation of such parameters as the maximum allowable number of failures at which the system remains in an operational state, as well as the calculation of the number of all combinations of consecutive failures at which the system fails. Experiments have been conducted to confirm the model's compliance with the system's behavior in the failure flow. Examples are given to demonstrate the process of building graph-logical models for linear consecutive-k-out-of-n, circular consecutive-k-out-of-n and (n, f, k) systems using the proposed methods.

The method of constructing a GL-model for a consecutive k-out-of-n system

The paper is devoted to the method of constructing GL-models of the behavior of multiprocessor systems in a failure flow, in particular, consecutive k-out-of-n systems are considered, whose main characteristic is the failure of the system when a certain number of processors connected consecutively fail. The GL-models under construction are based on the basic models with a minimum number of lost edges. It has been determined that to build a GL-model of systems of this type, it is sufficient to calculate the maximum possible number of failed processors at which the system remains operational. A GL-model of a system that can handle this number of failures is built without considering the consecutive failures. The next step is to determine all possible consecutive failures that cause the system to fail, and the model is modified to reflect the system failure when consecutive failures occur. The paper describes a method for calculating the maximum allowable number of failures at which the system remains operational. An example of building GL-models for consecutive k-out-of-n systems is given.

Non-inclusive g-extra diagnosability of interconnection networks under PMC model

System level fault diagnosis theory is of great weight in the design and maintenance of multiprocessor systems. In this paper, we propose a novel kind of diagnosability, called non-inclusive g-extra diagnosability, that requires all faulty sets to be non-inclusive and every connected fault-free subgraph has at least g+1 vertices. Furthermore, we determine the non-inclusive g-extra diagnosability of a class of graphs under PMC model. As applications, the non-inclusive g-extra diagnosability of (n,k)-star graph Sn,k, data center networks DCell (Dk,n), BCDC (Bn) and BCube (BCn,k) under PMC model are determined successively.

Metasurface Enabled Multi‐Target and Multi‐Wavelength Diffraction Neural Networks

AbstractBenefiting from low power consumption and high processing speed, there is a growing interest in diffraction neural networks (DNNs), which are typically showcased with 3D printing devices, leading to large volumes, high costs, and low levels of integration. Metasurfaces can desirably manipulate wavefronts of electromagnetic waves, providing a compact platform for mimicking DNNs with novel functions. Although multi‐wavelength and multi‐target recognition provides a richer and more detailed understanding of complex environments, existing architectures are primarily trained to classify a single target at a specific wavelength. A metasurface approach is proposed to design multiplexed DNNs that can classify multiple targets and spatial sequences across various wavelengths in multiple channels. To realize multi‐task processing, the dielectric metasurface is designed based on phase and wavelength multiplexing, which can integrate multi‐target DNNs with different tasks such as operating at distinct wavelengths and classifying diverse targets. The efficacy of this method is exemplified through the numerical simulation and experimental demonstration of recognizing a single target with two wavelengths, two targets at a single wavelength, and two targets at dual wavelengths. This compact metasurface approach enables the design of multi‐target and multi‐wavelength DNNs, opening a new window to develop massively parallel processing and versatile artificial intelligence systems.

Application of Cache Coherence Protocols in Enhancing Pharmacy Management Systems

The complexity of modern pharmacy management systems mirrors challenges faced in distributed computing, particularly in ensuring data consistency across multiple locations and systems. Cache coherence protocols, widely used in computer science to manage data consistency in multiprocessor systems, offer a valuable framework for addressing similar issues in pharmacy management. This paper explores the application of cache coherence protocols to pharmacy systems, proposing a model that enhances the accuracy, reliability, and efficiency of pharmacy operations, particularly in multi-location and online pharmacy environments

A review of the design and research of asynchronous FIFOs

Asynchronous FIFO (First In First Out) is a hardware structure for data transfer across clock domains. It is very important in the design of digital systems, especially when data needs to be exchanged between different modules or subsystems. The main function of an asynchronous FIFO is to solve the data transfer problem due to the unsynchronization of the clock domain, so as to ensure the integrity of the data and the stability of the system. Asynchronous FIFO is widely used in such fields as data acquisition systems, communication systems, and multiprocessor systems. It ensures the stability of data transmission between different modules and the overall system performance through reliable clock domain synchronization and effective read/write management. This paper provides a comprehensive review and analysis of the design principles, implementation methods, and applications of asynchronous FIFO memory. By examining the foundational concepts, various design techniques, and practical applications, this paper aims to offer valuable reference and guidance for digital system designers.

Broadband mode exchanger based on subwavelength Y-junctions.

Multimode silicon photonics, leveraging mode-division multiplexing technologies, offers significant potential to increase capacity of large-scale multiprocessing systems for on-chip optical interconnects. These technologies have implications not only for telecom and datacom applications, but also for cutting-edge fields such as quantum and nonlinear photonics. Thus, the development of compact, low-loss and low-crosstalk multimode devices, in particular mode exchangers, is crucial for effective on-chip mode manipulation. This work introduces a novel mode exchanger that exploits the properties of subwavelength grating metamaterials and symmetric Y-junctions, achieving low losses and crosstalk over a broad bandwidth and a compact size of only 6.5 µm × 2.6 µm. The integration of SWG nanostructures in our design enables precise control of mode exchange through different propagation constants in the arms and metamaterial, and takes advantage of dispersion engineering to broaden the operating bandwidth. Experimental characterization demonstrates, to the best of our knowledge, the broadest operational bandwidth covering from 1,420 nm to 1,620 nm, with measured losses as low as 0.5 dB and extinction ratios higher than 10 dB. Enhanced performance is achieved within a 149 nm bandwidth (1,471-1,620 nm), showing measured losses below 0.4 dB and extinction ratios greater than 18 dB.

Intelligent optimization for multiprocessor systems: hybrid algorithmic strategies for scheduling and load balancing

Intelligent optimization for multiprocessor systems: hybrid algorithmic strategies for scheduling and load balancing

Multi‐objective GA to schedule task graphs on heterogeneous voltage frequency islands

SummaryEnergy consumption of multiprocessor's system is increasing day by day. The capability of multiprocessor systems and high compute‐intensive tasks play a major role in increasing energy consumption. Voltage frequency island (VFI) architecture partitioned the cores into groups for which voltage/frequency can be controlled by a single switch. VFI plays a major role in optimizing the energy consumption. We have generated the initial population by using the slot technique to VFI architecture. The genetic algorithm studied by many researchers to solve scheduling problems. So we combined the genetic algorithm with the VFI‐enabled architecture and slot approach called VFIGen. Then apply the VFIGen algorithm to optimize the energy consumption. When comparing the results of the proposed one with the existing state‐of‐art we achieved the performance gain by to .

Neuro-Optimal Event-Triggered Impulsive Control for Stochastic Systems via ADP.

This article presents a novel neural-network-based optimal event-triggered impulsive control method. First, a novel general-event-based impulsive transition matrix (GITM) is constructed to represent the probability distribution evolving characteristics regarding all system states across the impulsive actions, rather than the prefixed timing sequence. On the foundation of this GITM, the event-triggered impulsive adaptive dynamic programming (ETIADP) algorithm and its high-efficiency version (HEIADP) are developed to deal with the optimization problems for stochastic systems with event-triggered impulsive controls. It is shown that the obtained controller design scheme can reduce the computational and communication burden caused by updating the controller periodically. By analyzing the admissibility, monotonicity, and optimality properties of ETIADP and HEIADP, we further establish the approximation error bound of the neural networks to address the connection between the ideal and neural-network-based realizations of the present methods. It is proven that the iterative value functions of both the ETIADP and HEIADP algorithms fall in a small neighborhood of the optimum as the iteration index increases to infinity. By adopting a novel task synchronization mechanism, the proposed HEIADP algorithm fully utilizes the computing resources of multiprocessor systems (MPSs), while significantly reducing the memory requirement compared to traditional ADP approaches. Finally, we carry out a numerical study to show that the proposed methods can fulfill the desired goals.

MP-ORAM: A Novel ORAM Design for Multicore Processor Systems

MP-ORAM: A Novel ORAM Design for Multicore Processor Systems

Proactive Load Balancing to Reduce Unnecessary Thread Migrations on Chip Multi-Processor (CMP) Systems

Proactive Load Balancing to Reduce Unnecessary Thread Migrations on Chip Multi-Processor (CMP) Systems