Parallel Coordinate Rotation Digital Computer Research Articles

Design and Implementation of Digital Down Converter for WiFi Network

This paper introduces a field-programmable gate array (FPGA)-based digital down converter (DDC) processing a sampling frequency of about 3.64 GHz to a down-converted frequency of 28.4375 MHz to match the IEEE 802.11ah Wi-Fi HaLow standard. The proposed DDC uses a polyphase mixer(PM) and a resampling filter. The PM adopts parallel coordinate rotation digital computer (CORDIC) processors and lowpass filter arrays to reduce high-speed data rates with minimum resource utilization. Again, the resampling filter employs a cascaded integrator comb (CIC) filter associated with a parallel prefixed adder (PPA) and a multi-channel systolic finite impulse response (FIR) filter implemented with canonical expression, attaining optimum hardware cost. Converting floating-point to fixed-point data types provides significant resource savings. Finally, the improved design is coded in the Xilinx Vivado synthesis tool and successfully tested on the FPGA Kintex-7 device. In contrast to other recent architectures, the proposed design substantially reduces area requirements and power utilization. The Matlab tool verifies the design to achieve an acceptable spurious-free dynamic range (SFDR) of 115 dB.

Design and Implementation of Smart Multi-Touch Interface Using Special Purpose CORDIC Processor

This paper presents a smart and embedded multi-touch system for consumer electronics. The infrared (IR) camera is utilized to capture the coordinate of the IR blob from IR stylus or human finger in an emitted IR field. This system allows the consumer to easily convert large surface, projector screen, or conference table into multi-touch interface. The keystone distortion of IR camera is compensated by using homography. To improve the user experience, the calibration of homography is automatically triggered by accelerometer sensor. The special purpose (SP) processor with the parallel COordinate Rotation Digital Computer (CORDIC) architecture computes the observation-to-track association, and the computation result updates the motion status of each tracked trajectory. These motion data support the multi-touch tracking system to evaluate the sliding window of each tracked trajectory for reducing the tracking error. Additionally, the motion data are reused by the adaptive trajectory estimation (TE) system to smooth the touch trajectory and mitigate the measurement noise. This research presents multiple autonomous functions to provide a user-friendly multi-touch interface for consumer electronics. These include the automatic calibration system, the multi-touch tracking architecture with motion estimation system, and the adaptive TE system.

Algorithm and Design of a Fully Parallel Approximate Coordinate Rotation Digital Computer (CORDIC)

This paper proposes a new approximate scheme for coordinate rotation digital computer (CORDIC) design. This scheme is based on modifying the existing Para-CORDIC architecture with an approximation that is inserted in multiple parts and made possible by relaxing the CORDIC algorithm itself. A fully parallel approximate CORDIC (FPAX-CORDIC) scheme is proposed. This scheme avoids the memory register of Para-CORDIC and makes the generation of the rotation direction fully parallel. A comprehensive analysis and the evaluation of the error introduced by the approximation together with different circuit-related metrics are pursued using HSPICE as the simulation tool. This error analysis also combines existing figures of merit for approximate computing (such as the Mean Error Distance (MED) and MED Power Product (MPP)) with CORDIC specific parameters. It is shown that a good agreement between expected and simulated error values is found. The Discrete Cosine Transformation (DCT) and the Inverse DCT (IDCT) transformations as case study of approximate computing to image processing are investigated by utilizing the proposed approximate FPAX-CORDIC architecture with different accuracy requirements. The results confirm the viability of the proposed scheme.

VLSI architecture for parallel radix-4 CORDIC

COordinate Rotation DIgital Computer (CORDIC) algorithm is an iterative method for fast hardware implementation of the elementary functions such as trigonometric, inverse trigonometric, logarithm, exponential, multiplication and division functions in a simple and elegant way. This paper presents a regular and scalable VLSI architecture for the implementation of parallel radix-4 rotational CORDIC algorithm. Thorough comparison of the proposed architecture with the available architectures has been carried out to show the latency and the hardware improvement. Furthermore, the proposed architecture is coded for 16-bit precision using the VHDL language. The functionally simulated net list has been synthesized with 90nm CMOS technology library and the area-time measures are provided. This architecture is also implemented using Xilinx ISE7.1i software and a Virtex device.

Low Latency Angle Recoding Methods for the Higher Bit-Width Parallel CORDIC Rotator Implementations

In this paper, a low latency angle recoding method for the higher bit-width parallel coordinate rotation digital computer (CORDIC) rotator implementations is proposed. In previous studies, parallel CORDIC (para-CORDIC) rotators have been used to reduce the computational bottleneck by precomputing the required rotation directions. However, the number of required microrotations increases with the bit-width of the input angle, leading to extra stages compared to the conventional CORDIC. To overcome this, our proposed method can obtain a reduced number of microrotations for larger bit-width implementations by recoding two bits of the input angle in the first few area-consuming stages concurrently. This leads to above 21% area/delay reduction compared to previously reported 64-bit para-CORDIC methods. We have implemented our proposed 64-bit para-CORDIC rotator implementations using 0.13- mum CMOS technology, and the operating speed can achieve 250 MHz.

A programmable CORDIC chip for digital signal processing applications

A chip implementing the coordinate rotation digital computer (CORDIC) algorithm is described. It contains a 10-MHz 16-b fixed-point CORDIC arithmetic unit, 2-kb RAM, a controller, and input/output (I/O) registers. A modified data-path architecture allows cross-wire free data flow. The chip design involved development of optimized carry-select adders and a modified programmable-logic-array (PLA) cell layout, which allows speed increase in single-layer metal technology. The authors designed, fabricated, and tested a general-purpose fully parallel programmable CORDIC chip in CMOS technology and developed optimal iteration sequences. >