Page Replacement Policy Research Articles

L2LRU: LRU 페이지 교체 기법을 위한 러닝 기반 페이지 이동 정책

페이지 캐시 교체 정책 중 하나인 LRU는 재접근이 발생하는 페이지를 리스트의 앞(Head) 위치로 이동시킴으로써 캐시 적중률을 높인다. 그러나, LRU의 페이지 이동은 락-언락 명령어를 호출함으로써 시스템의 대기 상태를 유발한다. 이에, 본 논문에서는 딥 러닝을 이용하여 페이지의 재접근 거리를 학습하고 재접근이 발생하는 경우, LRU 리스트 페이지에 대한 이동 유무를 판단하는 L2LRU(Learning-based Lock-free LRU) 기법을 새롭게 제안한다. 특히, L2LRU는 기존 LRU 교체 기법과 다르게 페이지를 재접근 될 가능성이 높은 위치로 페이지를 이동시킨다. 제안 기법을 평가하기 위해, 우리는 트레이스 기반 시뮬레이션 방식으로 L2LRU을 구현하였으며, Microsoft Research Cambridge Trace을 실험의 입력으로 사용하였다. 실험 결과 제안한 L2LRU가 LRU 대비 최대 91% 락-언락 명령어 호출을 감소시킬 수 있었다.

Killing Processes or Killing Flash? Escaping from the Dilemma Using Lightweight, Compression-Aware Swap for Mobile Devices

Android apps become increasingly memory-demanding as software vendors add more and more new features to their apps. In the mean time, Android users often launch multiple apps and conveniently switch back and forth among the apps. Although running multiple apps imposes a high pressure on memory management, virtual-memory swap, an essential feature to improve the degree of multitasking, is disabled in fear of premature retirement of flash-based storage devices. Instead, Android employs a termination-based, process-level memory reclaiming method. We observed that process killing is, unfortunately, not effective in memory reclaiming and is highly negative to user experience. In this study, we advocate re-thinking using swap in Android for improved user experience with managed write stress on flash storage. Based on a series of empirical analyses of swap activities, we propose an enhanced page replacement policy and a page-compressing frontswap module. The proposed page replacement policy jointly considers page activeness and compressibility to boost the compression ratio of swap writes. A sampled-based method for page compressibility prediction is introduced so that decisions on page replacement can be made without compressing every page. We also design a frontswap module that strategically organizes compressed pages in the swap space for reducing the overhead of swap I/O operations. Experimental results showed that compared with process killing, our method improved the app launching time and energy consumption by 58% and 19%, respectively; compared with the original swap, our approach reduced the swap write stress by 65%.

TA-CLOCK: Tendency-Aware Page Replacement Policy for Hybrid Main Memory in High-Performance Embedded Systems

Recently, high-performance embedded systems have adopted phase change memory (PCM) as their main memory because PCMs have attractive advantages, such as non-volatility, byte-addressability, high density, and low power consumption. However, PCMs have disadvantages, such as limited write endurance in each cell and high write latency compared to DRAMs. Therefore, researchers have investigated methods for enhancing the limitations of PCMs. In this paper, we propose a page replacement policy called tendency-aware CLOCK (TA-CLOCK) for the hybrid main memory of embedded systems. To improve the limited write endurance of PCMs, TA-CLOCK classifies the page access tendency of the victim page through access pattern analysis and determines the migration location of the victim page. Through the classification of the page access tendency, TA-CLOCK reduces unnecessary page migrations from DRAMs to PCMs. Unnecessary migrations cause an increase in write operations in PCMs and the energy consumption of the hybrid main memory in embedded systems. Thus, our proposed policy improves the limited write endurance of PCMs and enhances the access latency of the hybrid main memory of embedded systems by classifying the page access tendency. We compared the TA-CLOCK with existing page replacement policies to evaluate its performance. In our experiments, TA-CLOCK reduced the number of write operations in PCMs by 71.5% on average, and it enhanced the energy delay product by 38.3% on average compared with other page replacement policies.

An Energy Aware Strategy for Distributed Cache Discovery with Stale Page Reduction

With the immense growth in the field of mobile communication, a good number of complex applications are now available for the mobile devices. The complex applications are made available to comply with the client demand for the higher performing and higher capable applications, which can be accessible from any locations and any devices. Thus, the application developers have attempted to make highly scaled applications to be deployed on mobile communication devices. The larger applications have higher demand for memory and processing capabilities. Thus, making the similar infrastructure available on the mobile computing environments was always a challenge. Nonetheless, with the availability of distributed computing architecture, the bottleneck for the computing capabilities for these complex applications can be handled. Nonetheless, the memory capabilities for the applications must be addressed more sophisticated manner using distribution of the memory and sharing of the data. Henceforth, distributed caching came under existence.A conveyed cache is an augmentation of the customary idea of cache utilized in a solitary district. A conveyed cache may traverse various servers with the goal that it can develop in size and in value-based limit. It is for the most part used to store application information living in database and web session information.One of the most popular technique for making the cache available is to perform cache discovery operations in the network. A number of parallel research attempts are made to identify the accurate place in the network to create or build the distributed cache network.However, the most of the parallel research attempts are criticised for considering single dimensions for cache discovery as few of the work focuses on distance, few of the work focuses on density and some of the works focuses on page replacement policies applicable on mobile computing environments as MANETs or WSN. Henceforth, the demand of the research is to consider multiple parameters for cache discovery and build a framework to automatically define the cache distribution. Hence, this work proposes a novel architecture or framework to detect the cache distribution based on distance, stale page reduction mechanism and finally the energy optimization. The outcome of the research is to automate the recommendation of cache discovery and increase the network life time by 90% compared to the existing methods for cache discovery. In order to handle the complex processing of the proposed algorithms, this work deploys machine learning methods to reduce the time complexity.

The MT Stack: Paging Algorithm and Performance in a Distributed Virtual Memory System


 
 
 Advances in parallel computation are of central importance to Artificial Intelligence due to the significant amount of time and space their pro- grams require. Functional languages have been identified as providing a clear and concise way of programming parallel machines for artificial intelligence tasks. The problems of exporting, creating, and manipulating processes have been thoroughly studied in relation to the paralleliza- tion of functional languages, but none of the necessary support structures needed for the ab- straction, like a distributed memory, have been properly designed. In order to design and im- plement parallel functional languages efficiently, we propose the development of an all-software based distributed virtual memory system de- signed specifically for the memory demands of a functional language. In this paper, we review the MT architecture and briefly survey the related literature that lead to its development. We then present empirical results obtained from observ- ing the paging behavior of the MT stack. Our empirical results suggest that LRU is superior to FIFO as a page replacement policy for MT stack pages. We present a proof that LRU is an opti- ?Partially supported by the Seton Hall University Re- search Council. †Partially supported by NSF grant CDA-9114481. ‡Partially supported by NSF grant HRD-9703600. mal page replacement policy. Based on this proof the MT stack page replacement policy was de- veloped and implemented. We outline the paging algorithm and present an argument of partial cor- rectness. The MT stack page replacement policy is superior to LRU, because it does not incur the expensive time penalties associated with imple- menting LRU in software.
 
 

Adaptive-Classification CLOCK: Page replacement policy based on read/write access pattern for hybrid DRAM and PCM main memory

Phase change memory (PCM) has emerged as a new main memory in embedded systems because of its attractive characteristics, which include a lower static power, higher density, byte-addressability, and non-volatility. Although PCM has various advantages, it has a longer write latency than dynamic random access memory (DRAM) and limits the write endurance in each cell. Recently, a hybrid main memory was designed that combined DRAM and PCM. In particular, the page replacement policy in this hybrid main memory has been one of the major areas of study. The previous page replacement policies had three problems when used in embedded systems: the allocation policy, read/write access pattern identification, and migration policy. This paper proposes the adaptive-classification CLOCK (AC-CLOCK) page replacement policy for the hybrid main memory of an embedded system. AC-CLOCK measures the read/write access patterns of application programs and reduces the number of write operations in PCM by tracing these patterns. In addition, it reduces the number of unnecessary page migrations from PCM to DRAM by tracking the detailed access patterns such as write intensive pages or read intensive pages. In our experiments, AC-CLOCK reduced the number of write operations in PCM by 57.87% on average and outperformed the hit ratio of write operations in the DRAM by 9.47% on average, compared with CLOCK, CLOCK-Pro, and CLOCK-DWF. Moreover, AC-CLOCK reduced the energy delay product (EDP) by 23.25% on average, compared with the previous techniques.

A Working-set Sensitive Page Replacement Policy for PCM-based Swap Systems

Due to the recent advances in Phage-Change Memory (PCM) technologies, a new memory hierarchy of computer systems with PCM is expected to appear. In this paper, we present a new page replacement policy that adopts PCM as a high speed swap device. As PCM has limited write endurance, our goal is to minimize the amount of data written to PCM. To do so, we defer the eviction of dirty pages in proportion to their dirtiness. However, excessive preservation of dirty pages in memory may deteriorate the page fault rate, especially when the memory capacity is not enough to accommodate full working-set pages. Thus, our policy monitors the current working-set size of the system, and controls the deferring level of dirty pages not to degrade the system performances. Simulation experiments show that the proposed policy reduces the write traffic to PCM by 160% without performance degradations.

General Caching Is Hard: Even with Small Pages

Caching (also known as paging) is a classical problem concerning page replacement policies in two-level memory systems. General caching is the variant with pages of different sizes and fault costs. The strong NP-hardness of its two important cases, the fault model (each page has unit fault cost) and the bit model (each page has the same fault cost as size) has been established, but under the assumption that there are pages as large as half of the cache size. We prove that this already holds when page sizes are bounded by a small constant: The bit and fault models are strongly NP-complete even when page sizes are limited to $$\{1, 2, 3\}$$ . Considering only the decision versions of the problems, general caching is equivalent to the unsplittable flow on a path problem and therefore our results also improve the hardness results about this problem.

PCM 기반 스왑 장치를 위한 클럭 기반 최소 쓰기 우선 교체 정책

본 논문은 PCM을 가상메모리 스왑 장치로 사용하는 시스템을 위한 새로운 페이지 교체 기법을 제안한다. 제안하는 기법은 메모리 내의 각 페이지에 대한 수정 정도를 고려해서 교체 대상 페이지를 선정하며 이를 통해 PCM에 발생시키는 쓰기량을 줄인다. 즉, 제안하는 기법은 페이지의 수정 정도를 서브페이지 단위로 관리하고 최근에 사용되지 않은 페이지 중 수정된 서브페이지의 수가 최소인 페이지를 교체한다. 트레이스를 이용한 재현 실험을 통해 제안한 기법이 기존 CLOCK 알고리즘 대비 평균 22.9% 최대 73.7%의 PCM 쓰기량을 절감함을 확인하였다. 또한 PCM의 수명과 에너지 소모율을 각각 평균 49.0%와 3.0% 개선함을 보였다.

LDF-CLOCK: The Least-Dirty-First CLOCK Replacement Policy for PCM-based Swap Devices

Phase-change memory (PCM) is a promising technology that is anticipated to be used in the memory hierarchy of future computer systems. However, its access time is relatively slower than DRAM and it has limited endurance cycle. Due to this reason, PCM is being considered as a high-speed storage medium (like swap device) or long-latency memory. In this paper, we adopt PCM as a virtual memory swap device and present a new page replacement policy that considers the characteristics of PCM. Specifically, we aim to reduce the write traffic to PCM by considering the dirtiness of pages when making a replacement decision. The proposed replacement policy tracks the dirtiness of a page at the granularity of a sub-page and replaces the least dirty page among pages not recently used. Experimental results with various workloads show that the proposed policy reduces the amount of data written to PCM by 22.9% on average and up to 73.7% compared to CLOCK. It also extends the lifespan of PCM by 49.0% and reduces the energy consumption of PCM by 3.0% on average.

Comparison of Cache Page Replacement Techniques to Enhance Cache Memory Performance

Caching is a very important technique for improving the computer system performance, it employed to hide the latency gap between memory and the CPU by exploiting locality in memory accesses. In modern computer architectures a page miss cause the several hundred CPU cycles [1, 15]. In a memory hierarchy, a cache performs faster than auxiliary storage, but is more expensive. Some important page replacement policies such as FIFO, LRU, RANDOM and SECOND CHANCE are used in cache memory to replace the page whenever it is needed. So page replacement policy severely affects the performance of cache memory. So here our purpose is to simulate FIFO, LRU, RANDOM and SECOND CHANCE policies and to compare the results for various applications such as bzip, swim and gcc traces (taken from SPEC2000 benchmark for simulation) etc. using MS-Excel [3, 10, 12] . General terms Computer Architecture, Operating system, cache memory, main memory and Performance evaluation of system

Least Recently Used Page Replacement using Last Use Distance (LRUL)

Virtual memory technique is used in modern OS which permits the execution of a program while it is partially available in memory thus providing an illusion of very large memory to the user and freeing the user from the concern of large program size. This uses a page replacement technique such as first in first out (FIFO), least recently used (LRU), optimal etc. to replace a page in memory when a frame is needed and no free frame is available in memory. Here page replacement policy severely affects the performance of virtual memory. It has been observed that LRU approximates optimal so LRU and its variants are quite common in use in operating system as a reasonable choice of page replacement algorithm. But LRU performs very poor by generating continuous page faults while accessing looping pattern if all the pages does not fit in the memory simultaneously. This paper presents a simple modified LRU algorithm called LRUL overcoming this problem using the concept of last use distance (LUD). It is observed that the new algorithm gives better results than LRU. General Terms Operating system, page replacement algorithm.

Recency and Prior Probability (RPP) based Page Replacement Policy to Cope with Weak Locality Workloads having Probabilistic Pattern

Development of efficient block replacement policy is the topic of much research in operating system as well as database management systems. Among variety of page replacement algorithms Least Recently Used (LRU) algorithm is simple, flexible and has low overhead. LRU replaces page that is not accessed for longest time. But LRU makes bold assumption on recency factor only, which made LRU misbehave with weak locality workloads. This paper proposes a new Recency and Prior Probability (RPP) based page replacement policy for block replacement. The RPP combines recency and prior probability associated with the pages while selecting the victim frame from memory. If a page, to be used, has probability n times higher than another page, the page will get log(n) more chances to stay in the memory than lower probability pages. Hence with RPP, it is possible to prevent pages having higher probability of use from being replaced General Terms: Page Replacement, Memory Management, Operating System

Analysis of Page Replacement Policies in the Fluid Limit

The performance of storage systems and database systems depends significantly on the page replacement policies. Although many page replacement policies have been discussed in the literature, their performances are not fully understood. We introduce analytical techniques for evaluating the performances of page replacement policies including two queue (2Q), which manages two buffers to capture both the recency and frequency of requests. We derive an exact expression for the probability that a requested item is found (the hit probability) in a buffer managed by 2Q in the fluid limit, where the number of items is scaled by n, the size of items is scaled by 1/n, and n approaches infinity. The hit probability in the fluid limit approximates the hit probability in the original system, and we find that the relative error in the approximation is typically within 1%. Our analysis also illuminates several fundamental properties of 2Q useful for system designers.

Multi-buffer manager

Embedded devices such as personal digital assistants (PDAs), pocket PCs, palmtops, and handheld PCs are increasingly using flash memory for the permanent storage of databases. Databases achieve their fast data access speeds by using a memory manager that manages data pages in a memory buffer. The buffer manager uses a page replacement policy to evict pages when the memory buffer is full. An eviction of a dirty page will result in a write to flash memory. Unfortunately, writing to flash memory consumes a lot more energy than reading. Much of the previous work in page replacement policies has focused on reducing the number of page reads rather than writes. One of the few existing works to consider the effects of flash memory's hardware constraints for database design is Lee et. al.'s in-page Logging (IPL) approach [Lee and Moon 2007]. They demonstrated IPL significantly outperforms traditional disk-based databases when running on flash memory. However, they do not consider the energy efficiency of their approach in terms of the behavior of the page replacement policy. This article addresses this issue by presenting the Multi-Buffer Manager, which is customized for flash databases that use a logging-based approach for managing updates such as IPL. Extensive experiments show the page replacement policy used plays a pivotal role in the performance of the flash database system. In particular, our Multi-Buffer Manager can reduce energy consumption by up to 40% compared to the state-of-the-art clean first flash-based buffer replacement policy (CFLRU).

Managing Frequent Updates in R-Trees for Update-Intensive Applications

Managing frequent updates is greatly important in many update-intensive applications, such as location-aware services, sensor networks, and stream databases. In this paper, we present an R-tree-based index structure (called Rsb-tree, R-tree with semibulk loading) for efficiently managing frequent updates from massive moving objects. The concept of semibulk loading is exploiting a small in-memory buffer to defer, buffer, and group the incoming updates and bulk-insert these updates simultaneously. With a reasonable memory overhead (typically only 1 percent of the whole data set), the proposed approach far outperforms the previous works in terms of update and query performance as well in a realistic environment. In order to further increase buffer hit ratio for the proposed approach, a new page-replacement policy that exploits the level of buffered node is proposed. Furthermore, we introduce the concept of deferring threshold ratio (dtr) that simply enables deferring CPU- and I/O-intensive operations such as node splits and removals. Extensive experimental evaluation reveals that the proposed approach is far more efficient than previous approaches for managing frequent updates under various settings.

A page fault equation for modeling the effect of memory size

Modeling the effect of memory size on page faults is very difficult, because they are the result of the interaction between process reference behavior and page replacement policy. Moreover, a change in memory size will alter the timing and pattern of references in a multiprogramming mix. This paper presents an equation to model how memory size affects page faults. The equation is derived with the help of a conjectured invariant on the interaction between reference behavior and replacement policy. The page fault equation is validated in several experiments with real applications and systems. The equation can be used for energy conservation and capacity planning, characterizing the memory requirement of software and managing memory allocation, modeling of processor cache misses and database buffer management.

Token-ordered LRU: an effective page replacement policy and its implementation in Linux systems

Most computer systems use a global page replacement policy based on the LRU principle to approximately select a Least Recently Used page for a replacement in the entire user memory space. During execution interactions, a memory page can be marked as LRU even when its program is conducting page faults. We define the LRU pages under such a condition as false LRU pages because these LRU pages are not produced by program memory reference delays, which is inconsistent with the LRU principle. False LRU pages can significantly increase page faults, even cause system thrashing. This poses a more serious risk in a large parallel systems with distributed memories because of the existence of coordination among processes running on individual node. In the case, the process thrashing in a single node or a small number of nodes could severely affect other nodes running coordinating processes, even crash the whole system. In this paper, we focus on how to improve the page replacement algorithm running on one node. After a careful study on characterizing the memory usage and the thrashing behaviors in the multi-programming system using LRU replacement. we propose an LRU replacement alternative, called token-ordered LRU, to eliminate or reduce the unnecessary page faults by effectively ordering and scheduling memory space allocations. Compared with traditional thrashing protection mechanisms such as load control, our policy allows more processes to keep running to support synchronous distributed process computing. We have implemented the token-ordered LRU algorithm in a Linux kernel to show its effectiveness.

Resource policing to support fine-grain cycle stealing in networks of workstations

We present the design, implementation, and performance evaluation of a suite of resource policing mechanisms that allow guest processes to efficiently and unobtrusively exploit otherwise idle workstation resources. Unlike traditional policies that harvest cycles only from unused machines, we employ fine-grained cycle stealing to exploit resources even from machines that have active users. We developed a suite of kernel extensions that enable these policies to operate without significantly impacting host processes: 1) a new starvation-level CPU priority for guest jobs, 2) a new page replacement policy that imposes hard bounds on physical memory usage by guest processes, and 3) a new I/O scheduling mechanism called rate windows that throttle guest processes' usage of I/O and network bandwidth. We evaluate both the individual impacts of each mechanism, and their utility for our fine-grain cycle stealing.

Web-log mining for predictive web caching

Caching is a well-known strategy for improving the performance of Web-based systems. The heart of a caching system is its page replacement policy, which selects the pages to be replaced in a cache when a request arrives. In this paper, we present a Web-log mining method for caching Web objects and use this algorithm to enhance the performance of Web caching systems. In our approach, we develop an n-gram-based prediction algorithm that can predict future Web requests. The prediction model is then used to extend the well-known GDSF caching policy. We empirically show that the system performance is improved using the predictive-caching approach.