Page-level Mapping Research Articles

GFTL: Group-Level Mapping in Flash Translation Layer to Provide Efficient Address Translation for NAND Flash-Based SSDs

NAND flash memory has been widely used as data storage devices in consumer electronics, such as tablet computers and smart phones. Logical-to-physical address translation is important for improving the performance of NAND flash-based SSDs. Even though keeping the mapping table in a DRAM can boost the address translation, it is already infeasible to do this as the capacity of SSDs keeps increasing and only a limited part of DRAM will be used as the mapping cache. Orthogonal to the demand-based page-level FTLs, we develop a novel group-level mapping which divides the whole SSD into multiple equal-size groups. To map a logical-page-number to a physical-page-number, it will be translated into a group number and an offset. The group number can be obtained via calculation, and the offset will be retrieved from a recorded mapping entry which can correspond to any position within a group. Group-level mapping reduces the size of mapping table while obtaining the similar flexibility as the page-level mapping. We also design an effective group-level FTL (GFTL) with a block pool management approach. Our simulations show that GFTL improves the hit ratio of mapping cache and thus reduces the average response time.

Reinforcement learning-driven address mapping and caching for flash-based remote sensing image processing

Abstract Flash memory is featured with salient advantages over conventional hard disks for massive data storage and efficient on-board data processing. A flash translation layer (FTL) is a critical component for flash-based storage devices to handle particular technical constraints of flash. It is desirable to use flash memory for the storage of massive remote sensing images and support on-board remote sensing data processing applications, which typically require high I/O performance and hence call for advanced FTL design and implementations. In this paper, we introduce our efforts in developing a reinforcement learning driven page-level mapping and caching scheme (named Q-FTL) that is adaptive and responsive to ever-changing I/O streams of on-board remote sensing image processing operations. The adaptability and responsiveness are achieved by the separation of large and small I/O requests, an integrated weighting scheme to measure access costs of cached translation pages, and a reinforcement learning driven cache replacement algorithm. We demonstrate the efficiency of the proposed approach using actual I/O traces generated from on-board remote sensing image processing applications. Experimental results show that Q-FTL improves over several current state-of-the-art FTLs by a large margin and even achieves competitive performance close to an idealized pure page mapping FTL in some cases.

An I/O Scheduling Strategy for Embedded Flash Storage Devices With Mapping Cache

NAND flash memory has been the default storage component in embedded systems. One of the key technologies for flash management is the address mapping scheme between logical addresses and physical addresses, which deals with the inability of in-place-updating in flash memory. Demand-based page-level mapping cache is often applied to match the cache size constraint and performance requirement of embedded storage systems. However, recent studies showed that the management overhead of mapping cache schemes is sensitive to the host I/O patterns, especially when the mapping cache is small. This paper presents a novel I/O scheduling scheme, called MAP+, to alleviate this problem. The proposed scheduling approach reorders I/O requests for performance improvement from two angles. Prioritizing the requests that will hit in the mapping cache, and grouping requests with related logical addresses into large batches. Batches of requests are reordered to further optimize request waiting time. Experimental results show that MAP+ improved upon traditional I/O schedulers by 48% and 18% in terms of read and write latencies, respectively.

Balancing Spatial Locality with Parallelism in Solid State Disks

Objectives: Modern flash memory based storage systems, such as Solid State Disks (SSDs), are actively utilizing the channel/way interleaving to exploit parallelism among multiple NAND chips. Methods/Statistical Analysis: However, the flip side of the interleaving is that it disperses data with spatial locality across different NAND blocks, which eventually causes a high garbage collection overhead. To overcome this problem, we propose a spatial locality-aware allocation policy, called SLAP. It uses the notion of stream, which is defined as a set of data having consecutive Logical Page Numbers (LPN). Findings: By allocating a stream into a NAND block separately, it can preserve the spatial locality. In addition, by handling multiple streams simultaneously, it can obtain the parallelism among NAND chips. Also, we discuss that SLAP can balance between locality-preserving and parallelism by providing a spectrum from a traditional parallelism-oriented allocation to a strict locality-preserving one. We have implemented SLAP on a page-level mapping Flash Translation Layer (FTL) that is being used as a default FTL in many commercial SSDs. Improvements/Applications: Trace-driven simulation based experimental results have shown that SLAP can improve performance by up to 35.3% with an average of 13.1%, compared with the traditional allocation policy for the three workload considered.

플래시 변환 계층에서 시간적 지역성을 이용하여 쓰기 요청을 처리하는 효율적인 페이지 레벨 매핑 알고리듬

본 논문에서는 플래시 메모리의 FTL에서 페이지 매핑 기법을 기반으로 소거횟수를 줄이는 알고리듬을 제안한다. 제안된 알고리듬은 버퍼에서 매 쓰기요청들의 가중치들을 유지하고 이용하여 현재 쓰여질 요청의 시간적 지역성의 정도를 판단한다. 시간적 지역성을 효율적으로 이용하여 핫 요청을 판단하기 위해 현재 쓰여질 요청은 실험적으로 정한 기준점보다 높은 시간적 지역성을 가져야 한다. 반면 LRU 알고리듬을 이용한 FTL에서는 새로 쓰여질 요청을 항상 시간적 지역성이 높은 요청으로 판단하여 데이터를 순차적으로 저장하지만 제안된 알고리듬을 사용하여 판단된 핫 요청들의 데이터는 핫 블록에 집중적으로 저장한다. 핫 블록에 저장된 데이터들은 웜 블록의 데이터들보다 자주 업데이트되어 Garbage Collection 수행 시 핫 블록들 중 무효한 페이지가 많은 블록이 주로 희생블록으로 선택되므로 소거연산의 시작을 지연시켜 전체 소거횟수를 줄인다. 임의적인 요청을 위주로 하는 실제 I/O시스템에서 추출한 트레이스 파일들을 적용하여 검증한 결과, 기존의 LRU 알고리듬을 사용하는 경우에 비해 소거횟수는 9.3% 줄어들었다. This paper proposes an efficient page-level mapping algorithm that reduces the erase count in the FTL for flash memory systems. By maintaining the weight for each write request in the request buffer, the proposed algorithm estimates the degree of temporal locality for each incoming write request. To exploit temporal locality deliberately for determination of hot request, the degree of temporal locality should be much higher than the reference point determined experimentally. While previous LRU algorithm treats a new write request to have high temporal locality, the proposed algorithm allows write requests that are estimated to have high temporal locality to access hot blocks to store hot data intensively. The pages are more frequently updated in hot blocks than warm blocks. A hot block that has most of invalid pages is always selected as victim block at Garbage Collection, which results in delayed erase operation and in reduced erase count. Experimental results show that erase count is reduced by 9.3% for real I/O workloads, when compared to the previous LRU algorithm.

Exploiting Sequential and Temporal Localities to Improve Performance of NAND Flash-Based SSDs

NAND flash-based Solid-State Drives (SSDs) are becoming a viable alternative as a secondary storage solution for many computing systems. Since the physical characteristics of NAND flash memory are different from conventional Hard-Disk Drives (HDDs), flash-based SSDs usually employ an intermediate software layer, called a Flash Translation Layer (FTL). The FTL runs several firmware algorithms for logical-to-physical mapping, I/O interleaving, garbage collection, wear-leveling, and so on. These FTL algorithms not only have a great effect on storage performance and lifetime, but also determine hardware cost and data integrity. In general, a hybrid FTL scheme has been widely used in mobile devices because it exhibits high performance and high data integrity at a low hardware cost. Recently, a demand-based FTL based on page-level mapping has been rapidly adopted in high-performance SSDs. The demand-based FTL more effectively exploits the device-level parallelism than the hybrid FTL and requires a small amount of memory by keeping only popular mapping entries in DRAM. Because of this caching mechanism, however, the demand-based FTL is not robust enough for power failures and requires extra reads to fetch missing mapping entries from NAND flash. In this article, we propose a new flash translation layer called LAST++. The proposed LAST++ scheme is based on the hybrid FTL, thus it has the inherent benefits of the hybrid FTL, including low resource requirements, strong robustness for power failures, and high read performance. By effectively exploiting the locality of I/O references, LAST++ increases device-level parallelism and reduces garbage collection overheads. This leads to a great improvement of I/O performance and makes it possible to overcome the limitations of the hybrid FTL. Our experimental results show that LAST++ outperforms the demand-based FTL by 27% for writes and 7% for reads, on average, while offering higher robustness against sudden power failures. LAST++ also improves write performance by 39%, on average, over the existing hybrid FTL.

Correlated Locality Data Distribution Policy for Improving Performance in SSD

In this paper, we propose in this paper present a novel locality data allocation policy as COLD(Correlated Locality Data) allocation policy. COLD is defined as a set of data that will be updated together later. By distributing a COLD into a NAND block separately, it can preserve th locality. In addition, by handling multiple COLD simultaneously, it can obtain the parallelism among NAND chips. We perform two experiment to demonstrate the effectiveness of the COLD data allocation policy. First, we implement COLD detector, and then, analyze a well-known workload. And we confirm the amount of COLD found depending on the size of data constituting the COLD. Secondly, we compared the traditional page-level mapping policy and COLD for garbage collection overhead in actual development board Cosmos OpenSSD. Experimental results have shown that COLD data allocation policy is significantly reduces the garbage collection overhead. Also, we confirmed that garbage collection overhead vary depending on the COLD size.

Clustered page-level mapping for flash memory-based storage devices

Recent consumer devices such as smartphones, smart TVs and tablet PCs adopt NAND flash memory as storage device due to its advantages of small size, reliability, low power consumption, and high performance. The unique characteristics of NAND flash memory require an additional software layer, called flash translation layer (FTL), between traditional file systems and flash memory. In order to reduce the garbage collection cost, FTLs generally try to separate hot and cold data. Previous hot and cold separation techniques monitor the storage access patterns within storage device, or exploit file system hints from host system. This paper proposes a novel clustered page-level mapping, called CPM, which can separate hot and cold data efficiently by allocating different flash memory block groups to different logical address regions. CPM can reduce the FTL map loading overhead during garbage collection and it does not require any high-cost monitoring overhead or host hint. This paper also proposes a K-associative version of CPM, called K-CPM, which allows different logical address regions to share a physical block group in order to achieve high block utilizations. Experimental results show that CPM improves the storage I/O performance by about 54% compared with a previous page-level mapping FTL, and K-CPM further improves the performance by about 19.4% compared with CPM.

Map cache management using dual granularity for mobile storage systems

NAND flash memories have been used in many mobile consumer devices as storage media because they are small, fast, shock-resistant, and energy-efficient. However, the flash storage systems based on these flash devices need a special software layer, the FTL, to translate logical addresses from a host system to physical addresses in NAND flash memories. Recently, the flash storage systems in mobile devices tend to employ a page-level mapping scheme as they are required to yield higher access bandwidth. Unlike common SSDs, which often keep the majority of mapping information in fast but volatile DRAM, the flash storage systems in mobile consumer devices keep only a limited subset of mapping information in a small-sized SRAM due to the restrictions in size, cost, and power consumption. For this reason, many cache management schemes proposed for SSDs may not be suitable for the flash storage systems in mobile consumer devices, though most map cache management schemes used in mobile storage are basically designed for SSD. This paper proposes a novel cache management scheme targeting mobile consumer devices. The proposed scheme uses different management granularities in allocating and evacuating cache space. Experimental results show that the proposed scheme improves map cache performance by up to 36% compared to the existing cache management techniques.

P3Stor: A parallel, durable flash-based SSD for enterprise-scale storage systems

Driven by data-intensive applications, flash-based solid state drives (SSDs) have become increasingly popular in enterprise-scale storage systems. Flash memory exhibits inherent parallelism. However, existing solid state drives have not fully exploited this superiority. We propose P3Stor, a parallel solid state storage architecture that makes full use of flash memory by utilizing module- and bus-level parallelisms to increase average bandwidth and employing chip-level interleaving to hide I/O latency. To improve the bandwidth utilization of traditional interface protocols (e.g., SATA), P3Stor adopts PCI-E interface to support concurrent transactions. Based on the proposed parallel architecture, we design a lazy flash translation layer (LazyFTL) to manage the address space. The proposed LazyFTL adopts flexible super page-level mapping scheme to support multi-level parallelisms. It is able to distinguish hot data from cold data, and hot data identification enables LazyFTL to direct hot and cold data to separate physical blocks, which reduces page migrations when reclaiming blocks. As garbage collector migrates fewer valid pages, write amplification is significantly reduced, which in turn helps to extend the life span. Moreover, LazyFTL rarely triggers wear-leveling process. The lazy wear-leveling mechanism protects users’ requests from being disrupted by background operations. With the guidance of hot data identification, an intelligent write buffer is used to reduce program operations to flash chips. This is meaningful in extending P3Stor’s life span. The performance evaluation using trace-driven simulations and theoretical analysis shows that P3Stor achieves high performance and its life span is more than doubled.