Page-level Address Mappings Research Articles

DPAM: A Demand-Based Page-Level Address Mappings Algorithm in Flash Memory for Smart Industrial Edge Devices

Edge computing brings data storage closer to the location where it is needed. Therefore, the edge devices, especially smart industrial edge devices, require higher storage systems. NAND flash memory has the advantages of small size, high speed, and strong shock resistance, which is widely used in various storage systems, providing a good choice for edge devices. NAND flash has unique physical characteristics, such as “out-of-place updates” and “prewrite erasure,” therefore, the traditional address mapping methods require improvement. This article presents a novel demand-based page-level address mapping algorithm called DPAM. The goal of DPAM is to provide efficient address translation by using a smaller address mapping table. Due to the high service cost of block-level address mapping and hybrid address mapping, a page-level address mapping scheme is proposed. The algorithm is implemented and tested on the flash simulation platform FlashSim. The results indicate that our algorithm provides improvements of 7.11% for the hit ratio and 7% for the number of block erasures compared with other approaches.

A Correlation-Aware Page-Level FTL to Exploit Semantic Links in Workloads

NAND Flash based Solid State Disks (SSDs) are gaining tremendous popularity in today’s storage market due to their unique erase-before-write feature. The Flash Translation Layer (FTL) in the SSDs redirects the incoming writes to a free physical address and manages a logical to physical address mapping table. However, this induces significant performance degradation to the SSDs. One of the main reasons is that current cache management in FTLs is mainly optimized for the temporal or spatial locality. However, because of multiple levels of data buffers in the whole storage architecture, the locality of internal disk I/O is relatively low. What’s more, the increasing capacity of SSD not only generates large mapping tables, but also imposes high pressure on the efficiency of page-level address mapping. To overcome this limitation, we propose Correlation-Aware Page-level FTL, a.k.a CPFTL, which exploits I/O correlations in the workloads. In CPFTL, we develop a correlation-aware mapping table based on the correlation in read operations. We then build a correlation prediction table to support fast mapping entry lookup in the correlation-aware mapping table. Finally, we split read and write caches and build a skew-aware dirty entry index to improve the cache hit ratio and reduce the garbage collection overhead. Our emulator and prototype are open-sourced at: https://github.com/janzhou/SSD-Emulator . The experimental results show that CPFTL can reduce the average response time by 63.4 percent for read dominant workloads and 32.9 percent for transaction workloads.

RFTL: improving performance of selective caching-based page-level FTL through replication

The internal nature of flash memory technology, makes its performance highly dependent on workload characteristics causing poor performance on random writes. To solve this, Demand-based Flash Translation Layer (DFTL) which selectively caches page-level address mappings, was proposed. DFTL exploits temporal locality in workloads and when low, high cache miss rates are experienced. In this paper, we propose a replication based DFTL, called RFTL, which aims at minimizing the overhead caused by miss penalty from the cached mapping table in SRAM. We developed an analytical model for studying the range of performance for RFTL. We extended EagleTree simulator to implement RFTL. Our experimental evaluation with synthetic workloads endorses the utility of RFTL showing improved performance over DFTL especially for read-dominant workloads. With 80% read dominant workload, RFTL’s cumulative distribution function shows a 20% improvement and under 80% write dominant workload, it outperforms DFTL by 10% on I/O throughput.

Lazy-RTGC

Due to many attractive and unique properties, NAND flash memory has been widely adopted in mission-critical hard real-time systems and some soft real-time systems. However, the nondeterministic garbage collection operation in NAND flash memory makes it difficult to predict the system response time of each data request. This article presents Lazy-RTGC , a real-time lazy garbage collection mechanism for NAND flash memory storage systems. Lazy-RTGC adopts two design optimization techniques: on-demand page-level address mappings, and partial garbage collection. On-demand page-level address mappings can achieve high performance of address translation and can effectively manage the flash space with the minimum RAM cost. On the other hand, partial garbage collection can provide the guaranteed system response time. By adopting these techniques, Lazy-RTGC jointly optimizes both the average and the worst system response time, and provides a lower bound of reclaimed free space. Lazy-RTGC is implemented in FlashSim and compared with representative real-time NAND flash memory management schemes. Experimental results show that our technique can significantly improve both the average and worst system performance with very low extra flash-space requirements.

Data-assemblage: a translation-page-aware data block allocation strategy for flash-based solid state drives

Flash-based solid state drives (SSDs) are becoming popular as the storage media in recent years. In SSDs, translation pages normally store the address mapping information for data blocks. With the increasing capacity of SSDs, the management of translation pages is becoming a critical issue. In this paper, we present Data-Assemblage, a translation-page-aware data block allocation strategy for demand-based page-level address mappings in flash-based SSDs. Data-Assemblage is motivated by two observations: First, the translation page copy operations during garbage collection may significantly degrade the system performance. Second, the allocation of data blocks will directly impact the update operations in translation pages. By assembling write requests that share the same translation page into one data block, Data-Assemblage significantly reduces the page copies of translation pages and improves the average response time while retaining its space utilization and RAM cost. We evaluate Data-Assemblage using a set of benchmarks from both real-world and synthetic traces. Experimental results show that our scheme can achieve a 90.92 % reduction in the extra translation overhead and improve system performance by 22.14 % compared with the previous work.

DFTL

Recent technological advances in the development of flash-memory based devices have consolidated their leadership position as the preferred storage media in the embedded systems market and opened new vistas for deployment in enterprise-scale storage systems. Unlike hard disks, flash devices are free from any mechanical moving parts, have no seek or rotational delays and consume lower power. However, the internal idiosyncrasies of flash technology make its performance highly dependent on workload characteristics. The poor performance of random writes has been a cause of major concern, which needs to be addressed to better utilize the potential of flash in enterprise-scale environments. We examine one of the important causes of this poor performance: the design of the Flash Translation Layer (FTL), which performs the virtual-to-physical address translations and hides the erase-before-write characteristics of flash. We propose a complete paradigm shift in the design of the core FTL engine from the existing techniques with our Demand-based Flash Translation Layer (DFTL), which selectively caches page-level address mappings. We develop a flash simulation framework called FlashSim. Our experimental evaluation with realistic enterprise-scale workloads endorses the utility of DFTL in enterprise-scale storage systems by demonstrating: (i) improved performance, (ii) reduced garbage collection overhead and (iii) better overload behavior compared to state-of-the-art FTL schemes. For example, a predominantly random-write dominant I/O trace from an OLTP application running at a large financial institution shows a 78% improvement in average response time (due to a 3-fold reduction in operations of the garbage collector), compared to a state-of-the-art FTL scheme. Even for the well-known read-dominant TPC-H benchmark, for which DFTL introduces additional overheads, we improve system response time by 56%.