Page Allocation Research Articles

PARL: Page allocation in hybrid main memory using reinforcement learning

PARL: Page allocation in hybrid main memory using reinforcement learning

Page Replacement Algorithms: A Survey of Performance and Case Studies

This system uses paging as part of memory management in a computer's operating system. Page replacement algorithms are responsible for deciding which pages should be replaced when new allocations are required. Paging happens when there is a page fault, and there are insufficient or no free pages available for allocation. Keywords— Operating System, Page Replacement Algorithms, Virtual Memory Management, Page Allocation

Approximate data mapping in refresh-free DRAM for energy-efficient computing in modern mobile systems

In the context of modern mobile and embedded communication systems, the increasing storage density of dynamic random access memory (DRAM) poses significant challenges in energy management, with DRAM refresh emerging as a major factor in energy consumption. Meanwhile, approximate computing is becoming an emerging energy-efficient paradigm for mobile and embedded systems involving the error-resilient applications of media processing, recognition, and data mining. This paper proposes to leverage approximate computing to eliminate all the unnecessary refreshes in DRAM and makes it as energy-efficient as “non-volatile” devices. The devised solution is based on the observation that mapping the virtual page of certain reusing distances into the memory rows of the particular retention time intervals can greatly decrease or even completely eliminate refresh operations for approximate computing workloads. In the proposed Non-Volatile DRAM (NV-DRAM), special page allocation and data mapping strategies have been developed for different types of systems to control the Quality of Result (QoR) of the system and best exploit the allowable quality margin (precision loss) for refresh removing. A static data mapping policy and a control-theory inspired PID controller are proposed to dynamically map approximate work-set to NV-DRAM rows without infringing the QoR constraint. The results show that the error rate of our predictive strategies can be controlled under 1%, and our proposal saves more than 99.9% of refresh energy consumption.

Characterizing Multi-Chip GPU Data Sharing

Multi-chip Graphics Processing Unit (GPU) systems are critical to scale performance beyond a single GPU chip for a wide variety of important emerging applications. A key challenge for multi-chip GPUs, though, is how to overcome the bandwidth gap between inter-chip and intra-chip communication. Accesses to shared data, i.e., data accessed by multiple chips, pose a major performance challenge as they incur remote memory accesses possibly congesting the inter-chip links and degrading overall system performance. This article characterizes the shared dataset in multi-chip GPUs in terms of (1) truly versus falsely shared data, (2) how the shared dataset scales with input size, (3) along which dimensions the shared dataset scales, and (4) how sensitive the shared dataset is with respect to the input’s characteristics, i.e., node degree and connectivity in graph workloads. We observe significant variety in scaling behavior across workloads: some workloads feature a shared dataset that scales linearly with input size, whereas others feature sublinear scaling (following a \(\sqrt {2}\) or \(\sqrt [3]{2}\) relationship). We further demonstrate how the shared dataset affects the optimum last-level cache organization (memory-side versus SM-side) in multi-chip GPUs, as well as optimum memory page allocation and thread scheduling policy. Sensitivity analyses demonstrate the insights across the broad design space.

Reducing Minor Page Fault Overheads through Enhanced Page Walker

Application virtual memory footprints are growing rapidly in all systems from servers down to smartphones. To address this growing demand, system integrators are incorporating ever larger amounts of main memory, warranting rethinking of memory management. In current systems, applications produce page fault exceptions whenever they access virtual memory regions that are not backed by a physical page. As application memory footprints grow, they induce more and more minor page faults. Handling of each minor page fault can take a few thousands of CPU cycles and blocks the application till the OS kernel finds a free physical frame. These page faults can be detrimental to the performance when their frequency of occurrence is high and spread across application runtime. Specifically, lazy allocation-induced minor page faults are increasingly impacting application performance. Our evaluation of several workloads indicates an overhead due to minor page faults as high as 29% of execution time. In this article, we propose to mitigate this problem through a hardware, software co-design approach. Specifically, we first propose to parallelize portions of the kernel page allocation to run ahead of fault time in a separate thread. Then we propose the Minor Fault Offload Engine (MFOE), a per-core hardware accelerator for minor fault handling. MFOE is equipped with a pre-allocated page frame table that it uses to service a page fault. On a page fault, MFOE quickly picks a pre-allocated page frame from this table, makes an entry for it in the TLB, and updates the page table entry to satisfy the page fault. The pre-allocation frame tables are periodically refreshed by a background kernel thread, which also updates the data structures in the kernel to account for the handled page faults. We evaluate this system in the gem5 architectural simulator with a modified Linux kernel running on top of simulated hardware containing the MFOE accelerator. Our results show that MFOE improves the average critical path fault handling latency by 33× and tail critical path latency by 51×. Among the evaluated applications, we observed an improvement of runtime by an average of 6.6%.

HIPA: A hybrid load balancing method in SSDs for improved parallelism performance

NAND Flash-based SSDs have been widely adopted as underlying storage devices in storage systems thanks to high random performance in the SSDs. Because of inherent rich parallelism resources (channel, chip, plane, and die) inside an SSD, many researchers pay much attention on parallelism improvement. Page allocation policies (static and dynamic page allocation) in an SSD aim to translate logical addresses of I/O requests on the host into physical addresses in flash memory space. Existing static page allocation policies suffer from severe load unbalance inside SSDs. Dynamic allocation policies employed in high-performance SSDs address the load balancing issue. However, dynamic allocation-based I/O requests flow into fewer parallelism resources, deteriorating read I/O-requests parallelism. Recognizing that SSD performance can be optimized by reducing read parallelism loss, we propose a hybrid page allocation strategy named HIPA to fully exploit the advantages of dynamic and static allocation to achieve read/write parallelisms inside an SSD. HIPA embraces a load prediction mechanism to monitor die-level load in real-time, thereby determining a page allocation policy based on the status of die-level load. A static page allocation policy is triggered in case of balanced die-level load. When performance degrades due to imbalance in die-level load, HIPA dynamically changes the gear to a dynamic allocation policy, aiming to balance the load on dies. Thus, HIPA achieves the maximum read parallelism rather than crumbling write performance. Conducting the extensive experiments, we validate the advantages of HIPA in terms of average response time, plane-level write, and erase standard deviation. The findings unveil that compared with the four popular page allocation policies (CWDP, CHIP-D, DIE-D, and PLANE-D), HIPA slashes the average response time by up to 58% with an average of 20% and 81% with an average of 33% compared with the dynamic allocation (DIE-D) with the lowest response time and the static strategy, respectively; (2) drives up the write standard deviation degree of the static strategy by up to 44%; (3) improves erase standard deviation rate by up to 43%.

DQN based page allocation for ReRAM main memory

Benefiting from the characteristics of non-volatile, low leakage power consumption, high density, and good scalability, resistive random access memory (ReRAM) has been considered to replace DRAM as the main memory of embedded devices. However, ReRAM suffers from endurance issue that may lead to data failure. In this work, we take the endurance discrepancy of different ReRAM cells into consideration and proposed a Deep Q-Network (DQN) based page allocation scheme to evenly wear out ReRAM cells. We further embedded the proposed scheme in a real-time scenario and proved that it can effectively guarantee the deadline of each task. We have conducted a series of simulations and the results show that compared with the traditional page allocation scheme, our scheme prolongs the endurance time of ReRAM up to 118%.

CFFS: A Persistent Memory File System for Contiguous File Allocation With Fine-Grained Metadata

Extensive research on persistent memory (PM)-aware file systems has led to the development of numerous methods for improving read/write throughput. In particular, accessing or modifying file contents in a similar manner to the memory operations through <i>mmap</i> is a common approach. We designed a file system, CFFS (Contiguous File Allocation with Fine-Grained Metadata File System), to rapidly allocate PM pages to upper layer applications for <i>mmap</i> and to alleviate page fault overheads due to <i>mmap</i>. We optimized the physical contiguity of files in PM to reduce file fragmentation and increase fragment alignment with the goal of reducing software overhead. To achieve this goal, we implemented greedy-based buddy systems and implicit preallocation with a not-most-recently-used (NMRU) policy based on our overall page allocation strategy of considering not only the spatial but also the temporal locality of file access patterns. Furthermore, for efficient and atomic metadata operations, we fully leveraged the byte-addressable property of PM to design fine-grained metadata. CFFS adopts persistent doubly linked lists for directory operations to identify and recover from inconsistencies caused by system failures, doing so without using traditional log mechanisms. In experiments, CFFS showed superior page allocation performance to EXT4-DAX and NOVA did under different PM fragmentation levels. Our allocation algorithm also reduced the cost of page faults for frequently appended files. Finally, CFFS&#x2019;s lightweight directory operations performed excellently in creating and deleting files of various quantities. In summary, the main contribution of the paper is proposing an efficient page allocation algorithm to improve the performance of subsequent <i>mmaps</i>, based on the strategy of considering not only the spatial but also the temporal locality of file access patterns in PM file systems. Another contribution was the fine-grained and log-free method for atomic directory operations.

Improving Overall Performance of TLC SSD by Exploiting Dissimilarity of Flash Pages

TLC flash has three types of pages to accommodate the three bits in each TLC physical cell exhibiting very different program latencies. This paper proposes PA-SSD to effectively improve the overall performance by exploiting the dissimilarity of TLC pages on program latency throughout the write request handling workflow. The main idea behind PA-SSD is to coordinately allocate the same type of pages for sub-requests of any given user write request, to mitigate the potential program latency imbalance among the sub-requests, and to schedule sub-requests according to their page-types. We achieve the PA-SSD design goal by answering three key research questions: (1) how to properly determine page-type for each user write request? (2) how to actually allocate a physical page for each sub-request with an assigned page-type from (1)? (3) how to effectively schedule the sub-requests in the chips queues when their page-types are judiciously allocated from (2)? To answer the first question, we propose seven page-type specifying schemes to investigate their effects under different workloads. We answer the second question by redesigning the page allocation strategy in TLC SSD to uniformly and sequentially determine physical pages for allocation following the internal programming process of TLC flash. Lastly, a page-type aware scheduling policy is presented to reorder the sub-requests within chips’ queues. Our experiments show that PA-SSD can accelerate both the write and read performance. Particularly, our proposed queue-depth based page-type specifying scheme improves write performance by 2.6 times and read performance by 1.5 times over the conventional TLC SSD.

Optimal Page Allocation of Hybrid Main Memory using Page Caching Algorithm

In memory management system, DRAM has long write endurance and PRAM has shorter write latency. To get the advantages of both memories, a hybrid memory is constructed using DRAM and PRAM. In this article, the task allocation strategies on hybrid memory were carried out to achieve multiple targets such as, extending the lifetime, reducing power consumption and reducing the memory size. Different types of algorithm such as, genetic algorithm, scalable algorithm and distributed algorithms are proposed by many researchers. Here, page caching algorithm is proposed to achieve an optimal performance. The Page caching algorithm includes the following steps: 1.Getting instructions from CPU and finding address in DRAM, 2. Extracting page in PRAM, 3.Reallocating the page in DRAM and 4. Updating in PRAM. The work is designed and implemented using an evaluation framework and the hybrid memories optimal performance is calculated. The user provides workload, PRAM and DRAM parameters and environmental characteristics of hybrid memory as inputs to the system. It also determines the overall performance by considering several limitations. This architecture first optimizes the page allocation and then the task write in the memory was allocated. Comparing to the existing system, the page caching algorithm reduces upto 32.8% of total power.

A Real-Time Dependable Flash Storage System

One of the limitations of flash memory in real time, high dependability systems is its need for garbage collection and the resulting performance degradation due to non-deterministic response times. Recent work has presented RAID architectures for solid state storage systems. These RAID architectures increase the dependability from a data storage perspective but they do not provide application level dependability when real-time response times are required. In this study we present a garbage collection aware flash translation layer that offers guaranteed access time to a solid state RAID array by managing incoming requests and preventing them from being blocked by ongoing garbage collection. We present a novel serial technique with a dynamic page allocation mechanism that completely eliminates non deterministic behaviors of the garbage collectors in the array. The result is real-time access guarantees that maintain the data dependability enhancements using a run time parity migration technique. The mechanisms are evaluated using trace driven simulator and a number of synthetic and realistic traces. Simulation results indicate that the garbage collection aware techniques offer improved upper bound response times for I/O requests of up to 73% compared to an existing mechanism, without disturbing the data dependability at the storage level. Traces dominated by random writes exhibit similarly significant enhancements.

A New Indexing Method for Uncertain Databases

This paper presents an indexing method called the uncertain data index (UD-index) for uncertain databases. The design objectives of the UD-index are improving the range query performance of the multidimensional indexing methods and providing a compromise between optimal index node clustering. Although more than ten years of database research has resulted in a great variety of multidimensional indexing methods, most efforts have focused on the data-level clustering and there has been no attempt to cluster index nodes themselves in dynamic environments. As a result, most related index nodes are widely scattered on the disk due to dynamic page allocation, and it requires many random disk accesses during the range search. The UD-index avoids that by storing the related nodes contiguously in a segment that contains a sequence of contiguous disk pages. The UD-index improves the range query performance by offering high-performance sequential disk access within a segment. A new cost model is introduced to estimate the range query performance. It takes into consideration the physical adjacency of pages read as well as the number of pages accessed. The analytic performance analysis indicates that the UD-index shows better performance than the traditional indexing methods in most cases.

Making Huge Pages Actually Useful

The virtual-to-physical address translation overhead, a major performance bottleneck for modern workloads, can be effectively alleviated with huge pages. However, since huge pages must be mapped contiguously, OSs have not been able to use them well because of the memory fragmentation problem despite hardware support for huge pages being available for nearly two decades. This paper presents a comprehensive study of the interaction of fragmentation with huge pages in the Linux kernel. We observe that when huge pages are used, problems such as high CPU utilization and latency spikes occur because of unnecessary work (e.g., useless page migration) performed by memory management related subsystems due to the poor handling of unmovable (i.e., kernel) pages. This behavior is even more harmful in virtualized systems where unnecessary work may be performed in both guest and host OSs. We present Illuminator, an efficient memory manager that provides various subsystems, such as the page allocator, the ability to track all unmovable pages. It allows subsystems to make informed decisions and eliminate unnecessary work which in turn leads to cost-effective huge page allocations. Illuminator reduces the cost of compaction (up to 99%), improves application performance (up to 2.3x) and reduces the maximum latency of MySQL database server (by 30x). Importantly, this work shows the effectiveness of a simple solution for long-standing huge page related problems.

Impacts of Memory Address Mapping Scheme on Reducing DRAM Self-Refresh Power for Mobile Computing Devices

With the growth of the Internet of Things (IoT), increasingly, more computing tasks are implemented on power-sensitive mobile devices, causing a bottleneck on energy consumption. Most mobile devices consume considerable power in the standby mode, during which the capacitive DRAM cells’ self-refresh power, which is used to preserve data integrity, accounts for a large part. To address this issue, strategies from both hardware and software perspectives have been proposed, and yet, the existing hardware methods usually have a high cost. Software strategies mainly focus on the operating system page allocation strategy to maximize resource idleness. The partial array self-refresh technique has been proposed to allow for some of the DRAM cells to retain the self-refresh state while shutting down the others. Using this technique, numerous studies extend the unused DRAM idle time by clustering the applications’ data but do not discuss the impact of the address mapping mechanism on power consumption. However, this impact was proven to be essential in our previous study. In this paper, we attempt to investigate the impacts of different memory mapping schemes on different clustering strategies using a hierarchy-based memory management system (HBMM) and provide insights for selecting the optimal schemes. The experimental results on the Android platform demonstrate that the schemes and strategies are closely correlated, and memory idle time can be prolonged 125 times with their suitable combination. Conversely, the worst scheme may decrease memory idleness by 12% compared with the original system. Furthermore, our studies on a physical platform show that standby power consumption can be saved by 23% when using HBMM combined with the best clustering strategy.

Heterogeneous HMC+DDRx Memory Management for Performance-Temperature Tradeoffs

Three-dimensional DRAMs (3D-DRAMs) are emerging as a promising solution to address the memory wall problem in computer systems. However, high fabrication cost per bit and thermal issues are the main reasons that prevent architects from using 3D-DRAM alone as the main memory building block. In this article, we address this issue by proposing a heterogeneous memory system that combines a double data rate (DDRx) DRAM with an emerging 3D hybrid memory cube (HMC) technology. Bandwidth and temperature management are the challenging issues for this heterogeneous memory architecture. To address these challenges, first we introduce a memory page allocation policy for the heterogeneous memory system to maximize performance. Then, using the proposed policy, we introduce a temperature-aware algorithm that dynamically distributes the requested bandwidth between HMC and DDRx DRAM to reduce the thermal hotspot while maintaining high performance. We take into account the impact of both core count and HMC channel count on performance while using the proposed policies. The results show that the proposed memory page allocation policy can utilize the memory bandwidth close to 99% of the ideal bandwidth utilization. Moreover, our temperate-aware bandwidth adaptation reduces the average steady-state temperature of the HMC hotspot across various workloads by 4.5 K while incurring 2.5% performance overhead.

Segment and Conflict Aware Page Allocation and Migration in DRAM-PCM Hybrid Main Memory

Phase change memory (PCM), given its nonvolatility, potential high density, and low standby power, is a promising candidate to be used as main memory in next generation computer systems. However, to hide its shortcomings of limited endurance and slow write performance, state-of-the-art solutions tend to construct a dynamic RAM (DRAM)-PCM hybrid memory and place write-intensive pages in DRAM. While existing optimizations to this hybrid architecture focus on tuning DRAM configurations to reduce the number of write operations to PCM, this paper explores the interactions between DRAM and PCM to improve both the performance and the endurance of a DRAM-PCM hybrid main memory. Specifically, it exploits the flexibility of mapping virtual pages to physical pages, and develops a proactive strategy to allocate pages taking both program segments and DRAM conflict misses into consideration, thus distributing those heavily written pages across different DRAM sets. Meanwhile, a lifetime-aware DRAM replacement algorithm and a conflict-aware page remapping strategy are proposed to further reduce DRAM misses and PCM writes. Experiments confirm that the proposed techniques are able to improve average memory hit time and reduce maximum PCM write counts thus enhancing both performance and lifetime of a DRAM-PCM hybrid main memory.

Microsoft SQL Server 삭제 이벤트의 데이터 잔존 비교

Microsoft SQL Server의 데이터 복구와 관련된 그간의 연구는 삭제된 레코드가 트랜잭션 로그에 존재하는 경우를 바탕으로 복원하는 방법이 주를 이루었다. 그러나 관련 트랜잭션 로그가 존재하지 않거나 물리 데이터베이스 파일이 Server와 연결되어 있지 않은 경우 적용하기 곤란한 한계가 있었다. 그러므로 범죄 과정에서 용의자가 delete 외 다른 이벤트를 이용하여 삭제할 가능성이 있기 때문에 이에 대한 삭제된 레코드의 잔존을 확인하여 복구 가능성을 확인해볼 필요가 있다. 이 논문에서는 Microsoft SQL Server 물리 데이터베이스 파일의 구조를 기초로 데이터 삭제가 수행되는 delete, truncate, drop 이벤트에 따른 Page 할당정보 유지 여부, 미할당 삭제데이터 존재 여부, 페이지 내 행오프셋 배열 정보의 변화를 실험하여 최종적으로 디지털포렌식 조사 시 관리도구 이용 가능성 및 데이터 복구 가능성을 확인하였다. Previous research on data recovery in Microsoft SQL Server has focused on restoring data based on in the transaction log that might have deleted records exist. However, there was a limit that was not applicable if the related transaction log did not exist or the physical database file was not connected to Server. Since the suspect in the crime scene may delete the data records using a different deletion statements besides "delete", we need to check the remaining data and a recovery possibility of the deleted record. In this paper, we examined the changes "Page Allocation information" of the table, "Unallocation deleted data", "Row Offset Array" in the page according to "delete", "truncate" and "drop" events. Finally it confirmed the possibility of data recovery and availability of management tools in Microsoft SQL Server digital forensic investigation.

Exploring Parallel Data Access Methods in Emerging Non-Volatile Memory Systems

The exploitation of internal parallelism over hundreds of NAND flash memories is becoming a key design issue in high-speed solid state disks (SSDs). In this study, we simulate a cycle-accurate SSD platform with diverse parallel data access methods and 24 page allocation strategies, which are geared toward exploiting both system-level parallelism and flash-level parallelism, using a variety of design parameters. Our extensive experimental analysis reveals that 1) the previously proposed channel striping-based page allocation strategy is not the best from a performance perspective, 2) as opposed to the common belief that system-level and flash-level concurrency mechanisms are largely orthogonal, the system-level parallel data access methods employed interferes with flash-level parallelism, 3) when most of the current currency controls and page allocation strategies are implemented, the SSD internal resources are significantly underutilized, and 4) while the performance of all the page allocation strategies on read-intensive workloads (reads $>$ 99 percent) is improved by employing a high frequency flash interface, the performance enhancements are significantly limited. Finally, we present several optimization points to extract the maximum internal parallelism by offering comprehensive evaluations with controllable and easy-to-understand micro-benchmarks.

On the Restore Time Variations of Future DRAM Memory

As the de facto main memory standard, DRAM (Dynamic Random Access Memory) has achieved dramatic density improvement in the past four decades, along with the advancements in process technology. Recent studies reveal that one of the major challenges in scaling DRAM into the deep sub-micron regime is its significant variations on cell restore time, which affect timing constraints such as write recovery time. Adopting traditional approaches results in either low yield rate or large performance degradation. In this article, we propose schemes to expose the variations to the architectural level. By constructing memory chunks with different access speeds and, in particular, exploiting the performance benefits of fast chunks, a variation-aware memory controller can effectively mitigate the performance loss due to relaxed timing constraints. We then proposed restore-time-aware rank construction and page allocation schemes to make better use of fast chunks. Our experimental results show that, compared to traditional designs such as row sparing and Error Correcting Codes, the proposed schemes help to improve system performance by about 16% and 20%, respectively, for 20nm and 14nm technology nodes on a four-core multiprocessor system.

Morphable Resistive Memory Optimization for Mobile Virtualization

Virtualization offers significant benefits, such as better isolation and security for mobile systems. However, the limited amount of memory and virtualization’s memory-demanding nature make it challenging to virtualize mobile systems efficiently. In this paper, we utilize morphable resistive memories to design a high-performance mobile system with an extensible memory space. With morphable resistive memories, a simple and effective page management technique, Balloonfish, is proposed to convert the memory cell state between multilevel and single-level for achieving a balance between performance and memory space. First, an application-specific page allocation is proposed for managing morphable resistive memories in virtualized mobile systems. Besides, we use a balloon-style algorithm to balance memory allocation among multiple virtual machines. Our evaluation based on the Samsung Exynos 5250 system-on-chip with various real Android applications shows that our system achieves 28.63% performance improvement compared with the baseline scheme.