Packet-switched Interconnection Networks Research Articles

Power-aware high level evaluation model of interconnect length of on-chip memory network topology

Interconnect power is the factor that dominates the power consumption on the on-chip memory architecture. Almost all dedicated wires and buses are replaced with packet switching interconnection networks which have become the standard approach to on-chip interconnection. Unfortunately, rapid advances in technology are making it more difficult to assess the interconnect power consumption of NoC. To resolve this problem, a new evaluating methodology for interconnect power evaluation based on topology of on-chip memory (IP-ETOM) is proposed in this paper. To validate this method, two multicore architectures 2D-mesh and triplet-based architecture (TriBA) are evaluated in this research work. The on-chip memory network model is evaluated based on characteristics of on-chip architecture interconnection. MATLAB is used for conducting the experiment that evaluates the interconnection power of TriBA and 2D-mesh.

New nodal design for high throughput data vortex optical interconnection network

This paper proposes a new three input nodal structure within the data vortex packet switched interconnection network. With additional optical switches, the modified architecture allows for two input packets in addition to a buffered packet to be processed simultaneously within a routing node. A much higher degree of parallel processing is allowed in comparison to previously proposed enhanced buffer node with two input processing or the original network node with single input processing. Unlike the previous contention prevention mechanism, the new network operates by introducing the packet blocking within the node if no exit path is available. This eliminates the traffic control signaling and the strict timing alignment associated with the routing paths which simplifies the overall network implementation. This study shows that both data throughput and the latency performance are improved significantly within the new network. The study compares the three input node with the two input node as well as the original single input data vortex node. Due to additional switch count and nodal cost, networks that support the same I/O ports and of the same cost are compared for a fair comparison. The limitation introduced by the blocking rate is also addressed. The study has shown that under reasonable traffic and network condition, the blocking rate can be kept very low without introducing complex controls and management for dropped packets. As previous architectures require operation under saturation point, the proposed architecture should also operate at reasonable level of network redundancy to avoid excessive packet drop. This study provides guidance and criteria on the proposed three input network design and operation for feasible applications. The proposed network provides an attractive alternative to the previous architectures for higher throughput and lower latency performance.

An Experimental Validation of a Wavelength-Striped, Packet Switched, Optical Interconnection Network

We experimentally validate a complete optical packet switched interconnection network, implementing the SPINet architecture. The scalable photonic integrated network (SPINet) architecture capitalizes on wavelength division multiplexing (WDM) to provide very large transmission bandwidths, simplify network design, and reduce the network's power dissipation. Contention resolution is performed in the optical domain, and a novel physical layer acknowledgement protocol is employed to mitigate the associated latency and performance penalties. Moreover, the SPINet architecture is specifically designed to enable on-chip integration by not using any kind of optical delay lines. Experiments presented include a complete functionality verification, error-free routing of 80 Gb/s wavelength-striped optical packets (8 wavelengths each modulated at 10 Gb/s) with a bit-error rate (BER) better than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> , and novel performance-enhancement techniques such as path adjustments and load balancing.

All-optical packet-switched interconnection network based on modular photonic digital processing

Future interconnection networks will be required to achieve ultra-high bandwidth and low latency communications to cope with the increasing performance requirements of backbone routers, large data storage systems and supercomputing systems. Aiming at achieving ultra-high bandwidth communications and approaching optical time-of-flight processing latency while being robust to cascade impairments, the authors propose an all-optical packet-switched interconnection network, where not only the actual packet switching but also the packet processing is performed in the photonic domain. The authors present two modular architectures, based on the crossbar and the Batcher–Banyan topologies, capable of forwarding fixed-length packets with two classes of service. Both use photonic digital-processing subsystems built by combining a single integrable module which exploits cross gain modulation in a semiconductor optical amplifier. System level simulations on the crossbar switch controller guarantee that the control signals maintain an acceptable quality during the processing. Moreover, the Batcher–Banyan configuration is more cost-effective than the crossbar for increasing port count, while effective network performance in terms of packet loss rate can be obtained by adding just few recirculating delay lines.

Rotary router

The trend towards increasing the number of processor cores and cache capacity in future Chip-Multiprocessors (CMPs), will require scalable packet-switched interconnection networks adapted to the restrictions imposed by the CMP environment. This paper presents an innovative router design, which successfully addresses CMP cost/performance constraints. The router structure is based on two independent rings, which force packets to circulate either clockwise or anti-clockwise, traveling through every port of the router. It uses a completely decentralized scheduling scheme, which allows the design to: (1) take advantage of wide links, (2) reduce Head of Line blocking, (3) use adaptive routing, (4) be topology agnostic, (5) scale with network degree, and (6) have reasonable power consumption and implementation cost. A thorough comparative performance analysis against competitive conventional routers shows an advantage for our proposal of up to 50 % in terms of raw performance and nearly 60 % in terms of energy-delay product.

Performance evaluation of the augmented data vortex switch fabric: An all-optical packet switched interconnection network

Modern high-performance computing systems require networks with high capacity, extremely high throughput and low latency in order to pass messages between thousands of processors and memory elements. Optical Interconnection Networks (OIN) offer a potentially viable solution to this requirement. An all-optical packet switched interconnection network called a Data Vortex (DV) switch has already been proposed by Yang et al. for the purpose of large scale photonic interconnections. For any interconnection network, fault tolerance and reliability are crucial issues, evaluation of which lacked attention for the case of the DV switch. In our earlier work we therefore presented the results for fault tolerance and reliability analysis of the primary DV switch. We also proposed a new Augmented Data Vortex (ADV) switch fabric, to improve the fault tolerance of the primary DV switch. The performance as regards fault tolerance of the ADV switch was computed and detailed results were obtained. In this paper, performance of ADV is investigated with reference to parameters such as latency and injection ratio (throughput) by means of numerical simulations. A uniform random traffic model has been used for the performance evaluation. The results obtained are compared with the results reported for the DV switch. The results show that the ADV switch with enhanced fault tolerance also improves the performance regarding latency. For same switch sizes (i.e. the same number of angles A , and height H ) the injection ratios (throughput) for the DV and the ADV switches are comparable. Hence it can serve as a suitable candidate for high performance computing.

The augmented data vortex switch fabric: An all-optical packet switched interconnection network with enhanced fault tolerance

Optical Multistage Interconnection Networks (OMINs) are capable of transmitting terabits of bandwidth per second, and they have been considered as possible solutions to the electronic communications bottleneck in interconnection networks. A novel architecture, the Data Vortex (DV) switch, has been proposed by Yang et al., as a scalable, ultra low latency, ultra high capacity, high throughput, low cross-talk and low BER, all-optical packet switching fabric that is a suitable candidate for use as an OMIN. For any interconnection network, its fault tolerance and reliability are crucial issues, which have lacked attention up to now in the case for a DV switch. In this paper we, therefore, present results of fault tolerance and reliability analysis of the primary DV switch, and propose (1) a new Augmented Data Vortex (ADV) switch fabric, to improve the fault tolerance of the primary DV switch. (2) The labelling and a numbering scheme, with detailed interconnections of nodes for the ADV switch is given. (3) A new self-routing procedure and a priority scheme for distributed control signalling in the ADV switch have been given. (4) For the first time, conversion of the 3-dimensional switch to an equivalent chained-MIN model, has been given, which is more suitable for later analysis of fault tolerance. (5) A multiplexing scheme at input ports and output ports which further enhances the fault tolerance of the ADV switch has been given. (6) Computation has been done of the reliability and fault tolerance of the new architecture via an analytical model. (7) Finally, comparison of the ADV switch architecture with the primary architecture (DV) in view of fault tolerance and reliability has been given, and hardware complexity and cost effectiveness have been studied.

Bit-parallel message exchange and data recovery in optical packet switched interconnection networks

Multiwavelength optical messages encoded in a bit-parallel fashion are successfully routed through five switching nodes of a 12-port optical packet switching interconnection network. The data payloads are entirely recovered and processed at the destination node using an embedded clock signal with a measured clock-to-data skew tolerance window of 150 ps.

Development of the Base Station Transceiver Subsystem in the CDMA Mobile System

The base station transceiver subsystem (BTS) of the CDMA Mobile System is interfaced to mobile stations over the air and to the wired network through a packet switched interconnection network. The potential benefits of CDMA technology are achieved when the transmitter and the receiver are properly designed and implemented. The physical layer of the air interface at the base station is implemented with the CDMA ASICs and control circuits in the channel card of the BTS. We present the design perspectives and structural illustration of the BTS. Base station modem ASICs and their control to implement the CDMA receiver, baseband and RF signal processing blocks, and BTS controller are described. Elaborate power control is essential to ensure the high capacity which is one of advantages of the CDMA technology. The closed loop reverse link power control and the forward link power control operated in the BTS are described.

Prevention of congestion in packet-switched multistage interconnection networks

This paper proposes a simple, yet effective scheme to prevent congestion in a packet-switched multistage interconnection network (MIN) caused by hot spots. In this scheme, switches in the second and third stages of the MIN monitor their buffer occupancy to detect any notable nonuniform access behavior. When a switch detects congestion, packets generated by processors will be blocked from entering the congested switch until the congestion is cleared. Our scheme is compared with two well known schemes and shown to exhibit significantly better performance than these two. >

A contribution to the problem of avoiding congestion in multistage networks in the presence of unbalanced traffic

Multistage packet-switched interconnection networks (MINs) have been proposed for use in parallel processing systems and for implementation of fast packetswitch architecture designs. Performance of these networks has been known to severely degrade under unbalanced (nonuniform) traffic patterns. This article proposes various flow control procedures and corresponding logical implementations as possible solutions to the problem of performance degradation of such systems. Simulation results are presented to show the potential to improve MIN performance by introducing the proposed flow-control procedures.

Picosecond multistage interconnection network architecture for optical computing

We use nonlinear optical bistable devices to design a prototype of a building block for an all-optical multistage interconnection network architecture. This architecture is flexible in the sense that it can be used for either circuit-switched interconnection networks or packet-switched interconnection networks, depending on the user's applications and type of network architecture. Therefore this is a generalpurpose all-optical switch that is applicable to almost all types of network such as omega, banyan, perfect shuffle, etc. The system consists of several design units, each of which is described separately, and then all are synthesized together to form the complete system. When used with the packet-switched networks, the system is capable of buffering information optically with no need for electronic backup. The main functions of the architecture are achieved by the use of a nonlinear optical bistable device, namely, the interference filter (with the addition of mirrors and beam splitters). These optical c mponents are commercially available. They can also be integrated for future mass production. Therefore we anticipate that the implementation of this architecture is feasible.

A novel flow control and switching strategy for preventing hotspot congestion in multistage networks

Multistage packet switched interconnection networks have been proposed both for use in parallel processing systems and for communications switching. The performance of these networks has been known to degrade severely with non-uniformities in the traffic distribution. In this paper we present a combination of a flow control scheme with a novel switching strategy that reduces the performance degradation of such networks. We also present a switch model in order to support the proposed solution. Simulation results are presented to show that this method can successfully improve the overall network performance.

Performance analysis of synchronous multibuffered packet-switching networks

In this paper, a general mathematical method for analysis of synchronous multibuffered packet-switching interconnection networks in multiprocessor systems is presented. The proposed mathematical method is general in that he analyzed synchronous interconnection networks under uniform and nonuniform traffic. The existing methods for analysis of buffered interconnection networks have assumed either single or infinite buffers at each output (or input) port of a switch, as well as uniform traffic pattern of the networks. Recently, H. Yoon et al. [1] have presented an analytical model of buffered delta networks, assuming finite buffers at each input port and uniform traffic. Firstly, in the paper, a general model of synchronous buffered switching element, using output buffering, under assumption of finite buffer size for a very general class of traffic, is presented. Traffic can be uniform or nonuniform. It is assumed that the subsequent stages of the network are nearly independent and a model is extended for entire network under this assumption. Analytical results obtained with proposed model are then compared with each other, and it is shown that the proposed mathematical method is more general then the known models of interconnection networks.

Performance Evaluation of a Class of Multipath Packet Switching Interconnection Networks

This paper serves two purposes. First, it demonstrates that the analytic models and techniques used for unique-path networks can also be adopted for a class of multipath networks, called plusminus-2 (PM2I) networks. This is done by comparison of the analytic results and simulation results for unbuffered PM2I networks. Second, it extends earlier performance analysis of single-buffered delta networks, based on (2 x 2) crossbar switches, to handle different network types and switch sizes. From the extended performance model, numeric results for single-buffered delta networks based on switches larger than (2 )< 2) and single-buffered PM2I networks are obtained and compared.

A program-driven simulation model of an MIMD multiprocessor

A simulation model that supports very accurate modeling of multiprocessors with a hierarchical, packet-switched interconnection network and private caches is explored. The simulation system contains workload simulators and a memory system simulator. The workload simulators are program-driven, i.e. they actually execute programs. The time unit of the simulator is the time between two consecutive memory references from the processors. The performance of the simulation model, although acceptable, could be improved using a trace-driven approach. The author shows that results obtained from trace-driven simulation methods in the course of multiprocessor performance evaluation are generally not valid. Furthermore, he shows that in the evaluation of certain processor architectural features, such as non-blocking architectures, the program-driven approach is necessary. >

Performance analysis of multibuffered packet-switching networks in multiprocessor systems

An analytic model and analytic results for the performance of multibuffered packet-switching interconnection networks in multiprocessor systems are presented. The performance of single-buffered delta networks is first modeled using the state transition diagram of a buffer. The model is then extended to account for multiple buffers. The analytic results for multibuffered delta networks are compared to simulation results. The performance of multibuffered data manipulator networks is analyzed to demonstrate the generality of the model.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Approximate analysis of single and multiple ring networks

Asynchronous packet-switched interconnection networks with decentralized control are very appropriate for multiprocessing and data-flow architectures. The authors present performance models of single- and multiple-ring networks based on token-ring, slotted-ring, and register-insertion-ring protocols. The multiple ring networks have the advantage of being reliable, expandable, and cost effective. An approximate and uniform analysis, based on the gate M/G/1 queuing model, has been developed to evaluate the performance of both existing single-ring networks and the proposed multiple-ring networks. Approximations are good for low and medium load. The analyses are based on symmetric ring structure with nonexhaustive service policy and infinite queue length at each station. They essentially involve modeling of queues with single- and multiple-walking servers. The results obtained from the analytical models are compared to those obtained from simulation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Performance evaluation of nonrectangular multistage interconnection networks

The performance is considered of unbuffered packet-switching nonrectangular multistage interconnection networks. Performance analysis is based on a simplified model for resolution of packet contention. An approximate closed-form analytical expression for the probability of packet acceptance is derived. Blocking characteristics of nonrectangular networks are analyzed and it is shown that for large nonrectangular networks, the probability of packet acceptance does not degrade with growth of network size. >

The importance of being square

We present a theory that defines performance of packet-switching interconnection networks (delay and capacity) and their cost in terms of their geometry. This is used to prove that square banyan networks have optimal performance/cost ratio. These results, together with some known results on the complexity of routing in multistage networks, show that multistage shuffle-exchange networks are the unique networks with both optimal performance and simple routing. Finally, square delta networks are shown to have optimal area complexity.