Packet Switch Architecture Research Articles

Comparative analysis of optical data center switches

Abstract In the recent past, there has been an explosive growth in data traffic within data center systems. This rapid increase in data volume has put significant constraints on the speed of current data communication networks, which are predominantly based on electronic controllers and memory. The speed limitations of electronic devices hinder their ability to process data at higher rates efficiently. To address this issue and enable faster data processing, the use of optical communication emerges as the most promising solution. Optical communication leverages the capabilities of light signals and optical components, which can handle data at much higher rates compared to their electronic counterparts. One key element in optical communication systems is the utilization of fiber delay lines (FDLs) as optical storage for packets. FDLs offer the ability to temporarily store and delay optical signals, providing buffering capabilities within optical networks. These FDLs can be configured in various setups, including feed forward, feed backward, and recirculating configurations, each with its own set of advantages and disadvantages. In this context, this article explores several state-of-the-art arrayed waveguide grating (AWG)-based optical packet switch (OPSW) architectures. These switches are designed to efficiently route and manage optical packets within data center networks. Each architecture is summarized, highlighting its unique features and capabilities. To compare the different AWG-based OPSW architectures, various key parameters are considered, such as the cost, physical losses, bit error rate (BER), and the number of tunable components required. These parameters are critical in determining the performance, efficiency, and cost-effectiveness of the switches.

160 Gbps capacity and sub-us latency of polarization-independent optical packet switch architecture for free-space optical network using PLZT optical switch

In this paper, we discuss the challenges and limitations of current free-space optical (FSO) networks toward scaling beyond the 100 Gbps switch capacity era while achieving low-latency and high-reliability. Owing to the slowdown of Moore’s law, to avoid electronically-induced bottlenecks, we construct an FSO switch network and experimentally evaluate the feasibility of ultrafast optical packet switch architecture based on polarization-independent plomb lanthanum zirconate titanate (PLZT) switch without buffering. The bit error ratio of 160 Gbps ([Formula: see text]) data was validated based on measurements while still preserving the sub-us latency metrics ([Formula: see text] ns). The experimental results may offer a significant reference for FSO communication and network.

Architecture and Performance Evaluation of a Novel Optical Packet Switch with Input Concentrators

In this paper, we propose a novel optical packet switch (OPS) architecture with input concentrators, which employ multi-input single-output optical buffers to aggregate all the incoming traffic into a small size switching fabric. Accordingly, the physical size, the number of the needed wavelength converters, and the economic cost of the total OPS node are decreased dramatically. However, the deployment of input concentrators introduces additional packet loss and delay, except from the contention at the switch output. A Markov model is presented to study the packet loss ratio (PLR) and average packet delay given by the input concentrators. The corresponding closed form expressions are given. The model also demonstrates that the system performance can be greatly improved by increasing the buffer size when the traffic load is not larger than 0.69315. The analytical values are compared with the simulation results. All the obtained results show that the proposed model provides satisfactory approximations under different network scenarios. Moreover, the economic cost savings of the proposed OPS node at the present time and its evolution as a function of time are also discussed in detail. The proposed architecture can also be applied in a packet enhanced optical transport network (OTN).

Large device to device communication network including airborne drones for emergency scenarios

AbstractIn the case of emergency scenarios communication infrastructure might be destroyed, impairing communication abilities in the disaster area. In such situation device‐to‐device (D2D) communication networking plays an essential role to overcome the communication loss. To provide a reliable communication network, D2D devices are combined with airborne drones. The D2D devices provide a relay service while being able to transmit their own data. The airborne drones offer additional relay functionality and provide considerably reduced latency compared with D2D communication networks without any airborne drones. In this article, we will illustrate a large dynamic communication network (LDCN) and demonstrate its feasibility for even more than 64 000 D2D communication devices in the case of realistic channel conditions including path loss and fading. It will be shown that the illustrated LDCN is truly infrastructure‐less, that is, no infrastructure or backbone or base station functionality need to be reinstalled. Therefore, the airborne drones do not take over any coordination services. The illustrated LDCN has a simple packet switching architecture and since all communication is localized it is robust and fully flexible. In addition, no specific radio interface or preferred multiple access scheme such as code division multiple access or time division multiple access are required.

A novel reconfigurable router for QoS guarantees in real-time NoC-based MPSoCs

Abstract This paper presents a proposal and implementation of a multi-mode full-reconfigurable router for Network-on-Chip (NoC). First, the router supports a hybrid packet-switching architecture that is dynamically reconfigurable to exchange between wormhole and virtual cut-through switching schemes at run-time. Therefore, it reaches a higher average performance than wormhole switching, while decreasing the implementation cost in comparison with the virtual cut-through switching. Second, the router is equipped a Quality-of-Services (QoS)-driven arbiter. Therefore, the proposed solution not only guarantees the guaranteed-throughput service without reserving resources but also enhances the average performance for the best-effort service by using network resources efficiently based on the priority inheritance arbitration mechanism. Third, the router is enhanced with the dynamically deadline-aware rerouting mechanism. In contention situation, the router can configure the routing computation unit to reroute the packet to another path so as to reduce the waiting interval of the blocked packets. The router was designed at the Register Transfer Level and modeled using VHDL language and then synthesized with Xilinx Virtex-7 FPGA technology. The experimental results prove that the proposed router is reliable and can improve the average performance of different QoS loads significantly compared with the generic routers while the area and power overhead are acceptable.

Performance comparison between recirculating loop buffer-based optical packet switch architectures

Due to the high cabling complications and limited scalability, the Ethernet switching is not a well-suited technology for the next-generation data center systems (NGDCs). In designing of interconnects for NGDCs, the first step is to select an appropriate switching technology. The best solution to the problems faced by NGDCs is the use of optical switching technology in the core of data centers. In this paper, three recirculating loop buffer-based optical packet switches are discussed. The first two switch discussed in this paper were proposed in the recent past, and the third switch is proposed by the authors of this paper. In this paper, a performance comparison between the switches is performed by considering physical and network layer parameters. The obtained results presented in the paper show that the performance of our proposed switch is better in comparison with other switches.

An integrated hardware/software in Algeria Telecom access layers NGN model:MA5600T and C300M Shelfs MSAN’s solutions

The evolution of an existing network to the new structure will require a phased migration strategy aimed at minimising capital expenditure during the transition phase, while reaping the benefits early on. Any action taken during this transition step should simplify the network's evolution to the NGN packet-switched architecture. This work conducted the study of the migration of PSTN networks to NGN Optical Fiber networks, its configuration and implementation of Smart AX MA5600T HUAWEI and C300M ZTE Shelfs MSANs solutions. Full Text: PDF ReferencesAtzwanger. Joachim, Multi-Service Access Node: Soft switches ITSF ROM, Telekom Austria (2009). DirectLink B. Handley, Multi-Service Access Nodes (MSANs): Gateways to Next-Generation Network (NGN), Fujitsu scientific & technical journal 42, 4, 432-438 (Oct 2006). DirectLink D. C. Eddine, Presentation MSAN type ZTE (MSG 5200 & C300M). DirectLink DSM-2128 IP DSLAM and MSAN (Multi Service Access Node), Smart solutions for smart networks (Sept 2018). DirectLink Huawei, MSAN MA5600T Basic Configuration, Issue 1-00 (2010). DirectLink Huawei, SmartAX MA5600T/MA5603T/MA5608T Multiservice Access Module: Commissioning and Configuration Guide V800R015C10, Issue 01 (2014-10-30). DirectLink Loïc. Debourdeau, Le Protocole SIP (Session Initiation Protocol), RFC2543. DirectLink Sennouni. Hassane, Implementation de la solution Dual Homing pour la diversification des liens Uplinks du MSAN MA5600T au sein du reseaux metro Ip d'IAM, Ecole Nationale des Sciences Appliquées- Tanger (2014). DirectLink ZTE, ZXA10 C300M, Configuration Manual (CLI) (2012-10-20). DirectLink

Thermal-aware Test Scheduling Strategy for Network-on-Chip based Systems

Rapid progress in technology scaling has introduced massive parallel computing systems with multiple cores on the integrated circuit (IC), in which a flexible and scalable packet-switched architecture, Network-on-Chip (NoC), is commonly used for communication among the cores. However, technology scaling has also increased the susceptibility to internal defects in such systems. So, manufacturing tests of such multicore systems is crucial and this is a complex and time-consuming process. Due to stress on time-to-market, test engineers focus on the reduction of testtime and perform parallel tests of cores. Due to aggressive technology scaling into the nanometer regime, power consumption is also becoming a significant burden. Moreover, power consumption during manufacturing tests is more as compared to normal operation. In addition, peak power consumption is often significantly higher than the average power values. The consumed power leads to high temperature and creates hotspots, which in turn leads to failure of good parts, resulting in yield loss. Thermal safety during testing is an utmost challenging problem in NoC-based multicore systems, including three-dimensional NoC-based (3D NoC) multicore systems due to stacking of layers. This work proposes a preemptive test scheduling technique for NoC-based multicore systems to reduce the testtime by minimizing conflicts of resource usage. The preemptive test scheduling problem has been formulated using Integer Linear Programming (ILP). In this article, authors have also presented a thermal-aware test scheduling technique to test cores in 2D as well as 3D stacked NoC-based multicore systems using a Particle Swarm Optimization (PSO) based approach. To improve the solution further, several innovative augmentation techniques have been incorporated in the basic PSO. Experimental results highlight the effectiveness of the proposed method in reducing testtime and peak temperature under the power constraints and achieve a tradeoff between testtime and peak temperature.

A 1024-Port Optical Uni- and Multicast Packet Switch Fabric

Novel Data Center (DC) architectures based on resource disaggregation hold the potential to increase the resource utilization at a reduced energy and cost envelope, imposing, however, significant challenges in the underlying DC network infrastructure that has to provide high-radix and high-bandwidth connectivity, while maintaining sub-μs latency. At the same time, the explosive growth of AI applications has transformed the traffic profiles on the majority of DC workloads calling for support of advanced network functionalities, such as multicasting. In this direction, we scale-up the Hipoλaos optical packet switch architecture to a thousand-port layout, at the same time upgrading its functionality to allow latency-free intra-tray multicasting. The feasibility of a 10.24-Tb/s capacity switch fabric with a 10-Gb/s line rate in a 1024-port configuration, with four-packet buffering capacity is experimentally demonstrated, revealing error-free performance with <3.4-dB power penalty. Optical multicasting to up-to five nodes is also experimentally validated at 10 Gb/s, with a power penalty variation of less than 1 dB between the different output ports, while multicast operation across the whole required spectral range of a 1024-port switch is investigated, utilizing pairs of wavelengths with different channel spacing. Network-level analysis of the 1024-port Hipoλaos switch revealed sub-μs p90-latency and ∼85% throughput, for the unicast case, when utilizing a two-packet-buffer design. Finally, the simulation model was extended to support the Hipoλaos multicast friendly layout, revealing up to 4250% throughput improvement, as compared to the conventional layout, while maintaining sub-μs latency.

Thermal-Aware Application Mapping Strategy for Network-on-Chip Based System Design

Rapid progress in technology scaling makes transistors smaller and faster over successive generations, and consequently core count in a system gets increased. However, transistor power consumption no longer scales commensurately. Increased power density calls for better thermal safety of the multi-core systems, in which a flexible and scalable packet-switched architecture — Network-on-Chip (NoC) — is commonly used for communication among the cores. This paper proposes a strategy to increase the thermal safety of NoC-based systems by a graceful decrease in communication cost and an Integer Linear Programming (ILP) formulation to deal with the problem. To overcome huge computational overhead of ILP, another solution strategy, based on meta-heuristic technique, Particle Swarm Optimization (PSO) is also proposed. Several innovative augmentations have been introduced into the basic PSO to generate better quality solutions. A thermal-aware mapping heuristic is proposed to generate some intelligent solutions, which become a part of the initial population in the PSO. A trade-off has been established between communication cost and peak temperature of the die. Experiments on Big data and Graph analytical workloads are reported. The results obtained are better than those of many contemporary approaches, reported in the literature.

Birkhoff-Von Neumann Switch Based on Greedy Scheduling

It is important to develop high performance packet switches that are highly scalable. Among the popular solutions are input queued (IQ) switches and load balanced Birkhoff-von Neumann (LB-BvN) switches. However, both solutions have their drawbacks. Switch configuration pattern in IQ switches is random which can limit the supported port speed. On the other hand, LB-BvN switches require two switching stages which increase the overall cost. Also, some LB-BvN solutions suffer from the packet out of sequence problem. In this paper, we propose a novel packet switch architecture that combines the best properties of the IQ and LB-BvN switches and eliminates their drawbacks.

Enabling High-Performance SMART NoC Architectures Using On-Chip Wireless Links

Traditional network-on-chip (NoC) interconnects follow conventional packet switching architectures that require multiple cycles to traverse each router hop. In addition, commonly used NoCs lack low-latency multicast replication and acknowledgment aggregation mechanisms that are required to efficiently handle the collective communication requirements exhibited by many modern applications. To address these issues, the single-cycle multihop asynchronous repeated traversal (SMART) NoC architecture is proposed. By using an efficient router-bypass mechanism, the SMART NoC enables single-cycle data transfers even between physically distant on-chip routers. However, enabling single-cycle hops over long metal wires restrict the achievable clock frequency of the system. In other words, increasing the NoC clock frequency lowers the number of hops that can be bypassed in a single cycle in a fully wireline SMART NoC. In this paper, we demonstrate that by integrating on-chip wireless links, a novel look-ahead bypass-request mechanism and a congestion-free broadcast routing methodology, it is possible to enable low-latency and energy efficient data transfers in the SMART NoC even when the system is designed with high clock frequencies. For the various applications considered in this paper, the wireless-enabled SMART NoC achieves on an average 41% reduction in message latency compared to the wireline SMART NoC. This network level improvement translates into 20% savings in full system energy-delay product.

Packet Loss Rate Differentiation in slotted Optical Packet Switching OCDM/WDM

We propose a multi-class mechanism for Optical Code Division Multiplexing (OCDM), Wavelength Division Multiplexing (WDM) Optical Packet Switch (OPS) architecture capable of supporting Quality of Service (QoS) transmission. OCDM/WDM has been proposed as a competitive hybrid switching technology to support the next generation optical Internet. This paper addresses performance issues in the slotted OPS networks and proposed four differentiation schemes to support Quality of Service. In addition, we present a comparison between the proposed schemes as well as, a simulation scheduler design which can be suitable for the core switch node in OPS networks. Using software simulations the performance of our algorithm in terms of losing probability, the packet delay, and scalability is evaluated.

A scalable packet-switch architecture based on OQ NoCs for data center networks

Data Center switches need guarantee high throughput, resiliency and scalability for large-scale networks with constantly floating requirements. Multistage packet switches have been a pervasive solution to implement high-capacity Data Center Networks (DCNs) switches and routers. Yet, classical multistage switching architectures with their Space-Memory variants have shown limited performance. Most proposals prove either too complex to implement or not cost effective. In this paper, we present a highly scalable packet-switch for the DCN environment, in which we exploit the Network-on-Chip (NoC) design paradigm to replace the single-hop crossbars with multi-hop Switching Elements (SEs). In particular, we describe a three-stage switch with Output-Queued Unidirectional NoCs (OQ-UDN) in the central stage of the Clos-network. The design has several advantages over conventional multistage switches. First, it uses a simple Round-Robin (RR) packet dispatching scheme and avoids the need for complex and costly input modules. Besides, it offers better load balancing, a pipelined scheduling and more path-diversity. We assess the performance of the switch in terms of throughput, end-to-end latency and blocking probability using Markov chain analysis, and we propose an analytical model that integrates the various design parameters. Through extensive simulations, we show that the switching architecture achieves high performance under different types of traffic, and that both the analytical and experimental results correlate over wide range of evaluation settings.

Synchronous optical packet switch architecture with tunable single and multi-channels wavelength converters

Abstract In this paper, we propose a bufferless synchronous optical packet switch (OPS) architecture named the Limited-range wavelength conversion with Dynamic Pump-wavelength Selection (LDPS) architecture. LDPS is equipped with a dedicated limited-range wavelength converters (LRWCs, and a shared pool of parametric wavelength converters (PWCs) with dynamic pump-wavelength selection (DPS). The adoption of hybrid conversion types in the proposed architecture aims at improving the packet loss rate (PLR) compared to conventional architecture with single conversion types, while reducing (or at least maintaining) the conversion distance ( d ) of used wavelength converters. Packet contention in the proposed architecture is resolved using the first available algorithm (FAA) and the dynamic pump-wavelength selection algorithm (DPSA). The performance of the proposed architecture is compared to two well-known conventional architectures; namely, the LRWC architecture that uses dedicated LRWCS for each input wavelength, and the DPS architecture that uses a shared pool of dynamic pump-wavelength converters (PWCs). Simulation results show that, for the same value of d , the new architecture reduces the PLR compared to the LRWC architecture by up to 40 % and 99.7 % for traffic loads, 0.5 and 1; respectively. In addition, for d = 1 , the new architecture reduces the PLR compared to the DPS architecture by up to 10 % and 99.3 % for traffic loads, 0.5 and 1; respectively.

Capturing Video Stream Audience Over IP Networks

In recent years, the transmission of audiovisual content presented substantial growth in the context of ondemand delivery, made possible through networks based on Internet Protocol, IP. This increase, boosted by internet access omnipresence and new consumption habits of this content, makes this category of communication to be continuously rivaled with traditional broadcasting technologies of Television (TV) signals. Thus, developing techniques to assess the efficacy and risks that the use of IP networks for this purpose imposes becomes relevant. Moreover, while for the named Broadcast TV has technical mechanisms that ensure the quality of this communication are well established, the same does not occur for video stream over IP, or IP Stream. The reason for this is that, for one of them, its technology is equipped with quality guarantees based on a circuit-switching operation in a connection-oriented systematic. While the other, once the web is considered, is unable to ensure quality due to its packetswitching architecture. And this is what sets it as a model called 'best effort' which, besides the features to allow channel sharing and systems interconnection, enables precisely what makes its increase in its use for audiovisual transmission, the applicationoriented provision. Thereby attending the consumer’s desire for on demand content, subsequently amplifies the role of what and who is on the edge, ultimately placing the user as protagonist. In this IP scenario, it is underlined the lack of mechanisms, related to the Internet, capable of recording two technical parameters that influence the commercial chain that sustains this entire ecosystem, they are: availability and audience. Keeping this in mind and with the goal of evaluating this new method for audiovisual offering, this work has developed methodologies to acquire such information at this consumption edge. And this has been accomplished through the construction of a software tool. It was implemented as an extension to one of the most used browsers, Google Chrome, to capture the audience of Internet videos on the leading supplier of videos exists today, Google's YouTube. In this work, the abstractions of considerations around the Quality of Service (QoS) concept, is proposed to be interpreted as a measure of Quality of Experience (QoE) assimilated from time viewed compared against the total time of a video. This justification is founded on the concept that quality translates into a particular subjectivity for each user and their individual expectations, so a measure of time is shown to be an effective thermometer. This effectiveness is justified by a principle consolidated within TV broadcast for decades, audience measurement. Thus, the construction of something analogous to the 'People's meter' in a similar scheme of 'Television Rating Points', TRP, running to capture of information in order to convey assertiveness to all stakeholders involved in this new delivery method. Keywords— IP Stream, Audience, Connection Availability, Quality of Service (QoS), Quality of Experience (QoE), Software Development.

Multiple-combinational-channel: A network architecture for workload balance and deadlock free

As the number of cores in chip multiprocessors (CMPs) increases rapidly, network-on-chips (NoCs) have become the major role in ensuring performance and power scalability. In this paper, we propose multiple-combinational-channel (MCC), a load balancing and deadlock free interconnect network, for cache-coherent non-uniform memory accessing (CC-NUMA). In order to make load more balancing and reduce power dissipation, we combine low usage channels and make high usage channels independent and wide enough, since messages transmitted over NoC have different widths and injection rates. Furthermore, based on the in-depth analysis of network traffic, we summarize four traffic patterns and establish several rules to avoid protocol-level deadlocks. We implement MCC on a 16-core CMPs, and evaluate the workload balance, area, power and performance using universal workloads. The experimental results show that MCC reduces nearly 21% power than multiple-physical-channel with similar throughput. Moreover, MCC improves 10% performance with similar area and power, compared to packet-switching architecture with virtual channels.

English

In this paper, the packet switching architecture with output queuing is used. Here the switch is internally non-blocking, but if packets destined to same outputs, output blocking will occur and (even if there are output queues) has a capacity of N*N2.An exact model of the switch has been developed which can be used to determine the blocking performance of the switch and obtain both its throughput and packet loss characteristics. In this architecture, each line card is connected by a dedicated point to point link to the central switch fabric. Two structures can be classified as Centralized and Distributed. Buffer arrangements are also categorized into output queued and combined input- output queued switches and hardware complexity of OQ, VOQ are also discussed

Physical layer analysis of AWG based optical packet switch architecture

Optical packet switching is the next generation switching technique in conjunction with mature electronic switching. In optical packet switching, the core router plays an important role in the routing and buffering of packets. In recent past, AWG based optical router are proposed and heavily investigated due to its very low insertion loss and very simple wavelength dependent routing pattern. In this paper, a further modification in an AWG based optical packet switch is proposed. These modifications improve the signal reception quality at the output. Power budget analysis is presented to evaluate the buffer capacity. As a physical layer parameters, the minimum switch power is evaluated using the mathematical model and at the BER level of 10−9 the maximum buffering capacity is evaluated. Finally, simulation results are presented in terms of network layer parameters, packet loss probability and average delay. The packet loss probability is as low as 10−7 well under acceptable limits.

In-Band Label Extractor Based on Cascaded Si Ring Resonators Enabling 160 Gb/s Optical Packet Switching Modules

Photonic integration of optical packet switching modules is crucial to compete with existing electronic switching fabrics in large data center networks. The approach of coding the forwarding packet information in an in-band label enables a spectral-efficient and scalable way of building low-latency large port count modular optical packet switching architecture. We demonstrate the error-free operation of the four in-band label extraction from 160 Gb/s optical data packets based on photonic integrated silicon-on-insulator ring resonators. Four low-loss cascaded ring resonators using the quasi-TM mode are used as narrowband filters to ensure the detection of four optical labels as well as the error-free forwarding of the payload at limited power penalty. Due to the low-loss and less-confined optical quasi-TM mode the resonators can be very narrowband and have low insertion loss. The effect of the bandwidth of the four ring resonators on the quality of the payload is investigated. We show that using four rings with 3dB bandwidth of 21 pm and only an insertion loss of 3 dB, the distortion on the payload is limited (<;1.5 dB power penalty), even when the resonances are placed very close to the packet's central wavelength. We also investigate the optical power requirements for error-free detection of the label as function of their spectral position relative to the center of the payload. The successful in-band positioning of the labels makes this component very scalable in amount of labels.