Packet Processing Engines Research Articles

Corrections to: "Green Networking With Packet Processing Engines: Modeling and Optimization"

Presents corrections to the paper, “Green networking with packet processing engines: Modeling and optimization,” (Bolla, R., et al), IEEE/ACM Trans. Netw., vol. 22, no. 1, pp. 110–123, Feb. 2014.

An Improved 30 Gbps-Class Large-Capacity Packet Processing Method Using Core Isolation Technology

With the spread of 5G services and the development of IoT technology, network traffic for information delivery is increasing in capacity. As network traffic increases, cyber threats also increase, resulting in an increasing importance on traffic analysis. The existing packet processing engine generates a signature by analyzing the characteristics of the attack after the occurrence of suspicious traffic, and based on this, it is difficult to properly respond to new and variant attack traffic because a manual response method is performed to detect the same attack. In addition, even during a network operation, only analysis results generated by passive filtering appear, and when abnormal or suspicious traffic is observed, the quality of the report is often affected by the analysis capability of the administrator. The packet processing method proposed in this paper applies the core isolation method to the NUMA structure applied to the existing 20 Gbps packet processing engine to increase the accessibility of the existing NUMA memory structure and lower the packet drop rate to enable high-capacity 30 Gbps traffic processing. Using the proposed processing engine, it is possible to determine the degree of possibility of abnormal traffic, preferentially by a quick analysis of suspicious traffic rather than a detailed analysis of traffic.

Batch-scheduling Data Flow Graphs with Service-level Objectives on Multicore Systems

Data flow graphs are a popular program representation in machine learning, big data analytics, signal processing, and, increasingly, networking, where graph nodes correspond to processing primitives and graph edges describe control flow. To improve CPU cache locality and exploit data-level parallelism, nodes usually process data in batches. Batchy is a scheduler for data flow graph based packet processing engines, which uses controlled queuing to reconstruct fragmented batches inside a data flow graph in accordance with strict Service-Level Objectives (SLOs). Earlier work showed that Batchy yields up to 10x performance improvement in real-life use cases, thanks to maximally exploiting batch processing gains. Batchy, however, is fundamentally restricted to single-threaded execution. In this paper, we generalize Batchy to parallel execution on multiple CPU cores. We extend the analytical model to the parallel setting and present a primal decomposition framework, where each core runs an unmodified Batchy controller to schedule batch-processing on a subset of the data flow graph, orchestrated by a master controller that distributes the delay-SLOs across the cores using subgradient search. Evaluations on a real software switch provide experimental evidence that our decomposition framework produces 2.5x performance improvement while accurately satisfying delay SLOs that are otherwise not feasible with single-core Batchy.

Enfoque de alta granularidad para el procesamiento de paquetes en red para aplicaciones tolerantes a la latencia con CUDA (Corvyd)

En este artículo, estamos interesados en investigar el procesamiento por lotes basado en capas para la inspección de paquetes de red en paralelo. Estudios anteriores de inspección de paquetes basada en GPU [1], [2] y [3] lograron ganancias de rendimiento a través de algunas innovaciones, los más importantes se basaron en la latencia de acceso a la memoria ocultando [4] que no es monopolizado por los sistemas GPU. Los sistemas de procesamiento de paquetes en cualquier hardware también deben usar alguna forma de bypass del kernel para evitar la sobrecarga asociada con las pilas de red de propósito general [4] y [6]. Estos estudios producen un rendimiento dramáticamente mejor que sus predecesores. Por el contrario, el enfoque de este proyecto se limita estrictamente a un conjunto de mejoras algorítmicas. El procesamiento por lotes es común a cualquier implementación paralela de alto rendimiento. Este proyecto propone explorar un procesamiento más granular basado en capas que divide los paquetes a través de múltiples rondas de programación para maximizar la homogeneidad del lote y minimizar la divergencia de la GPU. Esto aumentará significativamente la sobrecarga para procesar un solo paquete, además de aumentar la latencia a medida que se requerirá más almacenamiento en búfer, pero este enfoque tiene el potencial de mejorar el rendimiento en cargas de trabajo de IP altamente erráticas, donde el trabajo previo ha favorecido fuertemente las cargas de trabajo uniformes como ejemplos de PoC minimizados para representar sistemas que probablemente tendrían un bajo rendimiento en el campo [4],[5], y [6].

New Alternatives to Optimize Policy Classifiers

Growing expressiveness of services increases the size of a manageable state at the network data plane. A service policy is an ordered set of classification patterns (classes) with actions; the same class can appear in multiple policies. Previous studies mostly concentrated on efficient representations of a single policy instance. In this work, we study space efficiency of multiple policies, cutting down a classifier size by sharing instances of classes between policies that contain them. In this paper we identify conditions for such sharing, propose efficient algorithms and analyze them analytically. The proposed representations can be deployed transparently on existing packet processing engines. Our results are supported by extensive evaluations.

P4-To-VHDL: Automatic generation of high-speed input and output network blocks

High-performance embedded architectures typically contain many stand-alone blocks which communicate and exchange data; additionally a high-speed network interface is usually needed at the boundary of the system. The software-based data processing is typically slow which leads to a need for hardware accelerated approaches. The problem is getting harder if the supported protocol stack is rapidly changing. Such problem can be effectively solved by the Field Programmable Gate Arrays and high-level synthesis which together provide a high degree of generality. This approach has several advantages like fast development or possibility to enable the area of packet-oriented communication to domain oriented experts. However, the typical disadvantage of this approach is the insufficient performance of generated system from a high-level description. This can be a serious problem in the case of a system which is required to process data at high packet rates. This work presents a generator of high-speed input (Parser) and output (Deparser) network blocks from the P4 language which is designed for the description of modern packet processing devices. The tool converts a P4 description to a synthesizable VHDL code suitable for the FPGA implementation. We present design, analysis and experimental results of our generator. Our results show that the generated circuits are able to process 100 Gbps traffic with fairly complex protocol structure at line rate on Xilinx Virtex-7 XCVH580T FPGA. The approach can be used not only in networking devices but also in other applications like packet processing engines in embedded cores because the P4 language is device and protocol independent.

Dynamic Router Performance Control Utilizing Support Vector Machines for Energy Consumption Reduction

In this paper, we propose a machine-learning-based novel dynamic performance control method for routers that supports several performance levels. The method utilizes support vector machine (SVM) to determine performance level change points. We utilize a traffic normalization technique with a corresponding performance threshold that allows us to apply the same SVM to different traffic volumes. This technique shortens the learning process for control. Several experiments on real Internet traffic data sequences prove that the method yields higher energy efficiency than conventional methods, that is, our previously proposed frequency decomposition-based method and a conventional traffic prediction method based on auto-regressive moving average model with optimal parameter values given by Akaike’s information criterion. We also evaluate the impact of several key parameters such as traffic measurement interval and the number of packet processing engines. The results clarify the proper ranges of parameter values that attain significant power reductions while keeping packet loss to acceptable levels.

Adaptive Frequency Control of Packet Processing Engines in Telecommunication Networks

This letter addresses the problem of energy saving in packet processing engines of network devices. The case of a single traffic queue is considered. The aim is to guarantee a delay constraint while adjusting the power consumption and the queue service rate. A feedback control is used, which is adaptive to the statistical behavior of traffic sources. The feedback is exploited by a heuristics and an optimal control technique. The latter approach, in particular, is capable of driving indications about which system conditions (statistical parameters and buffer size) are potentially more sensitive to energy saving.

Green Networking With Packet Processing Engines: Modeling and Optimization

With the aim of controlling power consumption in metro/transport and core networks, we consider energy-aware devices able to reduce their energy requirements by adapting their performance. In particular, we focus on state-of-the-art packet processing engines, which generally represent the most energy-consuming components of network devices, and which are often composed of a number of parallel pipelines to “divide and conquer” the incoming traffic load. Our goal is to control both the power configuration of pipelines and the way to distribute traffic flows among them. We propose an analytical model to accurately represent the impact of green network technologies (i.e., low power idle and adaptive rate) on network- and energy-aware performance indexes. The model has been validated with experimental results, performed by using energy-aware software routers loaded by real-world traffic traces. The achieved results demonstrate how the proposed model can effectively represent energy- and network-aware performance indexes. On this basis, we propose a constrained optimization policy, which seeks the best tradeoff between power consumption and packet latency times. The procedure aims at dynamically adapting the energy-aware device configuration to minimize energy consumption while coping with incoming traffic volumes and meeting network performance constraints. In order to deeply understand the impact of such policy, a number of tests have been performed by using experimental data from software router architectures and real-world traffic traces.

Instruction set architectural guidelines for embedded packet-processing engines

This paper presents instruction set architectural guidelines for improving general-purpose embedded processors to optimally accommodate packet-processing applications. Similar to other embedded processors such as media processors, packet-processing engines are deployed in embedded applications, where cost and power are as important as performance. In this domain, the growing demands for higher bandwidth and performance besides the ongoing development of new networking protocols and applications call for flexible power- and performance-optimized engines. The instruction set architectural guidelines are extracted from an exhaustive simulation-based profile-driven quantitative analysis of different packet-processing workloads on 32-bit versions of two well-known general-purpose processors, ARM and MIPS. This extensive study has revealed the main performance challenges and tradeoffs in development of evolution path for survival of such general-purpose processors with optimum accommodation of packet-processing functions for future switching-intensive applications. Architectural guidelines include types of instructions, branch offset size, displacement and immediate addressing modes for memory access along with the effective size of these fields, data types of memory operations, and also new branch instructions. The effectiveness of the proposed guidelines is evaluated with the development of a retargetable compilation and simulation framework. Developing the HDL model of the optimized base processor for networking applications and using a logic synthesis tool, we show that enhanced area, power, delay, and power per watt measures are achieved.

Quantitative analysis of packet-processing applications regarding architectural guidelines for network-processing-engine development

This paper presents a simulation-based profile-driven quantitative analysis of packet-processing applications. In this domain, demands for increasing the performance and the ongoing development of network protocols both call for flexible and performance-optimized engines. Based on the achieved profiling results, we introduce platform-independent analysis that locates the performance bottlenecks and architectural challenges of a packet-processing engine. Finally based on these results, we extract helpful architectural guidelines for design of a flexible and high-performance embedded processor that is optimized for packet-processing operations in high-performance and cost-sensitive network embedded applications.

Design and performance evaluation of a Programmable Packet Processing Engine (PPE) suitable for high-speed network processors units

In this paper, we present a Programmable Packet Processing Engine suitable for deep header processing in high-speed networking systems. The engine, which has been – fabricated as part of a complete network processor, consists of a typical RISC-CPU, whose register file has been modified in order to support efficient context switching, and two simple special-purpose processing units. The engine can be used in a number of network processing units (NPUs), as an alternative to the typical design practice of employing a large number of simple general purpose processors, or in any other embedded system designed to process mainly network protocols. To assess the performance of the engine, we have profiled typical networking applications and a series of experiments were carried out. Further, we have compared the performance of our processing engine to that of two widely used NPUs and show that our proposed packet-processing engine can run specific applications up to three times faster. Moreover, the engine is simpler to be fabricated, less complex in terms of hardware complexity, while it can still be very easily programmed.

Evaluating network processing efficiency with processor partitioning and asynchronous I/O

Applications requiring high-speed TCP/IP processing can easily saturate a modern server. We and others have previously suggested alleviating this problem in multiprocessor environments by dedicating a subset of the processors to perform network packet processing. The remaining processors perform only application computation, thus eliminating contention between these functions for processor resources. Applications interact with packet processing engines (PPEs) using an asynchronous I/O (AIO) programming interface which bypasses the operating system. A key attraction of this overall approach is that it exploits the architectural trend toward greater thread-level parallelism in future systems based on multi-core processors. In this paper, we conduct a detailed experimental performance analysis comparing this approach to a best-practice configured Linux baseline system.We have built a prototype system implementing this architecture, ETA+AIO (Embedded Transport Acceleration with Asynchronous I/O), and ported a high-performance web-server to the AIO interface. Although the prototype uses modern single-core CPUs instead of future multi-core CPUs, an analysis of its performance can reveal important properties of this approach. Our experiments show that the ETA+AIO prototype has a modest advantage over the baseline Linux system in packet processing efficiency, consuming fewer CPU cycles to sustain the same throughput. This efficiency advantage enables the ETA+AIO prototype to achieve higher peak throughput than the baseline system, but only for workloads where the mix of packet processing and application processing approximately matches the allocation of CPUs in the ETA+AIO system thereby enabling high utilization of all the CPUs. Detailed analysis shows that the efficiency advantage of the ETA+AIO prototype, which uses one PPE CPU, comes from avoiding multiprocessing overheads in packet processing, lower overhead of our AIO interface compared to standard sockets, and reduced cache misses due to processor partitioning.

The wireless edge router: A network processor-based packet data serving node for a CDMA2000* network

A network processing unit (NPU) is increasingly becoming the processor of choice for building custom packet-processing gateways. In this paper, we present an NPU-based design and architecture for a packet data serving node (PDSN) in a CDMA2000∗ network. A PDSN is a packet-processing gateway that interfaces between the Internet and the wireless radio access network to provide packet data services to mobile users. We map the different functions of the PDSN onto the packet-processing engines and the core processor of an NPU. This involves a complete separation of the control plane, which is implemented in the core processor, and the data plane, which is implemented using a multistage packet pipeline mapped onto the packet-processing engines. We describe resource allocation schemes for packet buffering and processing and also a flexible communication method with the core processor. The mechanisms described in the paper are general enough to be used to implement other NPU-based packet-processing gateways. We also present a prototype implementation of the PDSN on an NPU and show its superiority to commercial products by means of measurement experiments.

Scaling network services using programmable network devices

The NEon system offers an integrated approach to architecting, operating, and managing network services. NEon uses policy rules defining the operation of individual network services and produces a unified set of rules that generic packet-processing engines enforce.

An IPv6 enabled packet engine design for home/SOHO routers

Due to the diversity of internet applications and services, traditional software-based networking devices may not be sufficient to afford the processing load imposed by the services. One example is the mixed-version IP environment in which routers must handle the IPv4/IPv6 translation while keeping the IP processing at the line speed. In this paper, we present our work for the design of a protocol optimised packet processing engine that provides common IP services and mixed-version translations. This silicon is written in VHDL and is tested in a Xilinx Vertex II FPGA development board.

Packet Processing Acceleration With a 3-Stage Programmable Pipeline Engine

In this letter, we present the architecture and implementation of a novel, 3-stage processing engine, suitable for deep packet processing in high-speed networks. The engine, which has been fabricated as part of a network processor, comprises of a typical RISC core and programmable hardware. To assess the performance of the engine, experiments with packets of various lengths have been performed and compared against the IXP1200 network processor. The comparison has revealed that for the case study shown in this letter, the proposed packet-processing engine is up to three times faster. Moreover, the engine is simple to be fabricated, less expensive than the corresponding hardware cores of IXP1200 and can be easily programmed for different networking applications.

ETA: experience with an intel xeon processor as a packet processing engine

Server-based networks have well-documented performance limitations. These limitations outline a major goal of Intel's embedded transport acceleration (ETA) project, the ability to deliver high-performance server communication and I/O over standard Ethernet and transmission control protocol/Internet protocol (TCP/IP) networks. By developing this capability, Intel hopes to take advantage of the large knowledge base and ubiquity of these standard technologies. With the advent of 10 gigabit Ethernet, these standards promise to provide the bandwidth required of the most demanding server applications. We use the term packet processing engine (PPE) as a generic term for the computing and memory resources necessary for communication-centric processing. Such PPEs have certain desirable attributes; the ETA project focuses on developing PPEs with such attributes, which include scalability, extensibility, and programmability. General-purpose processors, such as the Intel Xeon in our prototype, are extensible and programmable by definition. Our results show that software partitioning can significantly increase the overall communication performance of a standard multiprocessor server. Specifically, partitioning the packet processing onto a dedicated set of compute resources allows for optimizations that are otherwise impossible when time sharing the same compute resources with the operating system and applications.

Hot interconnects 10 - thinking beyond the internet

Microcomputers and their users rely on interconnects to communicate. At the Hot Interconnects 10 conference, which took place 21 to 23 August 2002 at Stanford University, designers and architects from universities and companies met to discuss new technologies for high-performance switches, routers, and packet processing engines. These technologies enable computers and users to seamlessly exchange data over the Internet. They also transport data between multi-processors, interconnect clusters of workstations, and implement the core switching in storage area networks.