Packet Forwarding Engines Research Articles

CSVRF: A CAM‐based popularity‐aware egress group‐caching scheme for SVRF‐based packet forward engines

AbstractAs a key component of high‐performance switches and routers, the packet forwarding engine (PFE) is mainly responsible for selecting the appropriate output port for tens of thousands of packets within an extremely short time frame. However, the performance of PFE is determined by the selected group membership algorithm. This paper puts forth a hybrid strategy–caching scalar‐pair and vectors routing and forwarding (CSVRF), consisting of virtual output port bitmap caching (VOPBC) and fractional‐N SVRF to address major multicast forwarding issues such as scalability by using content addressable memory. In CSVRF, a virtual output port bitmap cache is introduced, which includes the most popular combinations of output port bitmap and divides the big scalar‐pair into N sub‐groups to achieve parallel compute and the reusability of less bit‐length prime. The results demonstrate that the memory space and the forwarding latency are effectively reduced compared with previous work. In space efficiency, it only required 10% memory space compared with the original SVRF/fractional‐N SVRF, decreased 10% memory usage compared with pure VOPBC and nearly improved 1 to 4 orders of magnitude of packet processing time compared with the original SVRF and the fractional‐N SVRF respectively.

P3FA: Unified Unicast/Multicast Forwarding Algorithm for High-Performance Router/Switch

High-performance multicast packet switching technologies are evolving to meet the growing demand for scalability on the Internet and datacenters, etc. Implementing a high-performance switch/router relies on a polynomial-time group membership query algorithm within the Packet Forwarding Engines (PFEs) to determine whether a packet is forwarded through an egress. Among these, Bloom filter (BF)-based and Residue Number System (RNS)-based are being considered as two representatives of the membership query algorithms. However, both approaches suffer from some fatal weaknesses such as false-positive probability and time inefficiencies, especially for a carrier-grade PFE with high port-density features. According to similar properties of the RNS, we propose a simplified forwarding algorithm in this paper, named Per-Port Prime Filter Array (P3FA). The simulation results indicate that the P3FA can significantly improve space efficiencies under specific lower egress-diversities conditions. Under the same space constraints, P3FA improves multicast and unicast time efficiency by 1 to 4 orders of magnitude in the port-density 16–1024 range compared to previous works. Although it comes at the expense of hardware cost, it is still acceptable compared to recently improved previous work.

Scalable multicast control-plane for optical packet forwarding engines: A multiway SVRF approach

In control-plane of optical packet forwarding engines (OPFEs), the group-membership query algorithm determines the egress through which a packet should be forwarded. To implement a high-performance multicast-enabled switch/router, a super-fast group-membership query algorithm is the key element within the PFEs which require the following essential properties: high link-bandwidth, high port-density, high forwarding speed, high scalability, and affordable cost. Current group-membership query approaches such as Bloom filter (BF) and Scalar-Pair Vectors Routing and Forwarding (SVRF) still suffer from serious weaknesses in terms of the space/time inefficiency, false-positive error, and low maintainability, etc. To accommodate these weaknesses, we propose an improved forwarding scheme–M-way Scaler-matrix and Vectors Routing and Forwarding (M-way SVRF) by re-examining the idea of the original SVRF. The M-way SVRF divides a ρ-bit port identifier into M-sub-blocks in the memory unit, thus element's keys belonging to distinct sub-blocks are able to reuse relatively smaller identical prime keys. Compared to previous works, simulation results show that the membership queries can be partitioned to leverage task parallelism, and better performance in the aspects of memory consumption and computational complexity, especially when the port-density of optical PFE is sufficiently high.

DH-SVRF: A Reconfigurable Unicast/Multicast Forwarding for High-Performance Packet Forwarding Engines

High-performance multicast-enabled packet forwarding engines (PFEs), as an essential component of high-end switches, use a polynomial-time membership query algorithm to determine which port(s) the data packet should be forwarded. The currently widely used query algorithm is Bloom Filter (BF), which has been proven to have many fatal flaws. Another error-free membership query algorithm includes Scalar-pair Vectors Routing Forwarding (SVRF), Fractional- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> Scalar-pair Vectors Routing Forwarding (Frac- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> SVRF), and the Per-Port Prime Filter Array (P <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> FA) also have some shortcomings in space and time efficiencies. In this paper, we proposed a hybrid strategy: Divaricate Heterogeneous SVRF (DH-SVRF) scheme, which based on the P <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> FA and Frac- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> SVRF, which randomly divides all member ships into <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> groups, and each group has the same structure and is independent of each other to obtain higher time efficiency and space utilization. Finally, we also discussed the selection of the optimal egress-diversity threshold. Through mathematical modeling and simulation, we validate that the proposed DH-SVRF scheme is superior to the SVRF/Frac <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-N</i> SVRF and traditional BF in terms of scalability, space utilization, and time efficiency in specific conditions such as appropriate egress-diversity thresholds.

Fractional-N SVRF Forwarding Algorithm for Low Port-Density Packet Forwarding Engines

High-performance multicast-enabled switches and routers are being constantly developed, which use a polynomial-time group membership query algorithm within the Packet Forwarding Engines (PFEs) to determine whether or not a packet is forwarded through a unique or multiple egress ports. Among these, Bloom filter (BF) and Scalar-pair Vectors Routing and Forwarding (SVRF) are being considered as two representations of the membership query algorithms. However, both approaches suffer from some fatal weaknesses such as space and time inefficiencies, especially for a carrier-grade PFE with high port-density feature. In order to solve these imperfections of SVRF, we propose an improved Fractional-N Scalar-matrix and Vectors Routing and Forwarding (Fractional- N SVRF) scheme based on re-examining the idea of the original SVRF. The Fractional- N SVRF preprocesses a scalar-matrix by dividing an n-element group into N sub-blocks, thus element' keys belonging to distinct sub-blocks and sub-scalars are allowed to reuse relatively smaller identical prime keys. Based on Fractional-N SVRF, membership queries can be partitioned to leverage task parallelism, therefore better performance is achieved in terms of memory consumption and computational complexity.

Advanced hashing schemes for packet forwarding using set associative memory architectures

Building a high performance IP packet forwarding (PF) engine remains a challenge due to increasingly stringent throughput requirements and the growing size of IP forwarding tables. The router has to match the incoming packet’s IP address against all entries in the forwarding table. The matching process has to be done at increasingly higher wire speed; hence, scalability and low power consumption are critical for PF engines. Various hash table based schemes have been considered for use in PF engines. Set associative memory can be used for hardware implementations of hash tables with the property that each bucket of a hash table can be searched in a single memory cycle. However, the classic hashing downsides, such as collisions and worst case memory access time have to be dealt with. While open addressing hash tables, in general, provide good average case search performance, their memory utilization and worst case performance can degrade quickly due to collisions (that lead to bucket overflows). The two standard solutions to the overflow problem are either to use predefined probing (e.g., linear or quadratic probing) or to use multiple hash functions. This work presents two new simple hash schemes that extend both aforementioned solutions to tackle the overflow problem efficiently. The first scheme is a hash probing scheme that is called Content-based HAsh Probing (CHAP). As the name suggests, CHAP, based on the content of the hash table, avoids the classical side effects of predefined hash probing methods (i.e., primary and secondary clustering phenomena) and at the same time reduces the overflow. The second scheme, called Progressive Hashing (PH), is a general multiple hash scheme that reduces the overflow as well. The basic idea of PH is to split the prefixes into groups where each group is assigned one hash function, then reuse some hash functions in a progressive fashion to reduce the overflow. Both schemes are amenable to high-performance hardware implementations with low overflow and constant worst-case memory access time. We show by experimenting with real IP lookup tables and synthetic traces that both schemes outperform other existing hashing schemes.

An 8$\,\times\,$8 InP Monolithic Tunable Optical Router (MOTOR) Packet Forwarding Chip

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> In this paper, we demonstrate single-channel operation of the first InP monolithic tunable optical router (MOTOR) chip designed to function as the packet forwarding engine of an all-optical router. The device has eight-input and eight-output ports and is capable of 40-Gb/s operation per port with bit-error rates below 1E-9. MOTOR integrates eight wavelength-tunable differential Mach–Zehnder semiconductor optical amplifier (SOA) wavelength converters with preamplifiers and a passive 8<formula formulatype="inline"><tex Notation="TeX">$\,\times\,$</tex> </formula>8 arrayed-waveguide grating router. Each wavelength converter employs a widely tunable sampled-grating distributed Bragg reflector (DBR) laser for efficient wavelength switching across the C band and other functions required for 40-Gb/s wavelength conversion. Active and passive regions of the chip are defined through a robust quantum well intermixing process to optimize the gain in the wavelength converters and minimize the propagation losses in passive sections of the chip. The device is one of the most complex photonic integrated circuits (PICs) reported to date, with dimensions of 4.25 mm<formula formulatype="inline"><tex Notation="TeX">$\,\times\,$</tex></formula>14.5 mm and more than 200 functional elements integrated on-chip. We demonstrate single-channel wavelength conversion and channel switching with this device using <formula formulatype="inline"><tex Notation="TeX">$2^{31}-1$</tex></formula> pseudorandom bit sequence (PRBS) data at 40 Gb/s. A power penalty as low as 4.5 dB was achieved with less than 2-W drive power per channel. </para>

A Novel Cache Architecture and Placement Framework for Packet Forwarding Engines

Packet forwarding is a memory-intensive application requiring multiple accesses through a trie structure. With the requirement to process packets at line rates, high-performance routers need to forward millions of packets every second with each packet needing up to seven memory accesses. Earlier work shows that a single cache for the nodes of a trie can reduce the number of external memory accesses. It is observed that the locality characteristics of the level-one nodes of a trie are significantly different from those of lower level nodes. Hence, we propose a heterogeneously segmented cache architecture (HSCA) which uses separate caches for level-one and lower level nodes, each with carefully chosen sizes. Besides reducing misses, segmenting the cache allows us to focus on optimizing the more frequently accessed level-one node segment. We find that due to the nonuniform distribution of nodes among cache sets, the level-one nodes cache is susceptible to high conflict misses. We reduce conflict misses by introducing a novel two-level mapping-based cache placement framework. We also propose an elegant way to fit the modified placement function into the cache organization with minimal increase in access time. Further, we propose an attribute preserving trace generation methodology which emulates real traces and can generate traces with varying locality. Performance results reveal that our HSCA scheme results in a 32 percent speedup in average memory access time over a unified nodes cache. Also, HSCA outperforms IHARC, a cache for lookup results, with as high as a 10-fold speedup in average memory access time. Two-level mapping further enhances the performance of the base HSCA by up to 13 percent leading to an overall improvement of up to 40 percent over the unified scheme.

Throughput increase in packet forwarding engines using adaptive block-selection scheme

We propose a new approach for using the block-selection scheme to increase the search throughput in a multi-block TCAM-based packet forwarding engine. While the existing methods try to counter and forcibly balance the inherent bias of the Internet traffic, our method takes advantage of it hence improving flexibility of table management and scalability towards high rates of change in traffic bias. This approach also offers higher throughput than the current art.

Reconfigurable memory architecture for scalable IP forwarding engines

In this paper, a reconfigurable memory architecture and lookup technique for IP packet forwarding engines is presented. This is achieved by partitioning the forwarding table into smaller partial lookup tables for each output port and allowing a forwarding engine to process them in parallel. This effectively reduces the complexity of finding the ‘longest prefix match’ problem to the ‘first prefix match’ problem. Our method is a flexible technique that significantly elevates the scalability of the next generation network processors and other packet processing devices. Such scalability facilitates migration to IPv6 and benefits network equipments especially in terms of growing routing table size, traffic, frequency of route updates and bandwidth requirement.

Parallelisation of trie-based longest prefix matching for fast IP address lookups

IP address lookup is an important design issue for the high performance packet forwarding engine. The forwarding engine performs a longest prefix matching on the address lookup for an incoming IP packet to determine the next hop. A parallelisation scheme of longest prefix matching algorithms based on path-compressed trie is proposed. The proposed scheme reduces memory access time of IP address lookup while keeping memory spaces of parallel elements balanced.

Provisioning differentiated services using programming interfaces for networks

The IETF Differentiated Service (DiffServ) effort aims to create a scaleable framework for realizing traffic differentiation in IP networks. At present, the framework has laid the ground for ar-chitecting routers that provide basic functionalities to support traffic differentiation. How these DiffServ-enabled routers can be put together to form a service network is not mandated by the framework. The open signaling approach, originally proposed for ATM networks defines programming interfaces for switches and routers. End to end services can be created by programming the routers via the standard interfaces using simple signaling mechanisms. This leads to flexible service creation and co-operative behavior of multiple routers in a network. In this paper, we present a behavioral abstraction called virtual link for IP packet forwarding engines. The virtual link abstraction and open signaling are used for provisioning Differentiated Services. The work described herein has been submitted in part, as a contribution to the IEEE P1520.3 working group for standardizing programming interfaces for networks. Implementation experience of the proposed interfaces is presented.

Evolution of multiprotocol label switching

Multiprotocol label switching (MPLS) is rapidly emerging as an Internet Engineering Task Force (IETF) standard intended to enhance the speed, scalability, and service provisioning capabilities in the Internet. MPLS uses the technique of packet forwarding based on labels, to enable the implementation of a simpler high-performance packet forwarding engine. This also decouples packet forwarding from routing, facilitating the provision of varied routing services independent of the packet forwarding paradigm. The authors track the evolution of this technology in relation to other existing technologies. Then an overview of the MPLS architecture and design is provided. In addition, some of the work that was a precursor to MPLS is discussed, as well as related issues and debates.

Directions in active networks

Active networks represent a significant step in the evolution of packet-switched networks, from traditional packet-forwarding engines to more general functionality supporting dynamic control and modification of behavior. However, the phrase network means different things to different people. This article introduces a model and nomenclature for talking about active networks, describes some possible approaches in terms of that nomenclature, and presents various aspects of the architecture being developed in the DARPA-funded active networks program. Potential applications of active networks are highlighted, along with some of the challenges that must be overcome to make them a reality.