Packet Classification Method Research Articles

A parallel decision-making design for highly speedy packet classification

Packet classification is crucial in computer networks to increase network security because of developments in high-speed data communication. To support different network services including Quality of Service (QoS), security, and resource reservation, network packet classification is a crucial network kernel function. It became extremely challenging to classify arriving packets using the traditional packet classification algorithms at a decent pace due to the rapidly increasing size of rulesets and rule fields in current networks. In addition to hardware-based solutions, numerous contemporary software-based classification techniques have been put out to speed up packet classification. In general, it's critical to manage low latency, fast throughput, and higher energy efficiency with minimal memory needs while designing a packet classification method. In this paper, proposed the architecture makes use of the parallelism provided by current hardware technologies to classify numerous packets at once to improve throughput, reduce energy consumption, and significantly decrease the latency. The suggested high-speed parallel classification procedure uses two DPRAMs (DPRAM1 and DPRAM2) to support multiple read of the data. DPRAMs(Dual Port Random Access Memories) are preferred for stage memory because of their low latency performance, which enables quick rate packet lookup. The packet scheduling module receives the data from the DPRAM. The four successive packet splitter modules receive the packets in parallel. As a result, the packet classification throughput increased. To optimize throughput, and latency while maintaining low energy consumption, facilitating parallel packet classification architecture on FPGA is discussed in this work. Several parameters, including throughput, latency, energy efficiency, and memory requirements, will be evaluated and compared to traditional methods to assess performance. The classifier offers less latency of 51 ns and the lowest energy efficiency of 5.2 nJ, and its throughput may approach 802 million packets per second at the rate of 420 MHz clock frequency.

PcmSU-A Packet Classification Method Supporting High-Speed Search and Fast Update

PcmSU-A Packet Classification Method Supporting High-Speed Search and Fast Update

PCMIgr: a fast packet classification method based on information gain ratio

To solve the problem of ambiguous attribute selection in existing decision tree classification algorithms, a decision tree construction method based on information entropy, PCMIgr, is proposed. PCMIgr is a heuristic method based on greedy strategy. At each decision tree node, when it is necessary to select classification attributes for division, the attribute with the highest information gain ratio is selected. The main innovation of this method is that the attribute selection in the traditional classification method based on decision tree is optimized, and the classification efficiency of the constructed decision tree is improved compared with that before optimization. At the same time, the decision tree ensures that each leaf node is only associated with one rule, which avoids the common problem of "rule replication" in the process of traditional decision tree construction, and effectively saves memory and calculation time. The experimental results show that the application of this method to the construction of classification decision tree can further improve the efficiency of packet classification method based on decision tree, and can be applied to high-speed real-time packet classification.

High-performance flow classification using hybrid clusters in software defined mobile edge computing

Mobile Edge Computing (MEC) provides different storage and computing capabilities within the access range of mobile devices. This moderates the burden of offloading compute/storage-intensive processes of the mobile devices to the centralized cloud data centers. As a result, the network latency is reduced and the quality of service provided for the mobile end users is improved. Different applications benefit from the large-scale deployments of MEC servers. However, the considerable complexity of managing large scale deployments of the sheer number of applications for the millions of mobile devices is a challenge. Recently, Software Defined Networking (SDN) is leveraged to resolve the problem by providing unified and programmable interfaces for managing network devices. Most of the current SDN packet processing services are tightly dependent on the packet classification service. This primary service classifies any incoming packet based on matching a set of specific fields of its header against a flow table. Acceleration of this basic process considerably increases the performance of the SDN-based MEC. In this paper, the hierarchical tree algorithm, which is a packet classification method, is parallelized using popular platforms on a cluster of Graphics Processing Units (GPUs), a cluster of Central Processing Units (CPUs), and a hybrid cluster. The best scenario for the parallel implementation of this algorithm on the CPU cluster is that which combines OpenMP and MPI.In this case, the throughput of the classifier is 4.2 million packets per second (MPPS). On the GPU cluster, two different scenarios have been used. In the first scenario, the global memory is used to store the rules and the Hierarchical-trie of the classifier while in the second scenario we break the filter set in a way that the resulting Hierarchical-trie of each subset could be stored in the shared memory of GPU. According to the results, although the first GPU cluster scenario achieves a throughput of 29.19 MPPS and a speedup 58 times as great as the serial mode, the second scenario is 12 times faster due to using the shared memory. The best performance, however, belongs to the hybrid cluster mode. The hybrid cluster achieves a throughput of 30.59 which is 1.4 MPPS more than the GPU cluster.

Design of a Low Latency and High Throughput Packet Classification Module on FPGA Platform

The Packet classification method plays a significant role in most of the Network systems. These systems categories the incoming packets in various flows and takes suitable action based on the requirements. If the size of the network is vast and complexity will arise to perform the different operations, which affects the network performance and other constraints also. So there is the demand for high-speed packet classifiers to reduce the network complexity and improve the network performance. In this article, The Bit vector Packet classifier (BV-PC) Module is designed to improve the network system performance and overcome the existing limitation of Packet classification approaches on FPGA. The BV-PC Module contains Packet generation Unit (PGU) to receive the valid incoming packets, Memory Unit (MU) to store valid packets, Header Extractor Unit (HEU) extracts the IP Header address information from the Valid packets, The BV-Based Source and Destination Address (BV-SA, BV-DA) unit receives the IP packet header Information and Process with BV based rule set and aggregates the BV-SA and BV-DA outputs, Priority Encoder encodes the Highest priority BV Rule for the generation of Classified output. The BV-PC utilizes <2% Chip area (slices), works at 509.38MHz, and consumed Less 0.103 W of total Power on Artix-7 FPGA. The BV-PC operates with a latency of 5 clock cycles and works at 815.03Mpps throughput. The BV-PC is compared with existing approaches and provides Better improvements in Hardware constraints.

A Packet Classification Method via Cascaded Circular-Run-Based Trie

A Packet Classification Method via Cascaded Circular-Run-Based Trie

Fast packet classification algorithm for network-wide forwarding behaviors

Packet classification has been a key technology to quickly identify an action to be taken on a packet at a switch. Several advanced applications, most of which have been introduced recently with the advent of software-defined networking, commonly require the identification of a combination of switch actions, i.e., the network-wide forwarding behavior of a packet. Conventional classification methods, however, fail to well support network-wide behaviors, since the search space is partitioned in convoluted manner due to the complexity posed by the combinations possible.This paper proposes a novel packet classification method that supports the fast determination of network-wide forwarding behaviors. To avoid the inefficiencies of existing methods, which are revealed for the first time by our research, we base our method on a compressed data structure named the multi-valued decision diagram. On the solid foundation of decision diagrams, several algorithms are introduced with thorough theoretical analyses, and the construction process and the classification performance are highly optimized for the new classification problem. Experiments on real network datasets show that our method identifies the network-wide forwarding behaviors at the line basic rate, e.g., 10 Mpps, on a single CPU core with only tens of MB of memory.

International Conference on Advances in Engineering Research on packet classification cased on improved cross- product method

Packet filtering and forwarding is the core problem of gigabit network intrusion forensics system, which requires network forensics machine to classify IP packet, and packet is processed differently according to classification results. This paper presents an improved packet classification method based on cross-product. It classifies the addresses into several classes, and then cross-products these classes. To compress the large of cross-product table, this paper uses no-overlapping partition method to combine repeated rows or columns. Simulation experiments have verified the validity of our method.

Accelerating network security services with fast packet classification

To protect a network, secure network systems such as intrusion detection system (IDS) and firewall are often installed to control or monitor network traffic. These systems often incur substantial delay for analyzing network packets. The delay can be reduced with fast packet classification, which can effectively classify network traffic, and consequently accelerate the analysis of network packets. In the last few years, many researchers devoted to providing fast packet classification methods for multidimensional classifier. However, these methods either suffer from poor performance and huge storage requirement, or are lack of dimension scalability. In this paper, we propose a packet classification method based on tuple space search, and use the multidimensional binary search tree (Kd-tree) to improve search performance. The proposed scheme requires only O(d log W) search time and controlled storage requirement, where d is the number of dimensions, and W is the utmost bit length for specifying prefixes in a classification rule. It features fast packet classification, and supports dynamic update which is a basic requirement of many secure network services, such as IDS and firewall.

Packet classification through hierarchical rulebase partitioning

A packet classification method through hierarchical rulebase partitioning. The packet classification method for searching for a rule having a highest priority and matching among a plurality of rules included in a specified rulebase with respect to a packet input from an external network and processing the packet according to the searched rule. The method includes: a preprocessing step of partitioning the rulebase into a plurality of independent sub-rulebases based on a specified condition and producing a hash table on the basis of the sub-rulebases; and a classification step of classifying the packet by searching the hash table using a hash key extracted from a packet header of the inputted packet and mapping the packet on the sub-rulebase corresponding to the packet.