Packet Classification Engine Research Articles

TeRa: Ternary and Range based packet classification engine

This work proposes a novel approach to the hardware implementation of packet classification in ASICs, using NAND-NOR logic at each stage. The proposed design utilizes modified ternary encoding to process the prefix field, resulting in a two-level NAND-NOR logic for prefix processing. The field representation based on classbench rules helps reduce memory usage by almost 45% compared to conventional prefix representations. Additionally, an efficient range matching solution is implemented using a carry tree logic that relies on 1’s and 2’s Complement subtraction. The integration of a carry-based range comparator enhances hardware optimization for range processing without the need for prefix conversion. Additionally, match inversion logic streamlines the processing of exceptional or inverse fields without incurring extra hardware overhead. This work also presents a specialized logic circuit for ternary and range matching, complemented by a specialized priority grouping technique. The proposed architecture, including TYPE1 and TYPE2, achieves throughput rates of 9.9 BPPS and 6.6 BPPS, respectively, while supporting both best-match and multi-match addresses within the same hardware environment.

A Network Packet Classification Engine For Real-Time Applications with Enhanced Performance

A Network Packet Classification Engine For Real-Time Applications with Enhanced Performance

Deterministic Approach for Range-enhanced Reconfigurable Packet Classification Engine

Reconfigurable hardware is a promising technology for implementing firewalls, routing mechanisms, and new protocols for evolving high-performance network systems. This work presents a novel deterministic approach for a Range-enhanced Reconfigurable Packet Classification Engine based on the number of rules on FPGAs. The proposed framework uses a RAM-established Ternary Match to represent the prefix and the range prefix and efficient rule-reordering for priority selection to get both best-match and multi-match in the same architecture. The recommended framework exhibits 3.2 Mbits of LUT-RAM-based ternary content addressable memory (TCAM) to hold a maximum of 31.3 K of 104- bit rules with 520 MPPS . LUT-RAM, along with BRAM, shows 4 Mbits of TCAM space to implement 38.5 K of 104- bit rules to sustain a throughput of 400 MPPS on Virtex-7 FPGA. The complete architecture offers scalability, better resource utilization (minimum of 50% ), representation of inverse prefix with single entry, range expansion with a single rule, getting best- and multi-match, and determination of the required number of FPGA resources for a particular dataset.

A high-performance energy efficient packet classification design on FPGA

One of the most crucial thing to safeguard the network against malicious activities is security and the network devices must be able to classify packets. The firewall applications benefit greatly from the architecture of the packet classification engine that is given in this research work. A tree-based approach is used to systematically analyze each field in a packet header, leading to a more secure system. The Packet Classification Engine (PCE) is configured to evaluate Ethernet packets based on the source IP address, destination IP address, source port, destination port, and protocol aspects in the packet header. The PCE shows that the typical clock frequency from input to output is 13 clocks per second. The architecture is extremely rapid, reliable, and adaptable and can make good use of the tree based algorithm's advantages. The proposed architecture has achieved high throughput of 538 MPPS with less energy of 10.6 nJ at low latency of 62 ns. The PCE must have a rapid and reliable FIFO buffer to work effectively. A FPGA (Field Programmable Gate Array) device is being utilized to filter Ethernet packets using the proposed PCE.

A high-performance dual classifier based packet classification engine on FPGA

Security is one of the key elements of real-time communication systems, especially with the developments in digital communication systems. One of the most crucial networking activities that guards against hacking and unintentional consequences on connected devices is packet classification. The router's and other linked devices' sluggish processing speeds are a problem for implementing real-time packet classification. This paper proposes a novel parallel architecture for packet classification in routers. The design that has been suggested uses the parallelism that modern hardware technologies offer to categorize several packets at once to increase throughput, lower energy usage, and drastically lower latency. The suggested design supports multiple data reads by utilizing Dual Port RAM, or DPRAM. They have low latency performance and allow for fast rate packet lookup, making them the preferable choice for stage memory. The DPRAM provides the data to the packet scheduling module. The packets are received concurrently by the two subsequent packet splitter units. The throughput of packet classification increases as a result. In this paper, a parallel packet categorization architecture using FPGA is explored for maximizing throughput and maintain allowable latency while preserving low energy consumption. The classifier has the lowest energy efficiency of 7.2nJ and less latency of 58 ns. Its throughput may reach 668 MPPS (million packets per second).

Many‐field packet classification with decomposition and reinforcement learning

Scalable packet classification is a key requirement to support scalable network applications such as firewalls, intrusion detection, and differentiated services. With the ever increasing line-rate in core networks, it becomes a great challenge to design a scalable packet classification solution using hand-tuned heuristic approaches. The authors present a scalable learning-based packet classification engine by building an efficient data structure for different rulesets with many fields. This method consists of the decomposition of fields into subsets and building separate decision trees on those subsets using a deep reinforcement learning procedure. To decompose given fields of a ruleset, the authors consider different grouping metrics such as standard deviation of individual fields and introduce a novel metric called diversity index (DI). The authors examine different decomposition schemes and construct decision trees for each scheme using deep reinforcement learning and compare the results. The results show that the SD decomposition metrics results in 11.5% faster than DI metrics, 25% faster than random 2 and 40% faster than random 1. Furthermore, the authors’ learning-based selection method can be applied to varying rulesets due to its ruleset independence.

High-Performance and Dynamically Updatable Packet Classification Engine on FPGA

High-performance and dynamically updatable hardware architectures for multi-field packet classification have regained much interest in the research community. For example, software defined networking requires 15 fields of the packets to be checked against a predefined rule set. Many algorithmic solutions for packet classification have been studied over the past decade. FPGA-based packet classification engines can achieve very high throughput; however, supporting dynamic updates is yet challenging. In this paper, we present a two-dimensional pipelined architecture for packet classification on FPGA; this architecture achieves high throughput while supporting dynamic updates. In this architecture, modular Processing Elements (PEs) are arranged in a two-dimensional array. Each PE accesses its designated memory locally, and supports prefix match and exact match efficiently. The entire array is both horizontally and vertically pipelined. We exploit striding, clustering, dual-port memory, and power gating techniques to further improve the performance of our architecture. The total memory is proportional to the rule set size. Our architecture sustains high clock rate even if we scale up (1) the length of each packet header, or/and (2) the number of rules in the rule set. The performance of the entire architecture does not depend on rule set features such as the number of unique values in each field. The PEs are also self-reconfigurable; they support dynamic updates of the rule set during run-time with very little throughput degradation. Experimental results show that, for a 1 K 15-tuple rule set, a state-of-the-art FPGA can sustain a throughput of 650 Million Packets Per Second (MPPS) with 1 million updates/second. Compared to TCAM, our architecture demonstrates at least four-fold energy efficiency while achieving two-fold throughput.

Fast Packet Classification Using Multi-Dimensional Encoding

Internet routers need to classify incoming packets quickly into flows in order to support features such as Internet security, virtual private networks and Quality of Service (QoS). Packet classification uses information contained in the packet header, and a predefined rule table in the routers. Packet classification of multiple fields is generally a difficult problem. Hence, researchers have proposed various algorithms. This study proposes a multi-dimensional encoding method in which parameters such as the source IP address, destination IP address, source port, destination port and protocol type are placed in a multi-dimensional space. Similar to the previously best known algorithm, i.e., bitmap intersection, multi-dimensional encoding is based on the multi-dimensional range lookup approach, in which rules are divided into several multi-dimensional collision-free rule sets. These sets are then used to form the new coding vector to replace the bit vector of the bitmap intersection algorithm. The average memory storage of this encoding is Θ (L · N · log N) for each dimension, where L denotes the number of collision-free rule sets, and N represents the number of rules. The multi-dimensional encoding practically requires much less memory than bitmap intersection algorithm. Additionally, the computation needed for this encoding is as simple as bitmap intersection algorithm. The low memory requirement of the proposed scheme means that it not only decreases the cost of packet classification engine, but also increases the classification performance, since memory represents the performance bottleneck in the packet classification engine implementation using a network processor.

Fast Packet Classification Using Bit Compression with Fast Boolean Expansion

To support applications such as Internet security, virtual private networks, and Quality of Service (QoS), Internet routers need to quickly classify incoming packets into flows. Packet classification uses information contained in the packet header and a predefined rule table in the routers. In general, packet classification on multiple fields is a difficult problem. Hence, researchers have proposed a variety of classification algorithms. This paper presents a novel packet classification algorithm, the bit compression algorithm. As with the best-known classification algorithm, bitmap intersection, bit compression is based on the multiple dimensional range lookup approach. Since bit vectors of the bitmap intersection contain many ”0” bits, the bit vectors could be compressed. We compress the bit vectors by preserving only useful information and removing the redundant bits of the bit vectors. An additional index table would be created to keep track of the rule number associated with the remaining bits. Additionally, the wildcard rules enable an extensive improvement in the storage requirement. A novel Fast Boolean Expansion enables our scheme to obtain better classification speed even under a large number of wildcard rules. Compared to the bitmap intersection algorithm, the bit compression algorithm reduces the storage complexity in the average case from O(dN^2) (for bitmap intersection) to θ(dN•logN), where d denotes the number of dimensions and N represents the number of rules. The proposed scheme cuts the cost of packet classification engine and increases classification performance by accessing less memory, which is the performance bottleneck in the packet classification engine implementation using a network processor.