Charge Packets Research Articles

Interline CCD image sensor with an antiblooming structure

A ⅔-in 384 (H) × 490 (V) element interline CCD image sensor with a new antiblooming structure was developed. Blooming was suppressed without sacrificing photosensitivity and dynamic range by means of a vertical overflow drain positioned under (rather than beside) a photodiode. For 10-percent vertical height illumination the smear signal was reduced to 0.05 percent of the illumination signal. Well-balanced performance, namely, large dynamic range (72 dB), low random noise (65 rms noise electrons per charge packet), high-contrast transfer functions for horizontal and vertical directions, and a spectral response similar to the luminous efficiency curve were obtained under moderate operating conditions.

A high-speed digitally programmable CCD transversal filter

A 32-stage programmable transversal filter is described which has 6-bit digitally programmable tap weights and has been operated at a 25-MHz clock rate. The device has a linear dynamic range of more than 60 dB and occupies a chip area of 24 mm/SUP 2/. Pipe-organ architecture made it possible to use a simple floating diffusion output circuit. The tap weight values are set by a 6-bit multiplying D/A converter (MDAC) at each delay-line input. The MDAC is a multiple CCD input structure with binary-weighted input gate areas and logic-controlled gates to multiply each charge packet by 0 or 1. The conversion speed of this structure is as high as that of a CCD input structure, but careful control of threshold voltage variations is required to achieve high accuracy. Experiments are described which show that threshold offsets can be reduced to about 2 mV RMS for a fill-and-spill input indicating that MDACs of this type with 8-bit accuracy are feasible.

Characterization of local transfer defects in CCD's using a multireversal transfer mode

In order to complement the usual measurement of average transfer inefficiency in linear CCD's, a new experimental method is proposed which allows one to determine the origin and to localize some transfer defects along the shift register. By repeatedly shifting charge packets forward and backward, the effect of local defects in the potential profile is locally emphasized and can be simply measured and characterized. Experimental results are given as examples, showing that local fixed losses of less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> Q <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</inf> can be measured.

Space charge perturbed transient transport in a dispersive medium a-As 2Se 3

Transport of an injected sheet of flash photoexcited holes is compared under small and large signal conditions in the same a-As 2Se 3 specimen films. Under small signal conditions the injected charge packet transits the specimen bulk in a uniform field. Under lage signal conditions nearly a CV of charge is injected and transport therefore proceeds under space charge perturbed conditions. Many experimental comparisons between transport under small and large signal conditions have been made in non-dispersive media. Features unique to transient transport under space charge perturbed conditions in nondispersive systems are theoretically predicted and typically observed. In a-As 2Se 3, a prototypical dispersive medium, no analogous distinction is observed between transient transport behavior under small and large signal conditions. Key characteristics of dispersive transport under small signal (pulse injection) conditions for example, the computed transit times, universality of the transient current pulse shape with respect to field and the correlation between current pulse shape and field dependence of the transit time are unchanged in the large photoexcitation limit. Temperature dependence of the dispersion parameter α is observed. It is also unaffected by photoexcitation intensity.

Measurement of cube-root broadening of charge packets in metal-oxide- semiconductor structures

The spatial width of electron packets drifting in a nearly uniform electric field in a metal-oxide-semiconductor structure is determined from flux pulse measurements. The width is found to broaden as the cube root of time, thus verifying an earlier prediction. Furthermore, the broadening rate constant is found to agree with that predicted to within 7%.

High-field drift velocity of electrons at the Si–SiO2 interface as determined by a time-of-flight technique

We describe a new technique for the study of high-field transport at semiconductor–insulator interfaces. In this technique, we observe the time-of-flight of discrete charge packets introduced by a pulsed laser. The packets drift in a region of uniform applied tangential field at the interface. We present data on the room temperature drift velocity of electrons at the interface between (100) silicon and thermally grown silicon dioxide as a function of both tangential and normal electric fields. We observe velocities near saturation of 8.9×106 cm/s at a tangential field of 4 V/μm and a normal field of 9 V/μm, and extrapolate to a saturation velocity of 9.2×106 cm/s independent of normal field. This value is more than 40% higher than reported by early workers, and is close to the saturation velocity observed in bulk silicon.

Combinatorial digital logic using charge-coupled devices

Describes a new approach to circuit design that allows charge-coupled devices to perform combinatorial digital logic. These circuits use charge packets, floating gates, and conventional NMOS circuitry in a way that combines the low power, high packing density of CCDs with some of the high-speed combinatorial logic capabilities of conventional NMOS circuits. Since only a few transfers are involved in the operation of these circuits, charge transfer efficiency is not a critical parameter. A CCD ripple adder is described that has been designed, fabricated, and tested, and a charge control analysis has been used to estimate its ultimate speed capabilities. An arithmetic logic unit design is also described. The combinatorial CCD circuits are particularly well suited to previous digital CCD logic approaches in that they allow elimination of power and space-consuming storage registers. These circuits are most useful in applications requiring large, regular, pipelined architectures such as systolic arrays where the critical performance parameter is throughput per unit power.

Dynamic packet splitting in charge domain devices

A set of experiments has been designed to investigate techniques for improving the accuracy of charge packet splitting using field oxide barriers. These experiments studied the effect of channel width (250 µm, 500 µm), split ratio (1:1, 1:3, 1:9), and dummy splitters (to equalize lateral fields) on split accuracy. In general, it was observed that split accuracy is higher in wider channel devices, especially when small coefficients are implemented. The major source of error was found to be due to processing. The dummy splitters used to compensate edge effects and equalize lateral fields, reduced the signal error (with respect to measured geometry) to as low as 0.07%.

Transport of broadening charge packets at surfaces

Surface transport of charge packets in metal-oxide-semiconductor structures is studied theoretically. The governing nonlinear partial differential equation is derived, and an approximate analytical solution to it is found. It shows that the density in the packet approximates an inverted truncated parabola whose width increases as the cube root of time, and whose drift velocity has a time dependence determined by the self-generated and applied electric fields normal to the surface. The time average of the self-generated and applied normal fields is shown to result in averages of the two fields over different portions of the drift channel. The flux peak velocity, which is measured in a time-of-flight experiment, is shown to be the sought-after drift velocity of the density peak plus the (negative) velocity of the flux peak relative to the density peak. An expression for the latter quantity is developed. A relation between the flux peak velocity and the drift velocity at the flux peak is also derived.

Exact solution for space-charge broadened packets in semiconductors

The transport equation for charge packets in time-of-flight measurements of drift velocity in bulk semiconductors including full account of space-charge effects is derived. It is found to be a nonlinear, partial, integro-differential equation. Two key transformations permit finding an exact, analytical solution by decomposing the problem into separate equations for the shape function, the broadening function, and the velocity function. The solution consists of a rectangular-shaped charge packet which broadens linearly in time and propagates with an exponentially increasing velocity until it begins entering the electrode at which time the velocity can be expressed in terms of modified Bessel functions. The observed current pulse in the external circuit is also calculated and it is shown that experimenters have made a mistake in interpreting the pulse and so have deduced too high a drift velocity. The error, however, has typically been small (\ensuremath{\sim}1%).

Realisation of multithreshold threshold-logic gates using charge-coupled devices

A threshold logic gate is described which uses as its core a charge-coupled device. It is shown that the CCD is suitable for this application because of its ability to (a) quantise charge input to a gate, (b) add charge packets from different gates, and (c) permit conditional charge overflow to occur. The peripheral circuitry employs compatible MOSFET circuits, so that the entire gate can be made in integrated circuit form. The gate is voltage programmbale.

CCD memory using multilevel storage

In CCD multilevel storage, more than one bit of information is stored in a charge packet. Requirements for CCD MLS systems are described, and circuits for the encoding and decoding of charge packets which operate essentially independent of device parameter and geometric tolerances are presented. 3-bit operation on a short shift register loop is demonstrated. Requirements on leakage and transfer in efficiency for 2- and 3-bit MLS are discussed.

Space Charge Expansion of Single Packets of Charge

Space Charge Expansion of Single Packets of Charge

Optimum scaling of buried-channel CCD's

The maximum charge packet size in a two-phase charge-coupled device (CCD) is limited by many constraints relating to the transfer efficiency requirement and control circuit limitations. The constraints are quantified and an optimization routine is developed for designing CCD's with maximum charge capacity per unit area under these constraints. The optimum charge capacity for scaled down CCD's is calculated and it is shown that the normal buried channel cannot be designed to have adequate charge capacity at small geometries. A novel low-voltage buried-channel structure is introduced which uses a shallow p-type surface implant to minimize surface trapping and increases the charge capacity per unit area 2.4× compared to the normal buried channel. The optimum charge packet size at ∼1-µm geometry for these CCD structures, based on these calculations, is shown to be inadequate for VLSI dynamic memory applications.

The low light level potential of a CCD imaging array

Some limitations to the operation of a CCD TV camera sensor at low light levels are discussed. Transfer inefficiency with small charge packets is analyzed theoretically, and the prediction made that with good processing this should not be a serious problem. The principal limitation is seen to be the output amplifier, and a new low-noise output detector, the "floating surface detector," is described in detail. At -50°C it yields a noise equivalent signal of 16 electrons and a dynamic range of 85 dB over a 1-MHz video bandwidth.

Characterization of charge-transfer devices with position-dependent small-signal transfer inefficiency

Models for the small-signal response of a CTD with position-dependent transfer inefficiency are developed. The small-signal inefficiency E. can become position-dependent, for example, when sizeable amount of thermally generated charge is added to the transferred charge packets at each stage. Expressions for the frequency response and for the step response are derived in terms of single-transfer inefficiencies. In order to describe the overall performance of a CTD by means of an unique parameter, an effective transfer inefficiency is defined which only depends upon the input bias charge and generation conditions. Based upon the small-signal response models an experimental characterization and performance prediction technique is presented. Bucket-brigade delay lines with different design parameters are used as experimental test vehicles. It is shown that for optimum performance the devices must be operated at some optimum input bias charge level.

Charge-coupled device structures for VLSI memories

High-performance CCD's which can operate at the scaled voltage levels and geometry sizes projected for VLSI memory will require the storage, transfer, and detection of very small charge packets (≤25 000 electrons). The scaling requirements for such CCD structures are shown to be more complex than MOS scaling laws. The device physics of CCD structures which can meet these performance requirements are discussed and related to material and technology problems which must be overcome. For a given area, an enhanced-capacity implant technique is used to increase the storage capacity. A new detection scheme using a bipolar charge amplification allows up to an order of magnitude increase in output sensitivity. Transient subthreshold measurements show that very small interelectrode barriers may exist at low clock voltage overdrive which severely limit CCD transfer efficiency at small geometries.

Leakage studies in high-density dynamic MOS memory devices

Dynamic MOS memories are the most promising for VLSI densities. With shrinking geometries and small charge packet sizes, it is becoming increasingly important to understand the relative importance of various mechanisms that contribute to leakage current in dynamic MOS structures. This paper presents an in-depth study of leakage sources in such devices. It is shown that special device structures may be fabricated to separate and understand the nature of leakage from periphery and bulk. The periphery leakage is due to the transition region of gate-to-field oxide overlapped by the gate electrode. This contribution can be up to 10× the contribution due to classical surface and bulk generation under the storage electrode itself. It is also shown that with increased bulk lifetime in state-of-the-art devices, the diffusion component of leakage becomes very significant, especially at high temperatures. These studies lead to device design criteria from leakage considerations that will be very important for VLSI memory design.

Antialiasing Filter with an Improved S/N Ratio

If a CCD low-pass filter is used for antialiasing, a higher data rate is necessary at the input compared to the output. This difference in the data rate is used to increase the signal-to-noise ratio. By adding a given number of consecutive charge packets at the output stage, the output data rate can be reduced until the Nyquist theorem for the output signal is violated. By summing up those charge packets, the signal is added arithmetically whereas the noise, not being correlated, is added geometrically. This results in an improvement of the S/N ratio equal to the number of charge packets added.

Antialiasing filter with an improved S/N ratio

Describes a CCD low pass filter for antialiasing employing a higher data rate at the input compared to the output, which is used to increase the signal-to-noise ratio. By adding a given number of consecutive charge packets at the output stage, the output data rate can be reduced until the Nyquist theorem for the output signal is violated. By summing up those charge packets, the signal is added arithmetically whereas the noise, not being correlated, is added geometrically. This results in an improvement of the S/N ratio equal to the number of charge packets added.