p-GaN Cap Layer Research Articles

Plasma Treatment Technologies for GaN Electronics

Nowadays, the third-generation semiconductor led by GaN has brought great changes to the semiconductor industry. Utilizing its characteristics of a wide bandgap, high breakdown Electric field, and high electron mobility, GaN material is widely applied in areas such as 5G communication and electric vehicles to improve energy conservation and reduce emissions. However, with the progress in the development of GaN electronics, surface and interface defects have become a main problem that limits the further promotion of their performance and stability, increasing leakage current and causing degradation in breakdown voltage. Thus, to reduce the damage, Plasma treatment technologies are introduced in the fabrication process of GaN electronics. Up to now, designs like the high-resistivity p-GaN cap Layer, passivating termination, and surface recovery process have been established via Plasma treatment, reaching the goals of normally-off transistors, diodes with high breakdown voltage and high-reliability GaN electronics, etc. In this article, hydrogen, fluorine, oxygen, and nitrogen Plasma treatment technologies will be discussed, and their application in GaN electronics will be reviewed and compared.

The composited high reflectivity p-type electrodes with patterned ITO for AlGaN-based ultraviolet light emitting diodes

Composited p-type electrodes with high reflectivity have been investigated in AlGaN-based ultraviolet light emitting diodes (UV-LEDs) to improve the light extraction efficiency, which are composed of a patterned ITO layer and an Al reflector. It is verified that the patterned ITO with a thickness of 30 nm can not only well form Ohmic contact with p-GaN capping layer, but also be nearly 90% transparent to ultraviolet light, and thus presenting a reflectivity of 73% at 280 nm when combined with an Al reflector. Further experimental efforts confirm that the performance of the UV-LEDs is dramatically improved with such p-type electrodes. The maximum light output power and wall plug efficiency in the current range of 0–100 mA are severally increased by 49.8% and 54.2% compared to the device with traditional Ni/Au electrodes.

Investigation of the forward gate leakage current in pGaN/AlGaN/GaN HEMTs through TCAD simulations

In this study, we examined the gate leakage characteristics of normally off pGaN/AlGaN/GaN HEMTs through a simulation study. The Fowler Nordheim Tunneling (FNT) mechanism mainly contributes to the gate leakage process as indicated by the Technology Computer-Aided Design (TCAD) simulation. However, at low bias, the FNT undercalculates the leakage current since the electric field is low in this region. This extra leakage current component at this low bias region can be attributed to the presence of surface traps. Trap-assisted tunneling current along with the FNT current can explain forward leakage characteristics of the pGaN HEMTs. Our TCAD simulations were matched with the experimental data for five devices from four different research groups to support this claim. Using TCAD simulations, we have been able to analyze several device parameters including the various potential drops inside the gate stack structure. We were able to identify some of the trap levels and compare them to the dominant defects expected to be present in the pGaN cap layer. Furthermore, we studied the effects of different device parameters on the gate leakage process in the pGaN HEMT.

Enhanced performance of normally-OFF GaN HEMTs with stair-shaped p-GaN cap layer

The p-GaN-gated E-mode HEMTs (P-HEMTs) are being extensively studied for emerging power electronics. However, the devices still suffer from performance trade-off among threshold voltage (V TH), output drain current (I DS), and breakdown voltage (V BD). Herein, we propose a P-HEMT with a stair-like p-GaN cap layer to boost their performance. The p-GaN cap layer is composed of four discrete p-GaN staircases with the decreased thickness to the right (Right-Stair P-HEMT) or to the left (Left-Stair P-HEMT). It is found that the RSP-HEMT simultaneously achieves the 1.3 times increased I DS, 160 V enhanced V BD, and improved V TH stability against drain-induced barrier lowering effects, compared with the LSP-HEMT and the conventional BaSeline P-HEMT. These device merits should be attributed to the effective manipulation of the lateral electric field (E F) under all bias conditions by the unique band structures enabled by the RSP configuration. Such E F manipulation strategies offer us helpful guidance and insights to further propel the development of high-performance E-mode P-HEMTs.

Incorporation of total ionizing dose effects into a compact model for p-GaN gate high electron mobility transistors

Total ionizing dose (TID) characteristics of p-GaN gate high electron mobility transistors (HEMTs) under different bias conditions are explored in this work. Potential mechanism accounting for the TID response of p-GaN gate HEMTs is analyzed, based on which a TID effects model is developed. The TID effects model describes the relationship among threshold voltage of p-GaN gate HEMTs, total radiation dose, and electric field inside the p-GaN cap layer. Furthermore, an approach incorporating the TID effects model into Advanced Spice Model for HEMT (ASM-HEMT) is proposed, the reliability of which is validated by the well-fitted modeled results in comparison with the measured ones. This approach makes it possible to probe into the impact of TID effects on p-GaN gate HEMTs from the perspective of circuit level, which provides a basis for the follow-up GaN-based circuit design.

On the integrated p-type region free of electron blocking layer for AlGaN-based deep-ultraviolet light emitting diodes

AlGaN-based deep-ultraviolet light emitting diodes (DUV-LEDs) with thin p-GaN capping layer have been one of the most promising configurations, thanks to their excellent light extraction potential, which are, however, generally accompanied by insufficient hole supply. In this work, multi-graded p-AlGaN layers are adopted as an integrated p-type region, in which the electron blocking layer (EBL) is taken off to promote the carrier transport. The experimental results show that both the operation voltage and light output power of the DUV-LEDs are improved compared to the traditional ones, leading to a remarkable increase (by 114%) in their wall-plug efficiency. Further analysis confirms that the integrated p-type region serving as the hole supply layer helps holes to avoid the barrier between the p-GaN and integrated p-type region during their transport, and the absence of the EBL further eliminates part of the obstacles for hole drifting, giving rise to an enhanced hole concentration in quantum wells. Meanwhile, thanks to the modulation of the negative polarization induced bulk charges for conduction band, which is introduced within the integrated p-type region, the electron leakage is effectively suppressed even without the EBL, thus improving the device performance dramatically.

Novel In-Situ AlN/p-GaN Gate HEMTs With Threshold Voltage of 3.9 V and Maximum Applicable Gate Voltage of 12.1 V

In this article, we demonstrate a novel E-mode HEMT featuring in situ AlN dielectric layer on p-GaN cap layer. Compared with conventional p-GaN gate HEMT, the threshold voltage of in situ AlN/p-GaN gate HEMT shifts from 1.8 to 3.9 V, and the forward gate breakdown voltage is increased from 10.0 to 17.6 V. By considering 10 years’ lifetime at 63% failure level, the maximum applicable gate voltage for AlN/p-GaN gate HEMT reaches a remarkable high value of 12.1 V (E-model), which is much higher than that of 6.1 V for conventional HEMT. In addition, the novel E-mode HEMT exhibits a high ON/OFF ratio of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{{9}}$ </tex-math></inline-formula> . Experiments demonstrate that E-mode in situ AlN/p-GaN gate HEMT has great potential in power electronics applications.

Enhancement of the light output efficiency and thermal stability of AlGaN-based deep-ultraviolet light-emitting diodes with Ag-nanodot-based p-contacts and an 8-nm p-GaN cap layer.

The efficiency of AlGaN-based deep-ultraviolet light-emitting diodes (DUV LEDs) is limited by the high absorption issue of the p-GaN contact layer or poor contact properties of the transparent p-AlGaN contact layer. Enhancement of the light output efficiency and thermal stability of DUV LEDs with an emission wavelength of 272 nm was investigated in this work. Ag nanodots on an 8-nm p-GaN cap layer were used to form ohmic contact, and Al and Mg reflective mirrors were employed to enhance the light output power (LOP) of DUV LEDs. However, serious deterioration of LOP occurred after the high-temperature process for the LEDs with Al and Mg reflective mirrors, which can be attributed to the damage to the ohmic contact properties. A Ti barrier layer was inserted between the Ag/p-GaN and Al layers to prevent the degeneration of ohmic contact. The wall-plug efficiency (WPE) of DUV LEDs fabricated by the Ag-nanodot/Ti/Al electrode is 1.38 times that of LEDs fabricated by adopting a thick Ag layer/Ti/Al at 10 mA after a high-temperature process. The Ag-nanodot/Ti/Al electrode on thin p-GaN is a reliable technology to improve the WPE of DUV LEDs. The experimental and simulated results show that the ohmic contact is important for the hole-injection efficiency of the DUV LEDs when p-GaN is thin, and a slight increase in the contact barrier height will decrease the WPE drastically. The results highlighted the importance of thermally stable ohmic contacts to achieve high-efficiency DUV LEDs and demonstrated a feasible route for improving the LOP of DUV LEDs with a thin p-GaN cap layer and stable reflective electrodes.

Low Buffer Trapping Effects above 1200 V in Normally off GaN-on-Silicon Field Effect Transistors.

We report on the fabrication and electrical characterization of AlGaN/GaN normally off transistors on silicon designed for high-voltage operation. The normally off configuration was achieved with a p-gallium nitride (p-GaN) cap layer below the gate, enabling a positive threshold voltage higher than +1 V. The buffer structure was based on AlN/GaN superlattices (SLs), delivering a vertical breakdown voltage close to 1.5 kV with a low leakage current all the way to 1200 V. With the grounded substrate, the hard breakdown voltage transistors at VGS = 0 V is 1.45 kV, corresponding to an outstanding average vertical breakdown field higher than 2.4 MV/cm. High-voltage characterizations revealed a state-of-the-art combination of breakdown voltage at VGS = 0 V together with low buffer electron trapping effects up to 1.4 kV, as assessed by means of substrate ramp measurements.

Selective sublimation of GaN and regrowth of AlGaN to co-integrate enhancement mode and depletion mode high electron mobility transistors

In the present study, the selective sublimation of the p-GaN cap layer of Al(Ga)N/GaN HEMTs is developed to replace the commonly used dry etching with no risk of damage in the barrier layer in order to fabricate enhanced mode transistors. Thanks to this approach, enhancement-mode transistors are fabricated with a threshold voltage between 0 V and +1.5 V depending on the barrier layer aluminum molar fraction and thickness. Furthermore, we show the benefit of the combination of selective sublimation with the regrowth of AlGaN to reduce access resistance in these transistors which can be co-integrated with depletion-mode devices fabricated in the same process in areas where p-GaN has been totally evaporated.

Normally-off AlGaN/GaN heterojunction field-effect transistors with in-situ AlN gate insulator

AlGaN/GaN heterojunction field-effect transistors (HFETs) with p-GaN cap layer are developed for normally-off operation, in which an in-situ grown AlN layer is utilized as the gate insulator. Compared with the SiN x gate insulator, the AlN/p-GaN interface presents a more obvious energy band bending and a wider depletion region, which helps to positively shift the threshold voltage. In addition, the relatively large conduction band offset of AlN/p-GaN is beneficial to suppress the gate leakage current and enhance the gate breakdown voltage. Owing to the introduction of AlN layer, normally-off p-GaN capped AlGaN/GaN HFET with a threshold voltage of 4 V and a gate swing of 13 V is realized. Furthermore, the field-effect mobility is approximately 1500 cm2⋅V−1⋅s−1 in the 2DEG channel, implying a good device performance.

The influence of lightly doped p-GaN cap layer on p-GaN/AlGaN/GaN HEMT

In this paper, the influence of a lightly doped p-GaN (p−-GaN) cap layer on p-GaN/AlGaN/GaN high electron mobility transistors (HEMTs) (LDP-HEMTs) was investigated. No difference in output or off-state breakdown characteristics was observed, but there was a negative shift in threshold voltage (V TH). The gate leakage (V GS = 7 V) dropped by three orders of magnitude, and the gate forward breakdown voltage and continuous operating voltage increased by 6.5 V and 2.5 V, respectively. It is worth noting that the gate characteristics are significantly optimized, which is ascribed to the employment of the p−-GaN cap layer. The simulations illustrate that the electric field is dispersed, and the electric peak is alleviated by the p−-GaN cap layer, thus suppressing the impact ionization and carrier injection in the high electric field. Furthermore, there is a negligible effect on the temperature reliability of V TH based on the temperature-dependent characteristics in LDP-HEMTs. However, the temperature stability of the gate current (V GS = 7 V) will worsen in LDP-HEMTs due to the difference in the conduction mechanism, compared with conventional p-GaN HEMTs.

Low etching damage surface obtained by a mixed etching method and the influence of surface states on the C–V characteristics of AlGaN/GaN Schottky barrier diodes

A mixed etching method including ICP dry etching and digital etching (plasma oxidation and wet etching) to remove the p-GaN capping layer was investigated. The results indicated that mixed etching can effectively modify the surface damage induced by dry etching and get a smoother surface. Further research revealed that the existence of nitrogen-vacancy-related states (NVRS) in the devices, which was served as discharging centers, played a key role in the discharging effect of the C–V characteristics of Schottky barrier diodes (SBDs). Based on the discharging effect of NVRS, a charge-discharge C–V model was constructed, and demonstrated validity in cases of inadequately-etching of p-GaN and over-etching of AlGaN. This work demonstrates the discharging effect can be weakened by a retained p-GaN thin layer above the AlGaN barrier layer.

Study on H plasma treatment enhanced p-GaN gate AlGaN/GaN HEMT with block layer

&lt;sec&gt;High electron mobility transistors(HEMTs)show tremendous potentials for high mobility, high breakdown voltage, low conduction, low power consumption, and occupy an important piece of the microelectronics field. The high-resistivity-cap-layer high electron mobility transistor (HRCL-HEMT) is a novel device structure. Based on the hole compensation mechanism, the p-GaN is converted into high resistance semiconductor material by hydrogen plasma implantation. Thus, the surface of the p-GaN layer will have a serious bombardment damage under the hydrogen plasma implantation. In practical work, it is also very challenging in the accurate controlling of the hydrogen injection rate, injection depth and injection uniformity. To achieve the required depth of injection, the injected hydrogen plasma is often more than the required dose or multiple injections times. The energy of hydrogen plasma plays a huge influence on the surface of the p-GaN layer.The leakage current will be generated on the device surface, which deteriorates the electrical performance of the device.&lt;/sec&gt;&lt;sec&gt;In this work, to protect the surface of p-GaN layer, a 2-nm Al&lt;sub&gt;2&lt;/sub&gt;O&lt;sub&gt;3&lt;/sub&gt; film is deposited on the surface of the p-GaN cap layer to reduce the implantation damage caused by hydrogen plasma treatment. The research shows that after the device deposited Al&lt;sub&gt;2&lt;/sub&gt;O&lt;sub&gt;3&lt;/sub&gt; film prior to the hydrogen plasma treatment, the gate reverse leakage current is reduced by an order of magnitude, the ratio of &lt;i&gt;I&lt;/i&gt;&lt;sub&gt;ON&lt;/sub&gt; to &lt;i&gt;I&lt;/i&gt;&lt;sub&gt;OFF&lt;/sub&gt; is increased by about 3 times. Meanwhile, the OFF-state breakdown voltage is increased from 410 V to 780 V. In addition, when the bias voltage is 400 V, the values of dynamic &lt;i&gt;R&lt;/i&gt;&lt;sub&gt;ON&lt;/sub&gt; of devices A and B are 1.49 and 1.45 respectively, the device B shows a more stable dynamic performance. To analyze the gate leakage mechanism, a temperature-dependent current&lt;i&gt; I&lt;/i&gt;&lt;sub&gt;G&lt;/sub&gt;-&lt;i&gt;V&lt;/i&gt;&lt;sub&gt;G&lt;/sub&gt; testing is carried out, and it is found that the dominant mechanism of gate leakage current is two-dimensional variable range hopping (2D-VRH) at reverse gate voltage. The reason for reducing the gate reverse current is analyzed, and the Al&lt;sub&gt;2&lt;/sub&gt;O&lt;sub&gt;3&lt;/sub&gt; film increases the activation energy of trap level and changes the surface states of HR-GaN; furthermore, the Al&lt;sub&gt;2&lt;/sub&gt;O&lt;sub&gt;3&lt;/sub&gt; film blocks the injection of too much H plasma, thereby reducing the density of AlGaN barrier and channel trap states, and weakening the current collapse.&lt;/sec&gt;

P-GaN field plate for low leakage current in lateral GaN Schottky barrier diodes

High-voltage gallium nitride Schottky barrier diodes (SBDs) suffer from large off-state leakage current, which further degrades during operation at high temperatures and limits the device blocking capabilities. The key to achieving low off-state leakage is to protect the Schottky barrier from the high electric field, which is challenging by employing conventional field plate structures due to their large pinch-off voltage. In this work, we propose a simple AlGaN/GaN SBD architecture based on a p-GaN cap layer to achieve excellent off-state performance with a very low leakage current. By properly designing the AlGaN barrier and p-GaN cap, the pinch off-voltage of the p-GaN field plate is carefully controlled and the voltage drop over the Schottky junction is effectively reduced. In addition, a large carrier concentration in the access region is achieved, leading to a reduced sheet resistance. This results in good on-state performance along with a very low leakage current of ∼1 nA/mm at 400 V, which is maintained well below 100 nA/mm up to elevated temperatures of 150 °C. Moreover, the proposed architecture shares the well-established fabrication process of commercial p-GaN HEMTs and, thus, represents a promising and viable solution for future GaN diodes.

Wide-range-adjusted threshold voltages for E-mode AlGaN/GaN HEMT with a p-SnO cap gate

p-GaN cap layer has been recognized as a commercial technology to manufacture enhanced-mode (E-mode) AlGaN/GaN high electron mobility transistor (HEMT); however, the difficult activation of Mg doping and etching damage of p-GaN limit the further improvement of device performance. Thus, the more cost-effective cap layer has attracted wide attention in GaN-based HEMT. In this paper, p-type tin monoxide (p-SnO) was firstly investigated as a gate cap to realize E-mode AlGaN/GaN HEMT by both Silvaco simulation and experiment. Simulation results show that by simply adjusting the thickness (50 to 200 nm) or the doping concentration (3 × 1017 to 3 × 1018 cm−3) of p-SnO, the threshold voltage (Vth) of HEMT can be continuously adjusted in the range from zero to 10 V. Simultaneously, the device demonstrated a drain current density above 120 mA mm−1, a gate breakdown voltage (VBG) of 7.5 V and a device breakdown voltage (VB) of 2470 V. What is more, the etching-free AlGaN/GaN HEMT with sputtered p-SnO gate cap were fabricated, and achieved a positive Vth of 1 V, VBG of 4.2 V and VB of 420 V, which confirms the application potential of the p-SnO film as a gate cap layer for E-mode GaN-based HEMT. This work is instructive to the design and manufacture of p-oxide gate cap E-mode AlGaN/GaN HEMT with low cost.

Combination of selective area sublimation of p-GaN and regrowth of AlGaN for the co-integration of enhancement mode and depletion mode high electron mobility transistors

We report on the fabrication of an enhancement mode p-GaN/AlN/GaN high electron mobility transistor with selective area sublimation under vacuum of the p-GaN cap layer. The GaN evaporation selectivity is demonstrated on the thin 2 nm AlN barrier layer. Furthermore, the regrowth of AlGaN is a major key to increase the maximum drain current in the transistors and enables the co-integration with depletion mode devices.

Recessed-anode AlGaN/GaN diode with a high Baliga's FOM by combining a p-GaN cap layer and an anode-connected p-GaN buried layer

In this article, a recessed-anode AlGaN/GaN Schottky barrier diode with a p-GaN cap layer and an anode-connected p-GaN buried layer was proposed and optimized by Silvaco TCAD. The impact of different structural parameters on the trade-off between breakdown voltage and differential specific on-resistance were systematically investigated. Compared with the conventional recessed-anode SBD, the introduction of a p-GaN buried layer with an optimum distance from 2DEG channel can improve the breakdown voltage mildly, reduce the on-resistance and increase the surge current capability obviously at relatively high forward bias. Besides, a p-GaN cap layers slightly decreases the current density but demonstrates an obvious improvement in the breakdown voltage. Therefore, a combining of the p-GaN buried layer and the p-GaN cap layer is promising to achieve the better trade-off between on-resistance and breakdown voltage, resulting in a higher Baliga's FOM.

Impurity incorporation and diffusion from regrowth interfaces in N-polar GaN photocathodes and the impact on quantum efficiency

We investigate the mechanisms of growth interruption mediated interfacial impurity diffusion in N-polar GaN, and through this understanding, we offer an approach toward achieving high quantum efficiency III-nitride photocathode devices. N-polar photocathode structures consisting of a p-GaN active layer and a thin unintentionally doped GaN (u-GaN) cap layer were grown on an N-polar u-GaN template with varied growth interruptions at interfaces. Unintentionally incorporated oxygen and silicon impurity spikes at regrowth interfaces were measured by secondary ion mass spectrometry. Pipe and bulk diffusion of the oxygen impurity is observed from the regrowth interfaces when the overgrown layer required higher temperature growth, whereas only bulk diffusion is seen otherwise. Furthermore, the proximity of regrowth interfaces to the surface is observed to impact the diffusivity of oxygen. Growth interruption between the p-GaN active layer and cap layer resulted in a low quantum efficiency of 0.27%, while uninterrupted growth of the p-GaN/u-GaN cap photocathode achieved a quantum efficiency of 10.79%. We attribute the low quantum efficiency of the interrupted cap photocathode to the high density of oxygen within the active region of the device. Understanding of impurity incorporation at regrowth interfaces, dominating driving mechanisms behind diffusion of these species, and their impact on material properties are critical elements in designing high performing devices.

Study of AlGaN/GaN Vertical Superjunction HEMT for Improvement of Breakdown Voltage and Specific On-Resistance

A GaN-based vertical superjunction high electron mobility transistor (SJ HEMT) with a composite structure (CS-SJ HEMT) is proposed and analyzed by Silvaco TCAD to improve the breakdown voltage and specific on-resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">onA</sub> ). In this paper, CS-SJ HEMT is compared with SJ HEMT with traditional structure (TS-SJ HEMT), SJ HEMT with only particular doping pillars (DP-SJ HEMT) and SJ HEMT with only special P-gate (SP-SJ HEMT). The particular doping pillars mean the doping concentration of n-pillar increases with a gradient from top to bottom, and the concentration of p-pillar is the same as the middle of n-pillar, which reduces the R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">onA</sub> by only 4%. The special P-GaN cap layer can reduce the R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">onA</sub> by 10%, and it can even increase the on-state current in the saturation region. The CS-SJ HEMT combines both doping pillars and special P-gate structures, and the R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">onA</sub> can be reduced by 14%. By the optimized design, the R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">onA</sub> can be reduced by 30% with BV = 2580 V, or the R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">onA</sub> can be reduced by 21% with BV = 2720 V. These results show that the composite structure of SJ HEMT contributes to improving the BV and R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">onA</sub> and propose a useful approach for improving the vertical HEMTs.