P-channel Polycrystalline Silicon Thin Film Research Articles

A New Method for Defect Prediction of Polycrystalline Silicon TFTs with Realistic Grain Boundary Model

We investigate the deviation of threshold voltage (V<SUB>th</SUB>) of p-channel polycrystalline silicon thin film transistors (poly-Si TFTs) using a new GB (grain boundary) model that better reflects reality. And we proposed new method for defect prediction using by this new GB model. The new GB model reflects a gaussian distribution of grain size and GB position. And by introducing a new parameter (β) which represents the defect ratio between GB and grain, the Vth deviation that increases as the channel gets shorter can be matched with the actual measurement results. And we found that the increase in the Vth deviation in the short channel becomes larger as the number of defects increases in GB (as the β increases). And we found that the β is an important physical parameter to explain why the Vth deviation of the short channel is rapidly increased. In this way, using this β value in our GB model, it is possible to predict the relative density of defect states of GB in the poly-Si by monitoring the Vth deviation in short channel TFTs in the process of developing polycrystalline TFTs.

Downscaling effects on self-heating related instabilities in p-channel polycrystalline silicon thin film transistors

Downscaling of polycrystalline silicon (polysilicon) thin film transistors (TFTs) is currently pursued to improve device speed, and in the present work we analyze the effects of downscaling on the self-heating related instability. Experimental results show improved stability of scaled polysilicon TFTs operating at same power densities. To explain this effect we performed three-dimensional thermo-electric numerical simulations, indicating that channel temperature reduction occurs in the scaled devices due to enhanced lateral thermal dissipation. Therefore, the present results show that downscaling not only provides higher speed devices but also a route for reducing self-heating related instability in polysilicon TFTs.

Stress-Induced Hump Effects of p-Channel Polycrystalline Silicon Thin-Film Transistors

Positive bias temperature instability in p-channel polycrystalline silicon thin-film transistors is investigated. The stress-induced hump in the subthreshold region is observed and is attributed to the edge transistor along the channel width direction. The electric field at the corner is higher than that at the channel due to thinner gate insulator and larger electric flux density at the corner. The current of edge transistor is independent of the channel width. The electron trapping in the gate insulator via the Fowler-Nordheim tunneling yields the positive voltage shift. As compared to the channel transistor, more trapped electrons at the edge lead to more positive voltage shift and create the hump. The hump is less significant at high temperature due to the thermal excitation of trapped elections via the Frenkel-Poole emission.

The Reduction of the Dependence of Leakage Current on Gate Bias in Metal-Induced Laterally Crystallized p-Channel Polycrystalline-Silicon Thin-Film Transistors by Electrical Stressing

The high dependence of the leakage current on the gate bias that is normally observed in metal-induced laterally crystallized polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) can be reduced effectively by electrical stressing. This brief examined the mechanism for the decrease in the high dependence of the leakage current on the gate bias in p-channel poly-Si TFTs by electrical stressing. This effect increased with increasing stress bias that is applied to the gate or drain. The effective decrease in leakage current dependence on the gate bias was attributed to electron trapping in the gate oxide during electrical stressing. It was found that this trapping occurred near the drain junction, and electron detrapping (or trap site regeneration) was also observed after annealing at temperatures above 350degC, resulting in an increase in leakage current. This brief proposes a device structure with a low dependence of the leakage current on the gate bias through light doping at the drain region.

Hot-carrier effects in p-channel polycrystalline silicon thin film transistors

The effects of hot carriers on the electrical characteristics of polycrystalline silicon p-channel thin film transistors have been analyzed, combining experimental data and numerical simulations. The transfer characteristics showed minor variations upon application of prolonged bias stress, while the output characteristics presented a reduction of kink effect. These results have been explained by using a self-consistent model based on the trapping of injected hot electrons. The authors’ charge injection model provided a precise evaluation of the extension of the trapped charge regions, at both front and back interfaces. By using such trapped charge distributions, it was possible to reproduce the output characteristics variations as well as the minor on-current increase observed in the transfer characteristics after bias stress.

Mechanism of the DC Bias Stressing in Metal Induced Laterally Crystallized P-Channel Polycrystalline Silicon Thin Film Transistor

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Polycrystalline silicon thin-film transistors fabricated by rapid Joule heating method

We report n- and p-channel polycrystalline silicon thin film transistors (poly-Si TFTs) fabricated with a rapid joule heating method. Crystallization of 50-nm-thick silicon films and activation of phosphorus and boron atoms were successfully achieved by rapid heat diffusion via 300-nm-thick SiO/sub 2/ intermediate layers from joule heating induced by electrical current flowing in chromium strips. The effective carrier mobility and the threshold voltage were 570 cm/sup 2//Vs and 1.8 V for n-channel TFTs, and 270 cm/sup 2//Vs and -2.8 V for p-channel TFTs, respectively.

Application of Rapid Joule Heating Method to Fabrication of Polycrystalline Silicon Thin Film Transistors

We report the rapid crystallization of silicon films with a joule heating method and its application to the fabrication of n-channel and p-channel polycrystalline silicon thin film transistors (poly-Si TFTs). Crystallization of 50-nm-thick silicon films and activation of dopant atoms were successfully achieved by rapid heat diffusion via 300-nm-thick SiO2 intermediate layers from joule heating induced by electrical current flowing in chromium strips. The average grain size was about 100 nm in crystallized films. A high electrical conductivity of 2050 S/cm was achieved for 1.3×1021-cm-3-phosphorus doped silicon films. TFTs have a carrier mobility and a threshold voltage of 570 cm2/Vs and 1.8 V for n-channel TFTs, and 270 cm2/Vs and -2.8 V for p-channel TFTs, respectively.

Stability of Non-Hydrogenated and Hydrogenated P-Channel Polycrystalline Silicon Thin-Film Transistors

ABSTRACTThe effects of high gate voltage Vg stress on the stability of non-hydrogenated and hydrogenated short p-channel polysilicon thin-film transistors (TFTs) are investigated for operation in the saturation region. The degradation mechanisms were identified from the evolution with stress time of the static device parameters. In non-hydrogenated TFTs, transconductance overshoot and a turnover behavior in the threshold voltage were observed. The results indicate that hot-electron trapping near the drain dominates in the initial stages of stress and channel holes are injected into the gate oxide followed by interface states generation as the stress proceeds further. In hydrogenated TFTs, first an effective shortening of the channel length is observed due to trapping of hot-electrons. As the stress proceeds further, donor-type interface states are generated and the electric field near the drain increases due to built-up of positive charge resulted from trapping of hot-holes in these states.

Dimensional Effects on the Drain Current of N- and P-Channel Polycrystalline Silicon Thin Film Transistors

N-channel and p-channel polysilicon thin film transistors (poly-Si TFTs) with different geometries were fabricated and characterized to study the interactive effects of active channel area on drain current. We find that for both non-passivated and passivated p-TFTs, since no avalanche multiplication is involved, the drain current is increased with reduced active channel area due to the reduction of grain-boundary trap density. In contrast, a somewhat unexpected trap dependence of the kink effect is observed in n-TFTs. Consequently, the dependence of active channel area on drain current differs between non-passivated n-TFTs with large trap density and passivated n-TFTs with small trap density.

Ultra-thin silicon-oxide films by sputter-deposition and their application to high-quality poly-Si TFTS

This paper describes ultra-thin high-quality silicon oxide (SiO 2) films deposited at low temperature by sputtering from a SiO 2 target in an oxygen–argon mixture. SiO 2 films up to a thickness of 6.5 nm are successfully formed on polycrystalline silicon (poly-Si) films which have a surface roughness of several nanometers. The SiO 2 films show electrical properties with a sufficiently high breakdown voltage and low leakage current which are comparable with the electrical properties of the thermally grown SiO 2 film on single-crystalline Si at high temperature. Moreover, both n- and p-channel polycrystalline silicon thin film transistors (poly-Si TFTs) with ultra-thin sputtered SiO 2 films show excellent characteristics.

Charge pumping in thin film transistors

Charge pumping (CP) has been used to study defects in p-channel poly-crystalline silicon thin film transistors (TFTs). At high frequencies (>∼1 kHz), we observe anomalous CP behavior in TFTs due to (a) the high resistivity of, and/or slow electron trapping in, the poly-Si channel and (b) the existence of a TFT drain offset region. At low frequencies, the CP technique still appears to provide a useful measure of the TFT grain boundary defect density.