P-channel MOS Transistors Research Articles

An Ultra-Low-Voltage Approach to Accurately Set the Quiescent Current of Digital Standard Cells Used for Analog Design and Its Application on an Inverter-Based Operational Transconductance Amplifier

An approach to design analog building blocks based on digital standard cells is presented in this work. By ensuring that every CMOS inverter from a standard-cell library operates with a well-defined quiescent current and output voltage, the suggested method makes it possible to construct analog circuits that are resistant against PVT variations. The method uses the local supply voltages connected to the source terminals of the p-channel and n-channel MOS transistors of the standard-cell inverters as control inputs. It is based on adaptive supply voltage generator (ASVG) reusable blocks, which are comparable to those used in digital applications to handle process variations. All of the standard-cell inverters used for analog functions receive the local supply voltages produced by the ASVGs, which enable setting each cell’s quiescent current to a multiple of a reference current and each cell’s static output voltage to an appropriate reference voltage. Both the complete custom design of the ASVG blocks and a theoretical study of the feedback loop of the ASVG are presented. An application example through the design of a fully synthesizable two-stage operational transconductance amplifier (OTA) is also provided. The TSMC 180 nm CMOS technology has been used to implement both the OTA and the ASV generators. Simulation results have demonstrated that the proposed approach allows to accurately set the quiescent current of standard-cell inverters, dramatically reducing the effect of PVT variations on the pmain performance parameters of the standard-cell-based two-stage OTA.

Low-Voltage LDO Regulator Based on Native MOS Transistor with Improved PSR and Fast Response

In this paper, a low-voltage low-dropout analog regulator (ALDO) based on a native n-channel MOS transistor is proposed. Application of the native transistor with the threshold voltage close to zero allows elimination of the charge pump in low-voltage regulators using the pass element in a common drain configuration. Such a native pass transistor configuration allows simplification of regulator design and improved performance, with supply voltages below 1 V, compared to commonly used regulators with p-channel MOS transistors. In the presented design of ALDO regulator in 180 nm CMOS X-FAB technology, an output voltage of 0.7 V was achieved with an output current of 10 mA and a supply voltage of 0.8 V. Simulation results show that despite the low supply voltage, output voltage spikes do not exceed 70 mV at the worst technology corner when output current transients from 100 µA to 10 mA. Under such conditions, stable operation and power supply rejection PSR = 35 dB were achieved with an output capacitance of 0–500 pF. The proposed regulator allows to push the limit of ALDO regulator applications to voltages below 1 V with only slight degradation of its performance.

A novel PMOS transistors based first-order all-pass network

In this paper, a new voltage-mode first-order all-pass network is introduced. It is realized by using only four p-channel metal–oxide–semiconductor transistors, one resistor and one capacitor. The proposed filter enjoys the feature of high input impedance and does not require any additional current source. It is also free from any kind of passive element matching constraint. In order to test the workability of the proposed structure, a second-order all-pass network and quadrature oscillator are presented. Personal simulation program with integrated circuit emphasis using 0.18 µm, level-7 complementary metal-oxide-semiconductor process parameters with ± 0.9 V supply voltages are used to validate the performance of the proposed structure.

Total ionizing dose radiation hardening technology based on double-charge multiple-step ion implantation

This paper describes the total ionizing dose (TID) radiation hardening of buried oxide in separation by implantation of oxygen silicon on insulator (SOI) substrates. In this study, 0.5-μm partially depleted SOI complementary metal–oxide–semiconductor (CMOS) transistors and circuits were prepared using double-charge multiple-step ion implantation and annealing, and the changes in the drive current, leakage current, and threshold voltage of the CMOS transistor under different TID radiation conditions were compared. Under a TID of 500 k Rad(Si), radiation-hardened H-type N-channel metal–oxide–semiconductor transistors had a threshold voltage drift of <100 mV in the worst case, and H-type P-channel metal–oxide–semiconductor transistors had a threshold voltage drift of <150 mV. Under a TID of 1 Mrad(Si), CMOS transistors showed no significant increase in leakage current caused by TID radiation. Under a TID of 500 k Rad(Si), the standby current of the radiation-hardened 32-bit DSP was <1.5 mA. The high-density integrated circuits prepared using this technology performed well under harsh ionizing radiation environments. Finally, this technology was compared with similar foreign technologies and TID-unhardened wafers with hardened wafers. This technology reached the international advanced level among equivalent technologies regarding hole capture cross section and maximum threshold voltage drift in the model. PACS85.30.De 85.30.-e.

A Biasing Approach to Design Ultra-Low-Power Standard-Cell-Based Analog Building Blocks for Nanometer SoCs

This paper presents an approach to design analog building blocks for nanometer systems on a chip (SoCs) that are based on digital standard-cells. The proposed approach guarantees that all the CMOS inverters, taken from a standard-cell library, operate with well-defined quiescent current and output voltage, thus allowing the implementation of analog circuits with good robustness against PVT variations. The approach is based on an Analog Body Bias Generator (ABBG) reusable block, similar to the ones adopted in digital applications to cope with process variations, and exploits the bulk terminals of both the p-channel and n-channel MOS transistors of the standard-cell inverter as current and voltage control inputs. The bulk voltages generated by the ABBG are routed to all the standard-cell inverters used for analog functions and allow to set the quiescent current of each cell to a multiple of a reference current and the static output voltage of each cell to half the supply voltage. The full custom design of the ABBG is presented, as well as the design flow to allow the automatic place and route of the proposed standard-cell based analog building blocks. We finally give an example of application trough the design of a fully synthesizable four-stage-gain low-power operational transconductance amplifier (OTA). Both the body bias generator and the OTA have been implemented in a 65-nm CMOS technology. The OTA nominal current consumption is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.75~\mu \text{A}$ </tex-math></inline-formula> with 0.41- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> standard deviation. Good robustness against supply and temperature variations is also found.

Design and mathematical analysis of a 7T SRAM cell with enhanced read SNM using PMOS as an access transistor

PurposeThis work is proposed for low power energy-efficient applications like laptops, mobile phones, and palmtops. In this study, P-channel metal–oxide–semiconductor (PMOS)’s are used as access transistor in 7 transistors (7 T) Static Random Access Memory (SRAM) cell, and the theoretical Static Noise Margin (SNM) analysis for the proposed cell is also performed. A cell is designed using 7 T which consists of 4 PMOS and 3 NMOS. In this paper write and hold SNM is addressed and read SNM is also calculated for the proposed 7 T SRAM cell.Design/methodology/approachThe authors have replaced N-channel metal–oxide–semiconductor (NMOS) access transistors with the PMOS access transistors, which results in proper data line recovery and provides the desired coupling. An error is likely to occur, if the read operation is performed too often probably by using the NMOS pass gate. It results in an improper recovery of the data line. Instead, by using PMOS as a pass gate, the time required for read operation can be brought down. As we know the mobility (µ) of the PMOS transistor is low, so the authors have used this property into the proposed design. When a low signal is applied to its control gate, the PMOS transistor come up with the desired coupling, when working as a pass gate.FindingsFeedback switched transistor is used in the proposed circuit, which plays an important role in the write operation. This transistor is in OFF state and PMOS’s work as access transistor, when the proposed cell operating in read mode. This helps in the reduction of power. This work is simulated using UMC 40 nm technology node in the cadence virtuoso environment. The simulated result shows that, write power saving of 51.54% and 61.17%, hold power saving of 25.68% and 48.93% when compared with reported 7 T and 6 T, respectively.Originality/valueThe proposed 7 T SRAM cell provides proper data line recovery at a lower voltage when PMOS works as the access transistor. Power consumption is very less in this technique and it is best suitable for low power applications.

Total dose measurements by p-channel transistors of ICs

In this paper, a new approach of p-channel MOS-transistors used for total dose monitoring at semiconductor components under radiation is presented. The calibration results enable to determine the numerical parameters for the MOSFETs electro-physical model of dose effects. We propose to calculate the total dose of ionization flux using the results of MOS-transistors drain current measurements, under a fixed gate and drain voltage.

SUBHDIP: process variations tolerant subthreshold Darlington pair‐based NBTI sensor circuit

Aggressive technology scaling has inevitably led to reliability becomes a major concern for modern high-speed and high-performance integrated circuits. The major reliability concerns in nanoscale very-large-scale integration design are the time-dependent negative bias temperature instability (NBTI) degradation. Owing to increasing vertical oxide field and higher operating temperature, the threshold voltage of P-channel MOS transistors increases with time under NBTI. This study presents a novel subthreshold Darlington pair-based NBTI degradation sensor under the stress conditions. The proposed sensor provides the high degree of linearity and sensitivity under subthreshold conditions. The Darlington pair used in the circuit provides the stability and the high-input impedance of the circuit makes it less affected by the process variations. Owing to high sensitivity, the proposed sensor is best suited for sensing of temperature variation, process variation, and temporal degradation during measurement. The sensitivity of the proposed sensor at room temperature is 0.239 mV/nA under subthreshold conditions. The proposed sensor is less affected by the process variation and has the maximum deviation of 0.0011 mV at standby leakage current of 30 nA.

Model for Charge Accumulation in n- and p-MOS Transistors during Tunneling Electron Injection from a Gate

A quantitative model for charge accumulation in an undergate dielectric during tunneling electron injection from a gate according to the Fowler–Nordheim mechanism is developed. The model takes into account electron and hole capture at hydrogen-free and hydrogen-related traps as well as the generation of surface states during the interaction of holes with hydrogen-related centers. The experimental dependences of the threshold voltage shift and gate voltage shift of n- and p-channel MOS (metal–oxide–semiconductor) transistors on the injected charge in the constant current mode are analyzed based on the model.

Effects of consecutive irradiation and bias temperature stress in p-channel power vertical double-diffused metal oxide semiconductor transistors

The mechanisms responsible for the effects of consecutive irradiation and negative bias temperature (NBT) stress in p-channel power vertical double-diffused MOS (VDMOS) transistors are presented in this paper. The investigation was performed in order to clarify the mechanisms responsible for the effects of specific kind of stress in devices previously subjected to the other kind of stress. In addition, it may help in assessing the behaviour of devices subjected to simultaneous irradiation and NBT stressing. It is shown that irradiation of previously NBT stressed devices leads to additional build-up of oxide trapped charge and interface traps, while NBT stress effects in previously irradiated devices depend on gate bias applied during irradiation and on the total dose received. In the cases of low-dose irradiation or irradiation without gate bias, the subsequent NBT stress leads to slight further device degradation. On the other hand, in the cases of devices previously irradiated to high doses or with gate bias applied during irradiation, NBT stress may have a positive role, as it actually anneals a part of radiation-induced degradation.

Effect of Body Bias on NBTI of p-MOSFETs

The effect of the body bias on the stability of the threshold voltage of p+ polysilicon gate p-channel MOS (pMOS) transistors stressed in the on-state is investigated. Special attention is given to pMOS transistors operating at low gate overdrive and non-zero body voltage. A mixed mode of degradation, including the usual negative bias temperature instability (NBTI) and the effect of hot-hole injection (HHI) into the gate oxide at high temperature, is reported. The relative importance of both the electric field in the gate oxide and the concentration of cold holes at the interface is pointed out for devices operating in the near threshold region. A kinetic model for NBTI/HHI is proposed.

Investigation of Threshold Voltage Shift in Gamma Irradiated N-Channel and P-Channel MOS Transistors of CD4007

Investigation of Threshold Voltage Shift in Gamma Irradiated N-Channel and P-Channel MOS Transistors of CD4007

Superior NBTI in High-k SiGe Transistors–Part II: Theory

The susceptibility of conventional silicon p-channel MOS transistors to negative bias temperature instabilities (NBTIs) is a serious threat to further device scaling. One possible solution to this problem is the use of a SiGe quantum-well channel. The introduction of a SiGe layer, which is separated from the insulator by a thin Si cap layer, not only results in high mobilities but also superior reliability with respect to NBTI. In part one of this paper, we provide experimental evidence for reduced NBTI by thoroughly studying single traps in nanoscale devices. In this paper, we present detailed TCAD simulations and employ the four-state nonradiative multiphonon model to determine the energetical and spatial positions of the identified single traps. The found trap levels agree with the defect bands estimated in large-area devices. Our conclusions are also supported by the observation of similar activation energies for defects present in transistors of various device geometries. From the calibrated TCAD simulations data, an impressive boost of the time-to-failure for the SiGe transistor can be predicted and explained.

TheI-VCharacteristic Prediction of BCD LV pMOSFET Devices Based on an ANFIS-Based Methodology

Comprehensive and predictive modeling of submicron devices using the traditional TCAD EDA tools of device simulation has become increasingly perplexing due to a lack of reliable models and difficulties in calibrating available device models. This paper proposes a new technique to model BCD submicron pMOSFET devices and to predict device behaviors under different bias conditions and different geometry dimensions by using the adaptive neurofuzzy inference system (ANFIS), which combines fuzzy theory and adaptive neuronetworking. Here, the power of using ANFIS to realize theI-Vbehaviors is demonstrated in these p-channel MOS transistors. After a systematic evaluation, it can be found that the predicting results ofI-Vbehaviors of complicated submicron pMOSFETs by ANFIS are compared with the actual diagnostic experiment data, and a good agreement has been obtained. Furthermore, the error percentage was no greater than 2.5%. As such, the demonstrated benefits of this new proposed technique include precise prediction and easier implementation.

Single event transients in a 0.18 m partially-depleted silicon-on-insulator complementary metal oxide semiconductor circuit

Single event transients (SETs) in a 100 series 0.18 m partially- depleted silicon-on-insulator (PDSOI) complementary metal oxide semiconductor (CMOS) inverter chain are studied by using pulsed laser. In this paper, effects of struck transistor type and struck locations on the threshold laser energy and the pulse width of SETs are investigated. Results show that the threshold laser energies at different locations are similar, but the threshold laser energies of n-channel metal-oxide-semiconductor (NMOS) transistors are much smaller than that of p-channel metal-oxide-semiconductor (PMOS) transistors. The SET pulse width of n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET) is 427.5 ps as measured at the output terminal when the 2nd stage is irradiated, and 287.4 ps when the 100th stage is irradiated; the SET pulse width of p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) is 295.9 ps as measured at the output terminal when the 1st stage is irradiated, and 150.5 ps when the 99th stage is irradiated. Both broadening rates are about 1.4 ps/stage. When the struck locations are close to the output terminal of the chain, the SET pulse is narrowed; however, when the struck nodes are close to the input terminal, the SET pulse is broadened. SET pulses are progressively broadened up when propagating is along inverter chains. A similar broadening rate in neither NMOSFET nor PMOSFET, indicates that the SET pulse broadening effect is caused by propagation, independent of the type of struck transistors. Through analysis, the charge of floating body-induced threshold voltage hysteresis in PDSOI transistors is the main cause of pulse broadening. The positive SET pulse observed on the oscilloscope, contrary to the expectation, is due to charging and discharging of the output node capacitor. Also, the observed sub-rail-to-rail swings of the SET pulses are due to the voltage division between the internal resistance of the oscilloscope and the resistance of the PMOS transistor.

Surface photovoltage method for the quality control of silicon epitaxial layers on sapphire

The surface photovoltage method is used to study “silicon-on-sapphire” epitaxial layers with a thickness of 0.3–0.6 μm, which are used to fabricate p-channel MOS (metal—oxide-semiconductor) transistors with improved radiation hardness. It is shown that the manner in which the photoconductivity of the epitaxial layer decays after the end of a light pulse generated by a light-emitting diode (wavelength ∼400 nm) strongly depends on the density of structural defects in the bulk of the structure. This enables control over how a “silicon-on-sapphire” structure is formed to provide the manufacturing of MOS structures with optimal operating characteristics.

Hybrid Forward and Backward Threshold-Compensated RF-DC Power Converter for RF Energy Harvesting

This paper presents a hybrid forward and backward threshold voltage compensated radio-frequency to direct current (RF-to-DC) power conversion circuit for RF energy harvesting applications. The proposed circuit uses standard p-channel metal-oxide semiconductor transistors in all the stages except for the first few stages to allow individual body biasing eliminating the need for triple-well technology in the previously reported forward compensation schemes. Two different RF-DC power conversion circuits, one optimized to provide high power conversion efficiency (PCE) and the other to produce a large output DC voltage harvested from extremely low input power levels, are designed and fabricated in IBM's 0.13 μm complementary metal-oxide-semiconductor technology. The first circuit exhibits a measured maximum PCE of 22.6% at -16.8 dBm (20.9 μW) and produces 1 V across a 1 MΩ load from a remarkably low input power level of -21.6 dBm (6.9 μW) while the latter circuit produces 2.8 V across a 1 MΩ load from a peak-to-peak input voltage of 170 mV achieving a voltage multiplication ratio of 17. Also, design strategies are developed to enhance the output DC voltage and to optimize the PCE of threshold voltage compensated voltage multiplier.

(Invited) Multilevel Cell Nonvolatile Memory with Field-effect Transistor Using Crystalline Oxide Semiconductor

Multilevel cell nonvolatile memory has been developed with a field-effect transistor (FET) containing a crystalline oxide semiconductor (OS), specifically c-axis aligned crystalline In-Ga-Zn-oxide (CAAC-IGZO). The memory is called nonvolatile oxide semiconductor random access memory (NOSRAM). A NOSRAM cell consists of a CAAC-IGZO FET, a p-channel MOS (PMOS) transistor, and a cell capacitor. We have demonstrated that a single 3-bit NOSRAM cell has an endurance of 1012 cycles and a write time of 5 ns. The 6σ tolerance for cell V th distribution of a test chip including an 18-kbit NOSRAM cell array is 109 mV. The test chip achieves a 3-bit/cell NOSRAM.

Impact of both metal composition and oxygen/nitrogen profiles on p-channel metal-oxide semiconductor transistor threshold voltage for gate last high-k metal gate

As transistor size continues to shrink, SiO2/polySi has been replaced by high-k/metal gate (HKMG) to enable further scaling. Two different HKMG integration approaches have been implemented in high volume production: gate first and gate last—the latter is also known as replacement gate approach. In both integration schemes, getting the right threshold voltage (Vt) for NMOS and PMOS devices is critical. A number of recent studies have shown that Vt of devices is highly dependent on not just the as deposited material properties but also on subsequent processing steps. In this work, the authors developed an advanced high-resolution electron energy loss spectroscopy method capable of accurate measurement of material composition on device structures. Using this method, the nitrogen and oxygen concentration at the HKMG interface on p-channel field-effect transistor (PFET) transistors with slightly different metal gate stacks were studied. The authors demonstrated that the correct amount of nitrogen and oxygen at the HKMG interface is required to get the right PFET Vt.

A New Method for Negative Bias Temperature Instability Assessment in P-Channel Metal Oxide Semiconductor Transistors

In this paper, we present a new method, named on the fly oxide trap (OTFOT), to extract the bias temperature instability (BTI) in MOS transistors. The OTFOT method is based on charge pumping technique (CP) at low and high frequencies. We emphasize on the theoretical-based concept, giving a clear insight on the easy-use of the OTFOT methodology and demonstrating its viability to characterize the negative BTI (NBTI). Using alternatively high and low frequencies, OTFOT method separates the interface-traps (ΔNit) and border-trap (ΔNbt) (switching oxide-trap) densities independently and also their contributions to the threshold voltage shift (ΔVth), without needing additional methods. The experimental results, from two experimental scenarios, showing the extraction of NBTI-induced shifts caused by interface- and oxide-trap increases are also presented. In the first scenario, all stresses are performed on the same transistor. It exhibits an artifact value of exponent n. In the second scenario, each voltage stress is applied only on one transistor. Its results show an average n of 0.16, 0.05, and 0.11 for NBTI-induced ΔNit, ΔNbt, ΔVth, respectively. Therefore, OTFOT method can contribute to further understand the behavior of the NBTI degradation, especially through the threshold voltage shift components such as ΔVit and ΔVot caused by interface-trap and border-trap, respectively.