P-channel MOSFETs Research Articles

Characterization and quantitative understanding of subthreshold swing of Si metal–oxide–semiconductor field effect transistors at cryogenic temperatures

The temperature and drain current (ID) dependencies of sub-threshold swing (SS) values of Si n- and p-channel metal–oxide–semiconductor field effect transistors (MOSFETs) with different substrate impurity concentrations ranging from the 1015 to 1018 cm−3 ranges are systematically and experimentally evaluated at cryogenic temperatures. It is found that SS of p-channel MOSFETs tends to increase with decreasing temperature, which contrasts with saturation of SS of n-MOSFETs at cryogenic temperatures, well reported by many previous works. To explain these SS behaviors quantitatively, we employ a density-of-state (DOS) model with tail states consisting of localized states in a deep energy range and mobile states in a shallow energy range, which are attributable to potential fluctuations caused by substrate impurities. It is shown that this model can quantitatively explain the temperature and ID dependencies of SS of both n-MOSFETs and p-MOSFETs. Then, we are assuming that the Si p-MOSFET has a higher density of localized states than the n-MOSFET. Thus, the increase in SS of the p-MOSFETs with decreasing temperature is explained by an increase in the density of localized states at the Fermi level with decreasing temperature, because the density of localized states increases with elevating the Fermi level position in the employed DOS model.

Investigation of performance-enhanced GaN-based E-mode p-channel MOSFET with pre-ohmic-annealing treatment

Pre-ohmic-annealing (POA) treatment of P-GaN/AlN/AlGaN epitaxy under N2 atmosphere was demonstrated to effectively achieve good p-type ohmic contact as well as decreased epitaxy sheet resistance. Ohmic contact resistance (R c) extracted by transfer length method reduced from 38 to 23 Ω·mm with alleviated contact barrier height from 0.55 to 0.51 eV after POA treatment. X-ray photoelectron spectroscopy and Hall measurement confirmed that POA treatment was able to reduce surface state density and improve the hole concentration of p-GaN. Due to the decreased R c and improved two-dimensional hole gas (2DHG) density, an outstanding-performance GaN E-mode p-channel MOSFET was successfully realized.

Ge quantum well channel P-MOSFET for 2.45 GHz wireless weak energy harvesting

Wireless energy harvesting is an important application of microwave wireless energy transmission system, but due to the weak energy of RF signals in the 2.45 GHz band, its rectification efficiency is not ideal. As one of the core rectifier components of wireless weak energy harvesting system, the performance of MOSFET determines the rectification efficiency of the system, and its optimized design to improve the rectification efficiency is an important direction of current research in the field. In view of this, this paper proposes and designs Ge quantum well channel PMOS for wireless weak energy harvesting at 2.45 GHz, aiming to improve the rectification efficiency of wireless weak energy harvesting systems. Starting from adjusting the structural physical parameters of the MOS tubes, the absolute value of the threshold voltage is reduced in the weak energy density region, which in turn improves the rectification efficiency of the device. Then, the novel diode connection with the introduction of substrate bias effect is compared with the conventional connection using an ADS simulation circuit, and the simulation results show that the leakage current is smaller and the rectification efficiency is higher under the novel connection. On this basis, a Ge quantum well channel PMOS device is proposed. Compared with the Ge surface channel, the hole mobility of the quantum well channel will be greatly improved, and its rectification efficiency can also be improved. The device is connected to the rectifier circuit with a novel connection and simulated using Silvaco's Mixedmode module. The results show that the rectification efficiencies of the Ge quantum well channel MOS reach 13.53 % and 32 % at low input powers of −20.34 dBm and −6.28 dBm, respectively, which are 3.3 and 1.14 times higher than those of the conventional surface channel MOS.

Numerical modeling of total dose effects on CD4007 MOSFET during switched-bias irradiation

The response of commercial-off-the-shelf CD4007 p-channel MOSFET exposed to 60Co radiation under switched-bias conditions is studied by real time monitoring the threshold voltage evolution with accumulated dose. The possibility to employ switched-bias techniques to recover threshold voltage is demonstrated. As reported for other devices, non-monotonic responses are observed. A physics-based numerical model that takes into account both charge buildup within the oxide and generation of interface traps is employed to reproduce the experimental results. The implications for dosimetry are discussed.

Effect of Yttrium Treatment on Germanium-Oxide-Based Interfacial Layer of Ge P-Channel Metal–Oxide–Semiconductor Field-Effect Transistor Fabricated Through in Situ Plasma-Enhanced Atomic Layer Deposition

Effect of Yttrium Treatment on Germanium-Oxide-Based Interfacial Layer of Ge P-Channel Metal–Oxide–Semiconductor Field-Effect Transistor Fabricated Through in Situ Plasma-Enhanced Atomic Layer Deposition

Combined Fabrication and Performance Evaluation of TOPCon Back‐Contact Solar Cells with Lateral Power Metal‐Oxide‐Semiconductor Field‐Effect Transistors on a Single Substrate

Nowadays, an increasing share of photovoltaic (PV) systems makes use of module‐ or submodule‐level power electronics (PE). Furthermore, PE is used in stand‐alone devices powered by PV‐storage solutions. One way to facilitate further implementation of PE in PV applications is to integrate PE components into crystalline silicon PV cells. Herein, the COSMOS device is introduced, denoting COmbined Solar cell and metal‐oxide‐semiconductor field‐effect transistor (MOSFET). Specifically, the combined manufacturing of lateral power MOSFETs and interdigitated back contact solar cells with tunnel‐oxide passivated contacts (TOPCon) on a single wafer is reported. Many steps of the proposed process flow are used for the fabrication of both devices, enabling cost‐effective integration of the MOSFET. Both n‐type solar cells with integrated p‐channel MOSFETs (PMOS) and p‐type solar cells with integrated n‐channel MOSFETs (NMOS) are successfully manufactured. NMOS devices perform better in achieving low on‐resistance, while PMOS devices exhibit lower leakage currents. Furthermore, the study reveals integration challenges where off‐state leakage currents of the MOSFET can increase due to illumination and specific configurations of monolithic interconnections between the MOSFET and the solar cell. Nevertheless, for both n‐type and p‐type solar cells, efficiencies exceeding 20% are achieved, highlighting the potential of the proposed process for COSMOS devices.

Reduction of Low Frequency Noise of Buried Channel PMOSFETs With Retrograde Counter Doping Profiles

Reduction of Low Frequency Noise of Buried Channel PMOSFETs With Retrograde Counter Doping Profiles

Evaluation of a comprehensive power management system with maximum power point tracking algorithm for multiple microbial fuel cell energy harvesting

This study presents a comprehensive power management system (PMS) capable of tracking the maximum power point (MPP) and harvesting the energy from up to five microbial fuel cells (MFCs). The harvested energy from the MFCs was used to power the electronics, and in cases where this power was insufficient, alternative backup power options can be used. The voltage can be increased up to 3.3 V, and a hysteresis-based control approach was utilised to regulate the output voltage. The MPP of each MFC was determined using a variable step size incremental conductance algorithm that controls the duty cycle of the synchronous boost converters. No additional electronic components are necessary for the operation of the N and P-channel MOSFETs. The efficiency of the PMS relies on the target output voltage and the power output characteristics of the MFCs. Efficiencies of up to 87 % were achieved by combining the outputs of each MFC boost converter. To save energy, some electronic components are disabled when not in use, and the maximum power consumption of the PCB is below 5.8 mW at an output voltage of 3.3 V. The PMS is applied to simulated and real tubular MFCs under various operating conditions.

Different temperature dependence of mobility in n- and p-channel 4H-SiC MOSFETs

The impact of interface state density (D it) near the conduction band edge (E C) and the VB edge (E V) on the field-effect mobility (μ FE) of NO- and N2-annealed n- and p-channel MOSFETs was investigated. With lowering the temperature, μ FE of n-channel MOSFETs decreased whereas μ FE increased in p-channel devices. Despite the comparable D it values near E C and E V, p-channel MOSFETs have less trapped carriers due to a deeper surface Fermi level caused by the larger effective masses of holes, resulting in smaller Coulomb scattering, and this may cause the different temperature dependence of μ FE in n- and p-channel MOSFETs.

A modelling method of the on-state resistance of p-channel power MOSFETs under NBTI stress

Negative Bias Temperature Instability (NBTI) of p-channel power MOSFETs is a primary concern in gate oxide degradation. Instead of a qualitative conclusion, predicting the degradation in the on-state resistance during long-term operation is significant. This paper evaluates the degradation of each component of the on-state resistance under NBTI stress. By dividing the on-state resistance into two parts based on whether it is affected by NBTI, we obtain a first-order linear model form to model the on-state resistance. This study can support the physical modelling and the remaining useful life prediction of the on-state resistance in long-term operation.

Impact of an Underlying 2DEG on the Performance of a p-Channel MOSFET in GaN.

The influence of an underlying 2-dimensional electron gas (2DEG) on the performance of a normally off p-type metal oxide semiconductor field effect transistor (MOSFET) based on GaN/AlGaN/GaN double heterojunction is analyzed via simulations. By reducing the concentration of the 2DEG, a greater potential can be dropped across the GaN channel, resulting in enhanced electrostatic control. Therefore, to minimize the deleterious impact on the on-state performance, a composite graded back-to-back AlGaN barrier that enables a trade-off between n-channel devices and Enhancement-mode (E-mode) p-channel is investigated. In simulations, a scaled p-channel GaN device with LG = 200 nm, LSD = 600 nm achieves an ION of 65 mA/mm, an increase of 44.4% compared to a device with an AlGaN barrier with fixed Al mole fraction, ION/IOFF of ∼1012, and |Vth| of | - 1.3 V|. For the n-channel device, the back-to-back barrier overcomes the reduction of ION induced by the p-GaN gate resulting in an ION of 860 mA/mm, an increase of 19.7% compared with the counterpart with the conventional barrier with 0.5 V positive Vth shift.

A 20 A bipolar current source with 140 μA noise over 100 kHz bandwidth

The precise control of direct current (dc) magnetic fields is crucial in a wide range of experimental platforms, from ultracold quantum gases and nuclear magnetic resonance to precision measurements. In each of these cases, the Zeeman effect causes quantum states to shift in energy as a function of the magnetic field. The development of low-noise current sources is essential because electromagnets are the preferred tool to dynamically control the magnetic field. Here, we describe an ultra-low noise bipolar current source using pairs of complementary n- and p-channel metal–oxide–semiconductor field-effect transistors controlled by zero-drift operational amplifiers. Our source has a 90 kHz inherent bandwidth and provides current from −20 to 20 A with noise (0.1 Hz to 100 kHz) of 140 µA at ±20 A.

A False Trigger-Strengthened and Area-Saving Power-Rail Clamp Circuit with High ESD Performance.

A power clamp circuit, which has good immunity to false trigger under fast power-on conditions with a 20 ns rising edge, is proposed in this paper. The proposed circuit has a separate detection component and an on-time control component which enable it to distinguish between electrostatic discharge (ESD) events and fast power-on events. As opposed to other on-time control techniques, instead of large resistors or capacitors, which can cause a large occupation of the layout area, we use a capacitive voltage-biased p-channel MOSFET in the on-time control part of the proposed circuit. The capacitive voltage-biased p-channel MOSFET is in the saturation region after the ESD event is detected, which can serve as a large equivalent resistance (~106 Ω) in the structure. The proposed power clamp circuit offers several advantages compared to the traditional circuit, such as having at least 70% area savings in the trigger circuit area (30% area savings in the whole circuit area), supporting a power supply ramp time as fast as 20 ns, dissipating the ESD energy more cleanly with little residual charge, and recovering faster from false triggers. The rail clamp circuit also offers robust performance in an industry-standard PVT (process, voltage, and temperature) space and has been verified by the simulation results. Showing good performance of human body model (HBM) endurance and high immunity to false trigger, the proposed power clamp circuit has great potential for application in ESD protection.

Study of Strained-SiGe Channel P-MOSFET Using Silvaco TCAD: Impact of Channel Thickness

Compressively strained SiGe is an interesting channel material for sub 45 nm p-MOSFETs because of its superior hole mobility (up to 10x over bulk Si channels) and compatibility with current Si manufacturing technologies. In this work, the impact of heterostructure composition and SiGe channel thickness on the electrical characteristics of p-MOSFET are studied. Using strained Si0.8Ge0.2 p-MOSFET, the thickness was altered to a few thicknesses of 3 nm, 5 nm, 7 nm, and 9 nm respectively. The optimal thickness was then used for Ge compositions (x = 0.2). The project was realized utilizing computer-aided Silvaco TCAD tools, with ATHENA tools creating the p-MOSFET structure and ATLAS tools doing the device simulation. The strained-Si1-xGex p-MOSFET and the Si p-MOSFET were compared in terms of their performances. The ID-VG and ID-VD characteristics, as well as the threshold voltage, VTH extraction, were the focus of the device simulation. The 7 nm thickness strained-Si0.8Ge0.2 p-MOSFET exhibited lower VTH than other SiGe thicknesses and the Si p-MOSFET which is VTH = 0.074 V. The lower threshold voltage of the strained-Si0.8Ge0.2 with 7 nm thickness indicating that the strained-Si1-xGex contributed to the decreased power consumption. In addition, the extracted IDsat for the strained-Si0.8Ge0.2 p-MOSFET with 7nm thickness provided higher IDsat compared to conventional Si p-MOSFET and other SiGe thicknesses devices. As compared to Si p-MOSFETs, the output characteristics of the strained-Si1-xGex demonstrated a drain current improvement by a factor of 1.01.

Field Effect Transistor with Nanoporous Gold Electrode.

Nanoporous gold (NPG) has excellent catalytic activity and has been used in the recent literature on this issue as a sensor in various electrochemical and bioelectrochemical reactions. This paper reports on a new type of metal-oxide-semiconductor field-effect transistor (MOSFET) that utilizes NPG as a gate electrode. Both n-channel and p-channel MOSFETs with NPG gate electrodes have been fabricated. The MOSFETs can be used as sensors and the results of two experiments are reported: the detection of glucose and the detection of carbon monoxide. A detailed comparison of the performance of the new MOSFET to that of the older generation of MOSFETs fitted with zinc oxide gate electrodes is given.

A 300 MHz MOS-only memristor emulator

MOS-only memristor emulators that work solely on the intrinsic capacitors of the transistors can have a high frequency operation feature and a low occupied chip area. This paper presents a memristor emulator consisting of two MOSFETs (i.e., M0 and M1) without any external elements and power supplies except for grounded M1’s source and body. When M0 and M1 are p-channel/n-channel MOSFETs, the proposed memristor emulator is named PMME/NMME. The post-simulation i−v curves of PMME/NMME exhibit pinched hysteresis loop shapes before the frequency of their sine inputs increases to 300 MHz. The occupied layout area of PMME/NMME is 1.8 * 2.57 μm2 in the Cadence design environment with 65 nm CMOS process. Furthermore, four stateful logic circuits based on PMMEs and NMMEs are presented. The feasibility of the proposed memristor emulator is verified with discrete p-channel MOSFETs of CD4007.

Influence of ionizing radiation on the parameters of p-channel MOS transistors

The results of experimental studies of the influence of gamma radiation Co60 on the basic parameters of silicon epitaxial-planar p-channel MOSFET transistors under different electrical modes are presented. Transistors were manufactured according to radiation-resistant DMOS technology with design standards of 1.4 μm. As a result of transistor studies, it was established that the values of all basic parameters after the radiation dose D = 106 rads (SiO2) in active electrical irradiation modes remained within the limits of the performance criteria; the parameter, most sensitive to influence of a dose of irradiation by gamma-quanta is the threshold voltage; in the passive electrical irradiation mode the transistor’s radiations resistance in all parameters corresponds to a dose of 2,8·106 rads (SiO2). A sufficiently high radiation resistance of the studied p-channel MOSFETs makes it possible to recommend them for use in aviation and space equipment. The different degrees of radiation degradation of the studied parameters during irradiation are due to their dependence either on the effects of ionization in the layers of sub-gate and insulating dielectrics, or structural damage in the bulk silicon of the transistor active regions. The high radiation resistance of the studied p-channel MOSFETs allows recommending them for use in aviation and space equipment.

Gate Oxide Instability of 4H-SiC p-Channel MOSFET Induced by AC Stress at 200 °C

The gate oxide instability of 4H-SiC pMOS induced by ac stress was experimentally investigated at 200 °C for the first time. The threshold voltage drift ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta {V}_{\text {th}}$ </tex-math></inline-formula> ) of pMOS under different stress conditions was experimentally measured. The results show that high-frequency ac stress could cause the additional <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta {V}_{\text {th}}$ </tex-math></inline-formula> . Furthermore, it was found first that high-frequency ac stress will cause the gate oxide breakdown at 200 °C. However, no gate oxide breakdown was found at 27 °C. By investigating the effects of ac stress conditions on the gate oxide breakdown, it is demonstrated that the captured electrons in interface states at low-level voltage (inversion) play an important role in the gate oxide breakdown.

Nitrogen Annealing As a Sustainable Method for Interface Trap Passivation in 4H-SiC Mosfets

Silicon Carbide (4H-SiC) has emerged as a leading wide band gap semiconductor for high-power, high-temperature applications1. 4H-SiC metal-oxide semiconductor-field-effect transistors (MOSFETs) have lower power dissipation compared to silicon, allowing for low-noise and high-efficiency all-electric vehicle drives, fast-charging stations, solar inverters, and more. While these devices provide substantial advancements for next-generation energy efficient power systems, 4H-SiC may also offer additional functionality in the form of integrated circuits (ICs) at high temperatures (>300 °C). Because of its high noise immunity and low static power consumption, lateral complementary-metal-oxide-semiconductor (CMOS) IC technology in 4H-SiC is desirable for large-scale integration2. This technology necessitates the use of both n- and p-channel MOSFETs that can operate at high temperatures.Despite the advances of 4H-SiC MOSFETs, the high density of interface states (Dit) at the 4H-SiC/SiO2 interface prevents reaching full potential resulting in high channel resistance and low mobility. Alternatives to nitric oxide (NO) annealing, the most common method adopted to reduce Dit in 4H-SiC3,4, are actively sought due to its toxicity and relatively expensive cost. Annealing in pure nitrogen (N2)5,6 at high temperatures (1400 °C-1600 °C) has been recently demonstrated promising results for 4H-SiC MOSFET processing. In this work, we report Dit measurements consistent with [6] and attempt to correlate the nitrogen areal densities of the near interfacial regions with the Dit for high temperature N2 annealing processes compared to NO. In our study, metal oxide semiconductor capacitors were fabricated on p- and n-type 4H-SiC epitaxial layers. Gate oxides were thermally grown at 1150 °C for 10 h in dry O2 resulting in a ~ 60 nm thick oxide layer. Selected samples are then annealed in flowing N2 at high temperatures (1400 °C, 1 h; 1450 °C, 1 h; and 1500 °C, 30 minutes or 1 h) or NO (1175 °C, 2 h). X-ray photoelectron spectroscopy (XPS), carried out after etching the oxide, indicates that the amount of nitrogen at the interface due to high temperature N2 annealing is ~ 4 × higher than NO annealed devices. Simultaneous high frequency (100 kHz)- low frequency CV was performed to extract interface trap densities (Dit) for each process and compared at room temperature (27 °C) with reference 1175 °C, 2 h NO annealed samples. The comparison reveals that, N2 annealing at 1500 °C for 30 minutes with a flow rate of 3 LPM results in Dit values comparable to NO annealing across the bandgap. Moreover, nitrogen annealing is more effective in reducing Dit near the valence band than NO annealing, while the opposite is true close to the conduction band-edge, consistent with previous reports [6] and observed in atomistic models of these interfaces using the density functional theory7. Nitrogen annealing also decreases the positive fixed charges at the interface of p-type 4H-SiC and SiO2, as evidenced from the flat band voltage comparison. The oxide breakdown voltage for the devices made with 1500 °C N2 annealing was similar to that of NO annealed devices. XPS analysis of the N2 annealed devices, their behavior under high temperature and bias, and their potential to substitute NO will be further discussed.The authors gratefully acknowledge the support from the National Renewable Energy Laboratory/ US Department of Energy sub-contract NREL-AHL-9-92362-01.

Study of Carrier Mobilities in 4H-SiC MOSFETS Using Hall Analysis.

The channel conduction in 4H-SiC metal–oxide–semiconductor field effect transistors (MOSFETs) are highly impacted by charge trapping and scattering at the interface. Even though nitridation reduces the interface trap density, scattering still plays a crucial role in increasing the channel resistance in these transistors. In this work, the dominant scattering mechanisms are distinguished for inversion layer electrons and holes using temperature and body-bias-dependent Hall measurements on nitrided lateral 4H-SiC MOSFETs. The effect of the transverse electric field () on carrier mobility is analyzed under strong inversion condition where surface roughness scattering becomes prevalent. Power law dependencies of the electron and hole Hall mobility for surface roughness scattering are determined to be and , respectively, analogous to those of silicon MOSFETs. Moreover, for n-channel MOSFETs, the effect of phonon scattering is observed at zero body bias, whereas in p-channel MOSFETs, it is observed only under negative body biases. Along with the identification of regimes governed by different scattering mechanisms, these results highlight the importance of the selection of substrate doping and of in controlling the value of channel mobility in 4H-SiC MOSFETs.