Oxide Trap Research Articles

Analysis of cell characteristics using back oxide trap charge effect in various channel structures of 3D-NAND flash

Abstract This study investigates how trap charges in the back oxide layer affect the memory performance of 3D NAND flash memory. We used TCAD to simulate the effect on cell reliability, focusing on retention and interference characteristics, based on changes in current paths and program speed as initial cell characteristics. Additionally, we applied these findings to various channel structures — planar, concave, and convex — that can occur in 3D NAND. Our results indicate that the optimal trap charge for enhancing cell performance lies between -10¹¹ and -10¹⁰ /cm³ and should not exceed -1011 /cm3. Through this research, we can expect the potential for effectively inserting trap charges in actual manufacturing processes to improve the performance characteristics of 3D NAND cells.

Gate Oxide Reliability in Silicon Carbide Planar and Trench Metal-Oxide-Semiconductor Field-Effect Transistors Under Positive and Negative Electric Field Stress

This work investigates the gate oxide reliability of commercial 1.2 kV silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) with planar and trench gate structures. The performance of threshold voltage (Vth) and gate leakage current (Igss) in SiC MOSFETs is evaluated under positive and negative gate voltage stress. The oxide lifetimes of SiC planar and trench MOSFETs at 150 °C are measured using constant voltage Time-Dependent Dielectric Breakdown (TDDB) testing. From the test results, it is found that electron trapping and hole trapping in SiO2 caused by oxide electric field (Eox) stress affect the Vth of SiC MOSFETs. The saturation and turnaround behavior of the Vth shift during positive and negative gate voltage stresses indicates that the influence of charge trapping in the gate oxide varies with stress time. The Igss under positive and negative gate voltages depends on the tunneling barrier height for electrons and holes, respectively, which can be calculated using the Fowler–Nordheim (FN) tunneling mechanism. Moreover, the presence of near-interface traps (NITs) affects the barrier height for holes under negative gate voltages. The behavior of Vth shift and Igss under high-temperature gate bias reflects the charge trapping occurring in different regions of the gate oxide. In addition, compared to SiC planar MOSFETs, SiC trench MOSFETs with thicker gate oxide tend to exhibit higher lifetimes in TDDB tests.

Electrochemical Oxidative Degradation and Trapping of the Mefenamic Acid Drug as a Redox-Active Hydroxy Metabolite on a Carbon Black Surface: Mediated Oxidation and Sensing of Thiol Biomarker

Electrochemical Oxidative Degradation and Trapping of the Mefenamic Acid Drug as a Redox-Active Hydroxy Metabolite on a Carbon Black Surface: Mediated Oxidation and Sensing of Thiol Biomarker

Positive Bias Temperature Instability in SiC-Based Power MOSFETs.

This paper investigates the threshold voltage shift (ΔVTH) induced by positive bias temperature instability (PBTI) in silicon carbide (SiC) power MOSFETs. By analyzing ΔVTH under various gate stress voltages (VGstress) at 150 °C, distinct mechanisms are revealed: (i) trapping in the interface and/or border pre-existing defects and (ii) the creation of oxide defects and/or trapping in spatially deeper oxide states with an activation energy of ~80 meV. Notably, the adoption of different characterization methods highlights the distinct roles of these mechanisms. Moreover, the study demonstrates consistent behavior in permanent ΔVTH degradation across VGstress levels using a power law model. Overall, these findings deepen the understanding of PBTI in SiC MOSFETs, providing insights for reliability optimization.

Origin and Recovery of Negative VTH Shift on 4H–SiC MOS Capacitors: An Analysis Based on Inverse Laplace Transform and Temperature-Dependent Measurements

SiC power MOSFETs are reported to suffer from both positive and negative threshold voltage shifts. Positive shift is well understood in the literature and attributed to electron trapping in near interface oxide traps (NIOTs). Negative shift is explained by hole generation and trapping in the oxide via impact ionization favored by the strong oxide field. However, studies on negative shift are still ongoing, and the origin and nature of the process are not fully understood. This study advances the comprehension of negative threshold voltage shift by investigating MOS capacitors subject to positive bias stress.We demonstrate that: a) a significant negative threshold shift is observed when the electric field is greater than 7.5 MV/cm; b) the detected shift is not recoverable at zero bias. Recovery can be obtained only by applying a positive gate voltage indicating a field-driven detrapping process. c) Trap-state mapping measurements were carried out to extract the activation energy of the detrapping processes, and a weak thermal activation was observed.Results collected within this paper indicate that holes are trapped at deep centers, and thermal detrapping is not possible. Hole release is only possible when a high field is applied to the insulator, possibly due to the recombination between leaking electrons and trapped holes.

Enantioselective domino alkyl arylation of vinyl phosphonates by combining photoredox and nickel catalysis

A nickel/photoredox mediated asymmetric domino alkyl arylation of vinyl phosphonates to generate a diverse array of enantioenriched α-aryl phosphonates is disclosed. This asymmetric three-component difunctionalization couples aryl halides and alkyl bromides with vinyl phosphonates, exhibiting excellent chemo- and regioselectivity under mild reaction conditions. The method avoids the need for pre-formed organometallics and phosphorus halides. Mechanistic and DFT studies suggest that photoexcited [4CzIPN]* oxidizes diethyl 1,4-dihydro-2,6-dimethyl-3,5-pyridinedicarboxylate (HEH) to generate the [4CzIPN]•–, which then reduces the alkyl bromide to form alkyl radicals that undergo Giese addition to the vinyl phosphonate. At the same time, Ni0 oxidatively adds the aryl bromide followed by enantiodetermining oxidative radical trapping of the phosphonate-based radical by the tetrahedral NiII center followed by reductive elimination. Independent gradient model based on Hirshfeld partition (IGMH) analysis suggests that the orientation of the phosphonate group (P=O…π interaction) is expected to play an essential role in controlling the enantioselectivity.

A Comparative Study on the Degradation Behaviors of Ferroelectric Gate GaN HEMT with PZT and PZT/Al2O3 Gate Stacks.

In this paper, the degradation behaviors of the ferroelectric gate Gallium nitride (GaN) high electron mobility transistor (HEMT) under positive gate bias stress are discussed. Devices with a gate dielectric that consists of pure Pb(Zr,Ti)O3 (PZT) and a composite PZT/Al2O3 bilayer are studied. Two different mechanisms, charge trapping and generation of traps, both contribute to the degradation. We have observed positive threshold voltage shift in both kinds of devices under positive gate bias stress. In the devices with a PZT gate oxide, we have found the degradation is owing to electron trapping in pre-existing oxide traps. However, the degradation is caused by electron trapping in pre-existing oxide traps and the generation of traps for the devices with a composite PZT/Al2O3 gate oxide. Owing to the large difference in dielectric constants between PZT and Al2O3, the strong electric field in the Al2O3 interlayer makes PZT/Al2O3 GaN HEMT easier to degrade. In addition, the ferroelectricity in PZT enhances the electric field in Al2O3 interlayer and leads to more severe degradation. According to this study, it is worth noting that the reliability problem of the ferroelectric gate GaN HEMT may be more severe than the conventional metal-insulator-semiconductor HEMT (MIS-HEMT).

Electrical stress reliability of graphene field effect transistor under different bias voltages

In this paper, graphene field effect transistors (GFETs) with the top-gate structure are taken as the research object. The electrical stress reliabilities are studied under different bias voltage conditions. The electrical pressure conditions are gate electrical stress (<i>V</i><sub>G</sub> = –10 V, <i>V</i><sub>D</sub> = 0 V, and <i>V</i><sub>S</sub> = 0 V), drain electric stress (<i>V</i><sub>D</sub> = –10 V, <i>V</i><sub>G</sub> = 0 V, and <i>V</i><sub>S</sub> = 0 V), and electrical stresses applied simultaneously by gate voltage and drain voltage (<i>V</i><sub>G</sub> = –10 V, <i>V</i><sub>D</sub> = –10 V, <i>V</i><sub>S</sub> = 0 V). Using a semiconductor parameter analyzer, the transfer characteristic curves of GFETs before and after electrical stress are obtained. At the same time, the carrier migration and the Dirac voltage <i>V</i><sub>Dirac</sub> degradation are extracted from the transfer characteristic curves. The test results show that under different electrical pressures, the carrier mobility of GFETs degrades continuously with the increase of electric stress time. Different electrical pressure conditions have varying effects on the drift direction and degradation of <i>V</i><sub>Dirac</sub>: gate electrical stress and drain electrical stress cause <i>V</i><sub>Dirac</sub> drift of the device in opposite directions, and the gate electrical stress is greater than the electrical stress applied by both gate voltage and drain voltage, leading to <i>V</i><sub>Dirac</sub> degradation of GFETs. An analysis of the causes indicates that different electrical stresses produce different electric field directions in the device, which can affect the carrier concentration and movement direction. Electrons and holes in the channel are induced and tunnel into the oxide layer, and they are captured by trap charges in the oxide layer and at the interface between graphene and oxide, forming oxide trap charges and interface trap charges. This is the main reason for reducing carrier mobility of GFET. Different electric field directions under different electric stresses produce positively charged trap charges and negatively charged trap charges. The difference in the type of trap charge banding is the main reason for the different directions of <i>V</i><sub>Dirac</sub> drift in GFETs. When both trap charges coexist, they have a canceling effect on the <i>V</i><sub>Dirac </sub>drift of the GFETs. Finally, by combining TCAD simulation the simulation model of the influence of electrical stress induced trap charge on the <i>V</i><sub>Dirac</sub> generation of GFET is further revealed. The result demonstrates that the differences in the type of trap charge banding have different degradation effects on the <i>V</i><sub>Dirac</sub> of GFETs. The related research provides data and theoretical support for putting graphene devices into practical application.

Methods to monitor mitochondrial disulfide bonds.

Mitochondria contain numerous proteins that utilize the chemistry of cysteine residues, which can be reversibly oxidized. These proteins are involved in mitochondrial biogenesis, protection against oxidative stress, metabolism, energy transduction to adenosine triphosphate, signaling and cell death among other functions. Many proteins located in the mitochondrial intermembrane space are imported by the mitochondrial import and assembly pathway the activity of which is based on the reversible oxidation of cysteine residues and oxidative trapping of substrates. Oxidative modifications of cysteine residues are particularly difficult to study because of their labile character. Here we present techniques that allow for monitoring the oxidative state of mitochondrial proteins as well as to investigate the mitochondrial import and assembly pathway. This chapter conveys basic concepts on sample preparation and techniques to monitor the redox state of cysteine residues in mitochondrial proteins as well as the strategies to study mitochondrial import and assembly pathway.

Total X-ray dose effect on graphene field effect transistor

In this paper, the total dose effects of graphene field-effect transistors (GFETs) with different structures and sizes are studied. The irradiation experiments are carried out by using the 10-keV X-ray irradiation platform with a dose rate of 200 rad(Si)/s. Positive gate bias (<i>V</i><sub>G</sub> = +1 V, <i>V</i><sub>D<i> </i></sub>= <i>V</i><sub>S<i> </i></sub>= 0 V) is used during irradiation. Using a semiconductor parameter analyzer, the transfer characteristic curves of top-gate GFET and back-gate GFET are obtained before and after irradiation. At the same time, the degradation condition of the dirac voltage <i>V</i><sub>Dirac</sub> and the carrier mobility <i>μ</i> are extracted from the transfer characteristic curve. The experimental results demonstrate that <i>V</i><sub>Dirac</sub> and carrier mobility <i>μ</i> degrade with dose increasing. The depletion of <i>V</i><sub>Dirac</sub> and carrier mobility <i>μ</i> are caused by the oxide trap charge generated in the gate oxygen layer during X-ray irradiation. Compared with the back-gate GFETs, the top-gate GFETs show more severely degrade <i>V</i><sub>Dirac</sub> and carrier mobility, therefore top-gate GFET is more sensitive to X-ray radiation at the same cumulative dose than back-gate GFET. The analysis shows that the degradation of top-gate GFET is mainly caused by the oxide trap charge. And in contrast to top-gate GFET, oxygen adsorption contributes to the irradiation process of back-gate GFET, which somewhat mitigates the effect of radiation damage. Furthermore, a comparison of electrical property deterioration of GFETs of varying sizes between the pre-irradiation and the post-irradiation is made. The back-gate GFET, which has a size of 50 μm×50 μm, and the top-gate GFET, which has a size of 200 μm×200 μm, are damaged most seriously. In the case of the top-gate GFET, the larger the radiation area, the more the generated oxide trap charges are and the more serious the damage. In contrast, the back-gate GFET has a larger oxygen adsorption area during irradiation and a more noticeable oxygen adsorption effect, which partially offsets the damage produced by irradiation. Finally, the oxide trap charge mechanism is simulated by using TCAD simulation tool. The TCAD simulation reveals that the trap charge at the interface between Al<sub>2</sub>O<sub>3</sub> and graphene is mainly responsible for the degradation of top-gate GFET property, significantly affecting the investigation of the radiation effect and radiation reinforcement of GFETs.

Study of the Influence of Different Gate Oxide Traps on Threshold Voltage Drift of SiC MOSFET based on Transient Current

Study of the Influence of Different Gate Oxide Traps on Threshold Voltage Drift of SiC MOSFET based on Transient Current

"Soggy-Sand" Chemistry for High-Voltage Aqueous Zinc-Ion Batteries.

The narrow electrochemical stability window, deleterious side reactions, and zinc dendrites prevent the use of aqueous zinc-ion batteries. Here, aqueous "soggy-sand" electrolytes (synergistic electrolyte-insulator dispersions) are developed for achieving high-voltage Zn-ion batteries. How these electrolytes bring a unique combination of benefits, synergizing the advantages of solid and liquid electrolytes is revealed. The oxide additions adsorb water molecules and trap anions, causing a network of space charge layers with increased Zn2+ transference number and reduced interfacial resistance. They beneficially modify the hydrogen bond network and solvation structures, thereby influencing the mechanical and electrochemical properties, and causing the Mn2+ in the solution to be oxidized. As a result, the best performing Al2 O3 -based "soggy-sand" electrolyte exhibits a long lifeof 2500 h in Zn||Zn cells. Furthermore, it increases the charging cut-off voltage for Zn/MnO2 cells to 2V, achieving higher specific capacities. Even with amass loading of 10 mgMnO2 cm-2 , it yields a promising specific capacity of 189 mAh g-1 at 1 A g-1 after 500 cycles. The concept of "soggy-sand" chemistry provides a new approach to design powerful and universal electrolytes for aqueous batteries.

Surface Passivation by Quantum Exclusion: On the Quantum Efficiency and Stability of Delta-Doped CCDs and CMOS Image Sensors in Space.

Radiation-induced damage and instabilities in back-illuminated silicon detectors have proved to be challenging in multiple NASA and commercial applications. In this paper, we develop a model of detector quantum efficiency (QE) as a function of Si-SiO2 interface and oxide trap densities to analyze the performance of silicon detectors and explore the requirements for stable, radiation-hardened surface passivation. By analyzing QE data acquired before, during, and after, exposure to damaging UV radiation, we explore the physical and chemical mechanisms underlying UV-induced surface damage, variable surface charge, QE, and stability in ion-implanted and delta-doped detectors. Delta-doped CCD and CMOS image sensors are shown to be uniquely hardened against surface damage caused by ionizing radiation, enabling the stability and photometric accuracy required by NASA for exoplanet science and time domain astronomy.

Study on annealing effect of bipolar transistors at different temperatures after total dose irradiation

The article investigates the annealing process of bipolar transistors after total dose irradiation, using the GLPNP transistor as the research object. After total dose irradiation, room temperature and high temperature annealing tests were carried out. Gummel curve, GS curve and SS curve of bipolar transistor are obtained by I/V scanning, gate scanning and sub-threshold scanning. The evolution behavior of radiation-induced oxide trap charges and interface state damage defects during annealing of bipolar transistors at different temperatures was quantitatively analyzed by different microscopic defect characterization methods. Generally speaking, this study is of great significance to better understand the recovery mechanism of electrical properties of bipolar transistors during annealing after total dose irradiation, and can provide reference for the design, application and radiation-hard of transistors.

Interface and oxide trap states of SiO2/GaN metal–oxide–semiconductor capacitors and their effects on electrical properties evaluated by deep level transient spectroscopy

The relationship between the electrical properties and the carrier trap properties of the SiO2/GaN metal–oxide–semiconductor (MOS) capacitors was investigated using electrical measurements and deep level transient spectroscopy (DLTS). The capacitance–voltage (C–V) measurement showed that the frequency dispersion of the C–V curves became smaller after an 800 °C annealing in O2 ambient. DLTS revealed that before the annealing, the interface trap states, in a broad energy range above the midgap of GaN, were detected with the higher interface state density at around 0.3 and 0.9 eV below the conduction band minimum (EC) of GaN. Moreover, the oxide trap states were formed at around 0.1 eV below the EC of GaN, plausibly indicating a slow electron trap with a tunneling process. Although both trap states affect the electrical reliability and insulating property of the SiO2/GaN MOS capacitors, they were found to drastically decrease after the annealing, leading to the improvement of the electrical properties.

Ultrathin four-quadrant silicon photodiodes for beam position and monitor applications: Characterization and radiation effects

Ultrathin semiconductor photodiodes are of interest for beam position and monitoring in X-ray synchrotron beamlines and particle therapy medical applications. In this work, single and four-quadrant diodes have been fabricated on ultrathin Si films with thicknesses of 10 μm, 5 μm and 3 μm from silicon on insulator (SOI) substrates. Physical and electrical characterization of the devices has been carried out. Good functional electrical characteristics have been obtained for the devices fabricated on the different silicon thicknesses. The impact of electron, neutron and proton irradiations on the electrical characteristics has been studied for the 10 μm-thick devices. In spite of the observed diode leakage current increase and positive charge trapping in interquadrant isolation oxide, functional operation as radiation detector is verified upon illumination with a pulsed laser beam transient current technique.

Imaging Fermi-level hysteresis in nanoscale bubbles of few-layer MoS2

The electrical stability and reliability of two-dimensional (2D) crystal-based devices are mainly determined by charge traps in the device defects. Although nanobubble structures as defect sources in 2D materials strongly affect the device performance, the local charge-trapping behaviors in nanobubbles are poorly understood. Here, we report a Fermi-level hysteresis imaging strategy using Kelvin probe force microscopy to study the origins of charge trapping in nanobubbles of MoS2 on SiO2. We observe that the Fermi-level hysteresis is larger in nanobubbles than in flat regions and increases with the height in a nanobubble, in agreement with our oxide trap band model. We also perform the local transfer curve measurements on the nanobubble structures of MoS2 on SiO2, which exhibit enhanced current-hysteresis windows and reliable programming/erasing operations. Our results provide fundamental knowledge on the local charge-trapping mechanism in nanobubbles, and the capability to directly image hysteresis can be powerful tool for the development of 2D material-based memory devices.

On the Fluctuation–Dissipation of the Oxide Trapped Charge in a MOSFET Operated Down to Deep Cryogenic Temperatures

In this paper, an analysis of the oxide trapped charge noise in a MOSFET operated down to deep cryogenic temperatures is proposed. To this end, a revisited derivation of the interface trap conductance [Formula: see text] and oxide trapped charge noise [Formula: see text] at the SiO2/Si MOS interface is conducted under very low temperature condition, where Fermi–Dirac statistics applies. A new relation between the oxide trapped charge noise [Formula: see text] and the interface trap conductance [Formula: see text] is established, showing the inadequacy of the Nyquist relation at very low temperature. Finally, a new formula for the oxide trapped charge 1/f noise, going beyond the classical Boltzmann expression, is developed in terms of oxide trap density and effective temperature accounting for degenerate statistics.

The effects of stress on interfacial properties and flatband voltage instability of 4H-SiC MOS structures

Strain engineering technology is expected to improve the poor SiO2/4H-SiC interface. The paper investigated the effects of curvature induced stress on interfacial properties and flatband voltage instability of 4H-SiC MOS capacitors. The slightest stress sample demonstrated the best calculation results and the superior properties in terms of interface state density, FN barrier, and effective near-interface traps density, which means the “stress free” or small compressive stress oxide film might be helpful for the realization of high performance of 4H-SiC MOS structures. The behavior of Vfb instability under various bias temperature stress and voltage stress at different durations was also studied. The more significant compressive/tensile stress led to worse reliability at high temperatures, which was caused by the combined effect of mobile ions and charge trapping. The trapping and de-trapping time constants of interface and oxide traps were calculated to clarify the relationship between temperature and Vfb instability. Moreover, the results of the measured Raman shift of the SiC bond implied that stresses tend to be unanimous in the subsequent processes while the influences on interfacial properties and Vfb instability still exist. These results are considered necessary for strain engineering technology, which is expected to lower the interface states density in SiO2/4H-SiC interface and reach the optimal performances of 4H–SiC.

Analysis of trap distribution and NBTI degradation in Al2O3/SiO2 dielectric stack

In this work, p-substrate MOS capacitors with plasma-enhanced atomic-layer-deposited Al2O3/ thermally-grown SiO2 dielectric stack (with a target equivalent oxide thickness of 4.2 nm) are investigated by means of the conductance method in a temperature range from 25 °C to 150 °C. The trap state density and energy level distribution in the silicon bandgap are extracted over the bandgap. Furthermore, negative bias temperature instability is analyzed by two-point capacitance–voltage characterization to evaluate the electrical stability and dielectric reliability of the Al2O3/SiO2 stack. The contributions from interface and oxide trap generations are detailed. Our results indicate that plasma-enhanced atomic layer deposited Al2O3 on thermal SiO2 stack features low interface trap density, and comparable dielectric reliability to conventional SiO2, SiOxNy, and high-k dielectric stacks.