Oxide Trap Research Articles

Trap properties of high-k/metal gate pMOSFETs with aluminum ion implantation by random telegraph noise and 1/f noise measurements

In this study, the impact of aluminum ion implantation on 1/f noise characteristics and random telegraph noise (RTN) in high-k/metal gate (HK/MG) p-type metal–oxide–semiconductor field-effect transistors (pMOSFETs) was investigated. Aluminum ion implantation (Al I/I) into TiN/HfO2/SiO2 was implemented to tune an effective work function (EWF) in pMOSFETs without EOT increase complicated processes. RTN and 1/f results revealed that regardless of the implanted dose, HK/MG devices with Al I/I exhibit lower slow oxide trap densities than the control devices, which are responsible for the reduced trap position (xt) from the SiO2 interfacial layer (IL)/Si interface. For the HK/MG devices with different implanted doses, no significant differences in trap properties were observed.

Investigation of interface, shallow and deep oxide traps under NBTI stress using charge pumping technique

By extracting and eliminating the geometric component from the charge pumping current (ICP) in on-the-fly oxide trap method (OTFOT), we have been able to demonstrate that both interface (ΔNit) and deep hole oxide traps (ΔNotD) induced by the negative bias temperature instability (NBTI) are principally located in the lightly doped drain region (LDD region) and they do not show any noticeable increase with stress time in the effective channel region. However, we have shown that the shallow hole oxide traps (ΔNotS) induced by NBTI are created in the whole of the channel.

Assessment of the Impact of Inelastic Tunneling on the Frequency-Depth Conversion from Low-Frequency Noise Spectra

An expression is derived for the conversion of the frequency axis of a low-frequency noise spectrum into a depth axis, based on the capture and emission time constant of a random telegraph signal. By connecting the corner frequency of the corresponding Lorentzian spectrum to the measured trapping time constant, the effect of multiphonon relaxation upon tunneling into an oxide trap can be included in a natural way. With this expression, one can derive in a straightforward manner some important trends with respect to the impact of several trap and material parameters on the tunneling depth, both for SiO2 and high- κ gate dielectrics.

Low-Frequency-Noise-Based Oxide Trap Profiling in Replacement High-κ/Metal-Gate pMOSFETs

Low-frequency noise is studied in planar high-κ/metal-gate (HK/MG) last pMOSFETs in order to assess the impact of a post-HfO2 deposition SF6-plasma or heat-treatment on the oxide trap density and profile. It is shown that the gate oxide quality is improved by lowering the active border trap density for both approaches. At the same time, a detailed analysis of the frequency exponent of the flicker noise spectra reveals that in the case of the SF6-plasma, the reduction of the active border trap density occurs more efficiently deeper in the high-κ layer, while the opposite holds for the annealed devices, i.e., a lower trap density is found closer to the interfacial SiO2 layer.

Investigation of Low‐Frequency Noise Characterization of 28‐nm High‐k pMOSFET with Embedded SiGe Source/Drain

We have studied the low‐frequency noise characterizations in 28‐nm high‐k (HK) pMOSFET with embedded SiGe source/drain (S/D) through 1/f noise and random telegraph noise measurements simultaneously. It is found that uniaxial compressive strain really existed in HK pMOSFET with embedded SiGe S/D. The compressive strain induced the decrease in the tunneling attenuation length reflecting in the oxide trap depth from Si/SiO2 interface to the HK layer, so that the oxide traps at a distance from insulator/semiconductor interface cannot capture carrier in the channel. Consequently, lower 1/f noise level in HK pMOSFET with embedded SiGe S/D is observed, thanks to the less carrier fluctuations from trapping/detrapping behaviors. This result represents an intrinsic benefit of HK pMOSFET using embedded SiGe S/D in low‐frequency noise characteristics.

Cyclic Plasma Treatment during ALD Hf1-xZrxO2 Deposition

Effect of slot plane antenna (SPA) Ar plasma on the reliability of intermediate plasma (DSDS) treated ALD Hf1-xZrxO2 samples with x = 0, 0.31, 0.8 were investigated. The metal oxide semiconductor capacitors (MOSCAP) were subjected to a constant field stress of 27.5 MV/cm in the gate injection mode and the stress-induced flatband voltage shifts and stress induced leakage currents were monitored. The dielectric film deposited without any intermediate step (As-Dep), having the same number of atomic layer deposition (ALD) cycles as DSDS samples was used as the control sample. It was observed that plasma exposure enhances the quality of high-κ film by reducing the number of intrinsic traps in the film and Zr addition further enhances the reliability. Breakdown characteristics also confirm this behavior. Electron affinity variation in HfO2 and ZrO2 and Zr variation seems to contribute to the improvement in DSDS Hf1-xZrxO2 (x = 0.8) by suppressing the oxide trap formation as observed in the Weibull characteristics. DSDS Hf1-xZrxO2 with x = 0.8, therefore, demonstrates a superior equivalent oxide thickness (EOT) downscaling ability and good reliability performance.

Total-Ionizing-Dose Radiation Effects in AlGaN/GaN HEMTs and MOS-HEMTs

<?Pub Dtl=""?> We have investigated the total ionizing dose (TID) radiation effects in AlGaN/GaN MOS-HEMTs as a function of dose and radiation bias, and compared them with conventional HEMTs. Under 10 keV X-ray irradiation, two distinct regimes of threshold voltage <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(V_{th})$</tex> </formula> shifts have been revealed: a rapid <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$V_{th}$</tex></formula> shift at low doses <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$[&lt; {3}{\rm krad (SiO}_{2})]$</tex></formula> for both HEMTs and MOS-HEMTs, and an additional <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V_{th}$</tex></formula> shift only found in MOS-HEMTs for doses up to at least 2 Mrad <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$({\rm SiO}_{2})$</tex></formula> . The rapid <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V_{th}$</tex> </formula> shift anneals quickly and is a strong function of layer material. We attribute this portion of the <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V_{th}$</tex> </formula> shift to hole trapping in the AlGaN barrier layer. The <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V_{th}$</tex></formula> shift at high doses found only in MOS-HEMTs is attributed to hole trapping in the gate oxide. By comparing MOSFETs with <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm HfO}_{2}$</tex></formula> and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm Al}_{2} {\rm O}_{3}$</tex></formula> gate dielectrics that are annealed during processing at various temperatures, we find that <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$500^{\circ}{\rm C}$</tex></formula> annealed <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm HfO}_{2}$</tex></formula> shows the most promising TID response.

Dependence on an oxide trap’s location of random telegraph noise (RTN) in GIDL current of n-MOSFET

We investigated the variation of random telegraph noise (RTN) in gate-induced drain leakage (GIDL) current by changing location of a trap inside the gate oxide of n type metal-oxide semiconductor field effect transistor (n-MOSFET). The dependence on drain to gate bias was then considered. This approach has been assessed with Technology Computer Aided Designed (TCAD) simulations.

Effects of Fin Width on Device Performance and Reliability of Double-Gate n-Type FinFETs

This paper investigates the impact of fin width ( W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fin</sub> s = 15, 20, and 25 nm) in a double-gate n-type FinFET on the performance and reliability of the device. Carrier conduction in the Si-fin body of FinFETs with various W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fin</sub> s is also studied. The experimental results show that the threshold voltage and drain current of n-type FinFETs increases and decreases, respectively, as W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fin</sub> is reduced. A thinner W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fin</sub> FinFET exhibits greater immunity to short channel effects. In addition, according to the analysis results of low-frequency noise, the thinnest W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fin</sub> FinFET possesses the largest bulk oxide trap density (N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BOT</sub> ) than that of a thicker W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fin</sub> FinFET. Moreover, the noise of the thinnest W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fin</sub> (15 nm) FinFET is largely dominated by the fluctuation of carrier number. In the hot-carrier injection (HCI) reliability test, the thinnest W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fin</sub> FinFET shows less performance degradation than those of the thicker ones. However, by removing the effect of the parasitic source/drain resistance, we believe that the volume inversion charged carriers flow through the entire thin Si-fin having a lower surface roughness and Coulomb scattering than those of thicker ones, which results in a higher carrier temperature and worsening of the reliability of the HCI.

Characterization of High-Current Stress-Induced Instability in Amorphous InGaZnO Thin-Film Transistors by Low-Frequency Noise Measurements

The instability of amorphous InGaZnO thin-film transistors is investigated under high drain current stress by applying bias voltages to both gate and drain electrodes. The instability involves positive threshold voltage shift, reduction of the ON-state current and recovery of the transfer characteristic toward the prestressed state when the stressed device is unbiased in dark at room temperature for an extended period. This instability behavior is investigated by low-frequency noise measurements before and after stress in the forward and reverse configurations. The overall results are consistent with the instability mechanism involving electron trapping in the existing donor-like gate oxide trap states near the source side.

On the Oxide Trap Density and Profiles of 1-nm EOT Metal-Gate Last CMOS Transistors Assessed by Low-Frequency Noise

The low-frequency noise behavior of replacement metal gate high- k/metal-gate MOSFETs with an equivalent oxide thickness of the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> bilayer in the range ~ 1 nm has been investigated. It will be shown that both the average trap density and its profile derived from the frequency exponent γ of the flicker noise spectra are mainly determined by the interfacial layer (IL) oxide processing, with a higher trap density corresponding with a thinner chemical oxide, compared with a ≤ 1-nm thermal SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> IL. The thickness of the HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layer and the metal gate fill has only a marginal impact on the noise power spectral density. It will also be shown that for the extraction of the trap density profiles from the 1/f <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">γ</sup> noise spectra accurate values for the tunneling effective mass and barrier height are required.

Zinc-oxide charge trapping memory cell with ultra-thin chromium-oxide trapping layer

A functional zinc-oxide based SONOS memory cell with ultra-thin chromium oxide trapping layer was fabricated. A 5 nm CrO2 layer is deposited between Atomic Layer Deposition (ALD) steps. A threshold voltage (Vt) shift of 2.6V was achieved with a 10V programming voltage. Also for a 2V Vt shift, the memory with CrO2 layer has a low programming voltage of 7.2V. Moreover, the deep trapping levels in CrO2 layer allows for additional scaling of the tunnel oxide due to an increase in the retention time. In addition, the structure was simulated using Physics Based TCAD. The results of the simulation fit very well with the experimental results providing an understanding of the charge trapping and tunneling physics.

Comparison of Bulk-Oxide Trap Models: Lumped Versus Distributed Circuit

Lumped- and distributed-circuit models for bulk-oxide traps are compared in terms of their fitting of p and n-type InGaAs MOS dispersion data. It is shown that the lumped-circuit model produces a distinct curvature in the capacitance versus log (frequency) plot-inconsistent with MOS data. Distributed-circuit model is able to fit both capacitance and conductance dispersions with a single, uniform oxide trap density, but the lumped-circuit model cannot. It is also shown that Hasegawa and Sawada's lumped-circuit model with an exponentially decaying distribution of border traps deviates even farther from the dispersion data.

Characterization of Oxide Traps Participating in Random Telegraph Noise Using Charging History Effects in Nano-Scaled Mosfets

not Available.

Low-Frequency-Noise-Based Oxide Trap Profiling in Replacement High-k/Metal-Gate Pmosfets

not Available.

Experimental and simulation study of in-cylinder strategies for regeneration of lean nitrogen oxide traps in a high-speed direct-injection diesel engine

The use of lean nitrogen oxide traps is an attractive solution for reducing the tailpipe emissions of nitrogen oxides in vehicles with diesel engines. During the operation, nitrogen oxides are stored on the surfaces of lean nitrogen oxide traps, and regeneration of lean nitrogen oxide traps is required for proper operation. In this paper, two in-cylinder combustion strategies for regeneration of lean nitrogen oxide traps were assessed for a high-speed direct-injection diesel engine. In particular, a delayed and extended main strategy and a premixed compression ignition strategy were studied through experiments and simulations. The experimental data were collected from a 1.5 l diesel engine to analyze its combustion, exhaust temperature, fuel consumption, and emission characteristics resulting from either the delayed and extended main strategy or the premixed compression ignition strategy. The results indicated that the premixed compression ignition strategy offered a better fuel economy and lower soot and nitrogen oxide emissions, while the delayed and extended main strategy offered a hotter exhaust temperature and higher production rates of reductant species. In addition, a one-dimensional numerical lean nitrogen oxide trap model was designed and validated to study the efficiency of the surface adsorbents on lean nitrogen oxide traps for each of these two strategies in terms of a reduction in the nitrogen oxide emissions. The simulation results revealed that both strategies can reach a lean nitrogen oxide trap efficiency rate of 100% when the exhaust gas recirculation rate was equal to 30% but that the lean nitrogen oxide trap efficiency rate drops when lower exhaust gas recirculation rates were applied. Overall, the results indicated that the premixed compression ignition strategy performed better than the delayed and extended main strategy in terms of the fuel economy and lower tailpipe emissions.

Effect of Bias Temperature Stress on the Anti-Reflection HfO2 Layer in Complementary Metal Oxide Semiconductor Image Sensors

The effects of various electrical characteristics of HfO2 in CMOS image sensors on bias-thermal stress instability were evaluated. In this work, the HfO2 dielectric layer was used as the anti-reflection layer of image sensors because it had negative charges and could electrically form a p+ layer on a silicon photodiode surface. After the HfO2 layer was stressed with electric field 0.5 MV/cm, 200 °C, and 10 min, there was severe electrical degradation such as +18.8 V flatband voltage shift. In order to investigate this degradation, the oxide trap charges and border trap charges of the HfO2 layer were measured and calculated. Based on these results, the interface trap density and minority carrier generation lifetime, which are directly related to the dark current in CMOS image sensors, were measured. The interface trap density degraded from 4.5×1011 to 1.0×1012 cm-1 eV-1 and the generation lifetime also degraded from 983 to 17 µs after stress application. This trap generated degradation model is suggested for CMOS image sensors. Therefore, pre-stabilization of bias-thermal stress should be implemented to use the HfO2 layer in modern CMOS image sensors.

The Effect of Trapped Charge on Silicon Nanowire Pseudo-MOSFETs

The effects of organic molecules grafted on top of silicon nanowires are modeled as the oxide trap charges (Qot) and interface trap charges (Qit). The device investigated here is a pseudo-MOSFET with a thick bottom oxide (200 nm) and only a thin native oxide (5 nm) on top. With Qot = -5.0 x 10(11) cm(-2) and the U-shaped distribution of interface trap density (Dit) as a function of trap energy (Et), the structures are reproduced through the conventional technology computer aided design (TCAD) simulation tool, and the channel is imaginarily divided into several sections (5 x 5 regions) to apply the localized traps. The electrical parameters are extracted from the each part to quantitatively compare their effectiveness. The local position of the grafted molecules, modeled by these charges, is shown to result in strong variations in the relative change in the threshold voltage and subthreshold swing. These variations are explained by the surface depletion and scattering near the edges of the etched device and the series resistance effect.

(Invited) Characterization of Oxide Traps Participating in Random Telegraph Noise Using Charging History Effects in Nano-Scaled MOSFETs

We propose a novel method for characterizing the oxide traps that participate in random telegraph noise (RTN) by using charging history effects on the traps. In this method, the variation in the frequency of the high/low drain current derived from RTN with the charging history is monitored instead of the time-scale parameters that are usually used. Moreover, we also propose a method to determine the number and charging conditions of the traps. These methods are particularly effective for characterizing individual oxide traps in multi-trap RTN.

Low-Frequency-Noise-Based Oxide Trap Profiling in Replacement High-k/Metal-Gate pMOSFETs

Low-frequency noise is studied in planar high-k-metal/gate (HKMG) last pMOSFETs in order to study the impact of a post-HfO2 deposition SF6-plasma or heat treatment on the oxide trap density and profile. It is shown that the gate oxide quality is improved by lowering the active border trap density for both approaches. At the same time, a detailed analysis of the frequency exponent of the flicker noise spectra reveals that in the case of the SF6-plasma, the reduction of the active border trap density occurs more efficiently deeper in the high-k layer, while the opposite holds for the annealed devices, i.e., a lower trap density is found closer to the interfacial SiO2 layer.