Oxide Semiconductor Thin-film Transistors Research Articles

Mobility and current boosting of In-Ga-Zn-O thin-film transistors with metal capping layer oxidation

This study investigates the effect of an oxidized Ta capping layer on the boosting of field-effect mobility (μ FE) of amorphous In-Ga-Zn-O (a-IGZO) Thin-film transistors (TFTs). The oxidation of Ta creates additional oxygen vacancies on the a–IGZO channel surface, leading to increased carrier density. We investigate the effect of increasing Ta coverage on threshold voltage (V th), on-state current, μ FE and gate bias stress stability of a-IGZO TFTs. A significant increase in μ FE of over 8 fold, from 16 cm2 Vs−1 to 140 cm2 Vs−1, was demonstrated with the Ta capping layer covering 90% of the channel surface. By partial leaving the a-IGZO uncovered at the contact region, a potential barrier region was created, maintaining the low off-state current and keeping the threshold voltage near 0 V, while the capped region operated as a carrier-boosted region, enhancing channel conduction. The results reported in this study present a novel methodology for realizing high-performance oxide semiconductor devices. The demonstrated approach holds promise for a wide range of next-generation device applications, offering new avenues for advancement in metal oxide semiconductor TFTs.

Deep-Submicron Channel Length Oxide Semiconductor Thin-Film Transistors Enabled by Self-Aligned Nanogap Lithography

Deep-Submicron Channel Length Oxide Semiconductor Thin-Film Transistors Enabled by Self-Aligned Nanogap Lithography

Light Effect on Amorphous Tin Oxide Thin‐Film Transistors

Amorphous tin oxide (a‐SnOx) is a potential transparent oxide semiconductor candidate for future large‐area electronic applications. The thin‐film transistor (TFT) mobilities reach ≈100 cm2 Vs−1, a mobility higher than other multiple cation‐based oxide semiconductor TFTs. Few optical properties have been reported so far and therefore both the effect of visible light and negative bias illumination stress (NBIS) on a‐SnOx TFT performances, known to dramatically impact oxide semiconductor‐based TFTs, have been investigated. The variation of density of states (DOS) due to NBIS by device simulation is analyzed, and a fourfold increase of the donor‐like states and a decrease in the band edge DOS from 2.3 to 2.0 × 1019 cm−3 eV−1 are showed. The evaluation of the effect of neutral, singly, and doubly ionized oxygen vacancies by density functional theory using 95 atoms reveals not only states in the gap of SnO2, but also variations in the electron density, and modifications in the crystal parameters compared to a structure without an oxygen vacancy. Material and device simulation analysis reveal that the oxygen vacancies have a dramatical impact on the DOS in the gap of SnO2 and can explain the NBIS phenomenon observed in a‐SnOx TFT.

Facile diffusion of sulfur and fluorine into a-IGTO thin films for high-performance and reliability of transparent amorphous oxide semiconductor thin-film transistors

Facile diffusion of sulfur and fluorine into a-IGTO thin films for high-performance and reliability of transparent amorphous oxide semiconductor thin-film transistors

High Reliability Tungsten-Doped Indium Zinc Oxide Thin Film Transistors for Display Applications

Recently, flat panel display technologies are based on amorphous silicon (a-Si), polycrystalline silicon (poly-Si) or amorphous oxide semiconductor (AOS) thin film transistors (TFTs) technology. In order to reach higher performance for ultra-high resolution display applications, the material selection for the channel layer is vital. AOS TFTs drawn lots of attention because of its advantages such as low leakage current, high driving current and high uniformity [1,3]. In this work, we presented a novel amorphous oxide semiconductor (AOS) material of gallium-free a-InWZnO thin film transistors (IWZO TFTs) which is very promising to be applied for ultra-high resolution display technology. Experiment In this work, we demonstrated the structure of a-IWZO TFTs processes. Figure 1 shows the schematic of the TFT cross-section. After growing a 550 nm thermal oxide layer as buffer layer, a 25-nm-thick of molybdenum was deposited by DC-sputter as the bottom gate electrode. A 10-nm-HfO2 was deposited by plasma-enhanced atomic layer deposition (PEALD) system as high-κ gate dielectric (GI). Then, post deposition annealing (PDA) was carried out to enhance the quality of the insulator layer. Next, an ultra-thin body a-IWZO was deposited by RF-sputter as channel layer. Finally, source and drain were defined by lift-off process and the gate contact via was etched by dry etching to finish the device fabrication. Result and Discussion Figure 1(b) shows the negative gate bias stress (NGBS) transfer curve (ID-VG) of a-IWZO TFTs with passivation layer. The experimental results have shown that passivation layer could keep the back channel of IWZO channel from exposing to oxygen and hydrogen from the atmosphere. Without the passivation layer, the back channel would contact moisture leading the diffused hydrogen atoms to fill oxygen vacancy sites and de-trap free carriers, causing the VTH shifts negatively. The ultra-thin a-IWZO TFTs with passivation layer exhibited a low subthreshold swing (S.S.) of 89.7 mV/dec, high on/off current ratio (ION/IOFF) of 2.1×107 and small threshold voltage shift (ΔVth) of -0.097 V during NGBS of -2MV/cm with 2000s. To sum up, the passivation layer could enhance the a-IWZO TFTs reliability. Reference [1] Kamiya, H. Hosono, NPG Asia Mater., vol. 2, pp. 15, 2010.[2] Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, nature, vol. 432, no. 7016, pp. 488-492, 2004.[3] Y. Kuo, C. M. Chang, I. H. Liu, and P. T. Liu, Scientific reports, vol. 9, no. 1, pp. 1-7, 2019. Figure 1

Compositional tailoring of indium-free GZO layers via plasma-enhanced atomic layer deposition for highly stable IGZO/GZO TFT

Oxide semiconductor-based thin-film transistors (TFTs) are promising candidates for display backplanes and memory device applications. To achieve high device performance and sustain the electrical properties under prolonged operation, it is important to overcome the mobility–stability trade-off in oxide TFTs. Here, we propose a bilayer-structured semiconductor stack formed by plasma-enhanced atomic layer deposition (PEALD), where an indium-free gallium zinc oxide (GZO) film is grown on top of indium gallium zinc oxide (IGZO), to be implemented in top gate devices. Applying a GZO layer (with optimum Ga to Zn ratio) between the IGZO and the gate insulator (GI) resulted in two major effects: interface engineering and band alignment modulation. While maintaining a sufficiently large field effect mobility (31.9 cm2 V−1 s−1), considerable improvements in device reliability were observed concerning positive-bias thermal stress (PBTS) and negative-bias illumination stress (NBIS) compared to TFTs incorporating IGZO single layers. This suggests that proper composition control through PEALD in the bilayer oxide semiconductor TFT may help achieve an appropriate balance between mobility and reliability.

Machine Learning Driven Channel Thickness Optimization in Dual-Layer Oxide Thin-Film Transistors for Advanced Electrical Performance.

Machine learning (ML) provides temporal advantage and performance improvement in practical electronic device design by adaptive learning. Herein, Bayesian optimization (BO) is successfully applied to the design of optimal dual-layer oxide semiconductor thin film transistors (OS TFTs). This approach effectively manages the complex correlation and interdependency between two oxide semiconductor layers, resulting in the efficient design of experiment (DoE) and reducing the trial-and-error. Considering field effect mobility (𝜇) and threshold voltage (Vth ) simultaneously, the dual-layer structure designed by the BO model allows to produce OS TFTs with remarkable electrical performance while significantly saving an amount of experimental trial (only 15 data sets are required). The optimized dual-layer OS TFTs achieve the enhanced field effect mobility of 36.1cm2 V-1 s-1 and show good stability under bias stress with negligible difference in its threshold voltage compared to conventional IGZO TFTs. Moreover, the BO algorithm is successfully customized to the individual preferences by applying the weight factors assigned to both field effect mobility (𝜇) and threshold voltage (Vth ).

Enhancement of electrical performance in indium-zinc oxide thin-film transistors with HfO2/Al2O3 gate insulator deposited via low-temperature ALD

Several studies have been conducted on amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) with the aim of applying them to the next-generation low-power displays. To improve the electrical performance of conventional AOS TFTs, which are known for their poor switching characteristics, we fabricated indium-zin oxide (IZO) TFTs with HfO2/Al2O3 gate insulator deposited via low-temperature atomic layer deposition (ALD). We optimized the electrical performance of the fabricated TFTs by varying the thickness of the IZO channel and Al2O3 insulator, respectively. Compared to the samples with a thermally grown 150 nm thick SiO2 gate insulator, the samples with a 10 nm thick IZO channel and a 10/70 nm thick HfO2/Al2O3 gate insulator exhibited the subthreshold swing of 0.24 V/dec, saturation carrier mobility of 7.49 cm2/V∙s and on–off current ratio of 1.09 × 107, which were improved by more than 47 %, 64 % and 5 times, respectively. Also, the threshold voltage shift in positive and negative bias stress conditions were improved to + 0.90 and – 1.75 V, respectively.

Lifetime estimation of thin-film transistors in organic emitting diode display panels with compensation

Oxide semiconductor thin-film transistors (TFTs) are used in the pixel array and gate driver circuits of organic light emitting diode (OLED) display panels. Long-term reliability characteristics of the TFTs are a barometer of the lifetime of OLED display panels. The long-term reliability of the driver TFTs is evaluated in a short time under high voltages and high temperature for an accelerated degradation test. If reliability parameters from the power law or stretched-exponential functions are the same for individual devices and devices in an operating panel, the lifetime of the panel can be accurately estimated. However, since compensation circuits are designed into operating panels, an environmental discrepancy exists between the accelerated test of single devices and the operation of devices in the panel. Herein, we propose a novel compensation stretched-exponential function (CSEF) model which captures the effect of the threshold voltage compensation circuit in the panel. The CSEF model not only bridges the discrepancy between individual devices and panel devices, but also provides a method to accurately and efficiently estimate the long-term lifetime of all display panels that utilize compensation circuits.

Rapid and simultaneous multiple detection of a tripledemic using a dual-gate oxide semiconductor thin-film transistor-based immunosensor

The simultaneous infection with a tripledemic—simultaneous infection with influenza A pH1N1 virus (Flu), severe acute respiratory syndrome coronavirus 2 (SARS-CoV-2), and respiratory syncytial virus (RSV)—necessitates the development of accurate and fast multiplex diagnostic tests. The coronavirus disease 2019 (COVID-19) pandemic has emphasized the importance of virus detection. Field-effect transistor (FET)-based immuno-biosensors have a short detection time and do not require labeling or polymerase chain reaction. This study demonstrates the rapid, sensitive detection of influenza A pH1N1, SARS-CoV-2, and RSV using a multiplex immunosensor based on a dual-gate oxide semiconductor thin-film transistor (TFT), a type of FET. The dual-gate oxide TFT was modified by adjusting both top and bottom gate insulators to improve capacitive coupling to approximately 120-fold amplification, exhibiting a high pH sensitivity of about 10 V/pH. The dual-gate oxide TFT-based immunosensor detected the target proteins (hemagglutinin (HA) protein of Flu, spike 1 (S1) protein of SARS-CoV-2, and fusion protein of RSV) of each virus, with a limit of detection of approximately 1 fg/mL. Cultured viruses in phosphate-buffered saline or artificial saliva and clinical nasopharynx samples were detected in 1-μL sample volumes within 60 s. This promising diagnosis could be potentially as point-of-care tests to facilitate a prompt response to future pandemics with high sensitivity and multiplexed detection without pretreatment.

Fluorination-mitigated high-current degradation of amorphous InGaZnO thin-film transistors

As growing applications demand higher driving currents of oxide semiconductor thin-film transistors (TFTs), severe instabilities and even hard breakdown under high-current stress (HCS) become critical challenges. In this work, the triggering voltage of HCS-induced self-heating (SH) degradation is defined in the output characteristics of amorphous indium-gallium-zinc oxide (a-IGZO) TFTs, and used to quantitatively evaluate the thermal generation process of channel donor defects. The fluorinated a-IGZO (a-IGZO:F) was adopted to effectively retard the triggering of the self-heating (SH) effect, and was supposed to originate from the less population of initial deep-state defects and a slower rate of thermal defect transition in a-IGZO:F. The proposed scheme noticeably enhances the high-current applications of oxide TFTs.

Low-Voltage Operated High DC Gain Amplification Stage Based on Large-Area Manufacturable Amorphous Oxide Semiconductor Thin-Film Transistor

The industry-standard amorphous metal–oxide–semiconductor (AOS) thin-film transistor (TFT) technology is demonstrated for making low-voltage high intrinsic gain devices. It is revealed by the technology computer-aided design (TCAD) simulation that, without need of making Schottky barrier contacts, large output resistance and high intrinsic gain can be achieved in a subthreshold regime for AOS TFTs. It is further proved by the measurement results with the fabricated AOS TFT from a Gen-4.5 manufacturing line. A simple single-stage zero- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{V}_{\text{GS}}$</tex-math> </inline-formula> load amplifier is implemented as a proof of concept, achieving a voltage gain larger than 50 for weak signal detection at a supply voltage of 5 V.

Theoretical Modeling of a Temperature-Dependent Threshold-Voltage Shift in Self-Aligned Coplanar IZTO Thin-Film Transistors

Here, we investigate the effect of increasing temperature on threshold voltage (VTH) stability in self-aligned coplanar amorphous indium-zinc-tin oxide (a-IZTO) thin-film transistors (TFTs). An analytical model of the temperature dependency of VTH stability reveals the importance of device geometry and subgap density-of-state (DOS) reductions in highly stable a-IZTO TFTs. The validity of the analytical model is confirmed using experiments and technology computer-aided design simulations to predict quantitative relationships under various shifts in temperatures, subgap DOS, and VTH. The role of hydrogen impurity in performance and VTH stability is also examined. The incorporation of hydrogen in a-IZTO channels improves TFT performance and thermal stability (ΔVTH/ΔT = 3.18 mV/K) due to hydrogen’s role as a passivation center. However, excessive incorporation of hydrogen increases subgap DOS distribution, causing a slight deterioration in thermal stability (ΔVTH/ΔT = 3.31 mV/K). This suggests that hydrogen can be converted from a shallow donor to an acceptor-like deep trap state. Our findings inform future designs of stable oxide semiconductor TFTs in terms of thermal stability in emerging organic light-emitting diode, augmented and virtual reality, memory, logic, and monolithic three-dimensional applications.

Influence of indium doping on electrical performance of gallium oxide thin-film transistors

In the field of oxide semiconductor thin-film transistors (TFTs), the occurrence of charge trapping in the gate dielectric and interfaces presents significant challenges to their operational stability and reliability. In this study, we present high-performing amorphous Ga2O3 TFTs created using atomic layer deposition with varying indium doping concentrations. The channel length (Lch) and channel width (Wch) are 50 and 200 μm, respectively. As the Indium concentration increases from 0% to 60%, the charge trap density (Nit) decreases, resulting in a smaller hysteresis window. The TFTs with a doping concentration of 20% are particularly noteworthy, exhibiting high field-effect mobility (22.6 cm2 V−1 s−1), lower subthreshold swing (160 mV/dec) than amorphous Ga2O3 channel devices, a high on-off current ratio (109), an appropriate threshold voltage (−1 V), and a substantial output current (26 mA/mm at VGS = 16 V).

Simultaneous Extraction of Mobility Enhancement Factor and Threshold Voltage With Parasitic Resistances in Amorphous Oxide Semiconductor Thin-Film Transistors

This study presents a technique for simultaneous and consistent extraction of the mobility enhancement factor ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\gamma$</tex-math> </inline-formula> ) and the threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{V}_{\textit{T}}$</tex-math> </inline-formula> ) with parasitic source and drain resistances ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{R}_{\textit{S}}$</tex-math> </inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{R}_{\textit{D}}$</tex-math> </inline-formula> ) in amorphous oxide semiconductor (AOS) thin film transistors (TFTs). This technique allows for the extraction of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{R}_{\textit{S}}$</tex-math> </inline-formula> from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{R}_{\textit{D}}$</tex-math> </inline-formula> as well as the accurate extraction of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{V}_{\textit{T}}$</tex-math> </inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\gamma $</tex-math> </inline-formula> with only <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{I}$</tex-math> </inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{V}$</tex-math> </inline-formula> characteristics of the saturation operation in a single AOS TFT. The proposed technique was applied to amorphous indium–gallium–zinc-oxide (a-IGZO) TFTs with various structures. For intentional asymmetry, we confirmed the consistency with an external resistor ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{R}_{\text{ext}} = \text{10}$</tex-math> </inline-formula> , 20, 30 k <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega$</tex-math> </inline-formula> ). Extracted parameters ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{R}_{\textit{S}}$</tex-math> </inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{R}_{\textit{D}}$</tex-math> </inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{V}_{\textit{T}}$</tex-math> </inline-formula> , and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\gamma$</tex-math> </inline-formula> ) by the proposed method were compared with parameters extracted by other methods for verification. Furthermore, the drain current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{I}_{\textit{D}}$</tex-math> </inline-formula> ) was well reproduced using the extracted parameters regardless of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{R}_{\text{ext}}$</tex-math> </inline-formula> .

Ultra-thin gate insulator of atomic-layer-deposited AlO x and HfO x for amorphous InGaZnO thin-film transistors

To strengthen the downscaling potential of top-gate amorphous oxide semiconductor (AOS) thin-film transistors (TFTs), the ultra-thin gate insulator (GI) was comparatively implemented using the atomic-layer-deposited (ALD) AlO x and HfO x . Both kinds of high-k GIs exhibit good insulating properties even with the physical thickness thinning to 4 nm. Compared to the amorphous indium-gallium-zinc oxide (a-IGZO) TFTs with 4 nm AlO x GI, the 4 nm HfO x enables a larger GI capacitance, while the HfO x -gated TFT suffers higher gate leakage current and poorer subthreshold slope, respectively originating from the inherently small band offset and the highly defective interface between a-IGZO and HfO x . Such imperfect a-IGZO/HfO x interface further causes noticeable positive bias stress instability. Both ALD AlO x and HfO x were found to react with the underneath a-IGZO channel to generate the interface defects, such as metal interstitials and oxygen vacancies, while the ALD process of HfO x gives rise to a more severe reduction of a-IGZO. Moreover, when such a defective interface is covered by the top gate, it cannot be readily restored using the conventional oxidizing post-treatments and thus desires the reduction-resistant pre-treatments of AOSs.

Ultra-thin top-gate insulator of atomic-layer-deposited HfOx for amorphous InGaZnO thin-film transistors

In recent years, high-k gate dielectrics have attracted increasing attention in amorphous oxide semiconductor (AOS) thin-film transistors (TFTs), due to the urge for stronger gate controllability in advanced applications of high integration density. In this work, the ultra-thin top-gate insulator of atomic-layer-deposited (ALD) HfOx was developed for the amorphous indium-gallium-zinc oxide (a-IGZO) TFTs. Despite the good electrical characteristics of the 4-nm HfOx-gated a-IGZO transistor, its reliability is considerably poor and ascribed to the abundant interface defects, for example, oxygen vacancies. The interface reaction between HfOx and a-IGZO during the ALD process is clarified to be responsible for such defect generation. To prevent the oxygen-related reaction, the a-IGZO channel is pre-treated using the strong oxidizing plasma, contributing to significantly enhanced electrical stabilities. However, the further thinner HfOx would readily increase the gate leakage current, since the electron can easily tunnel through the ultra-thin HfOx due to the low conduction band offset between HfOx and AOS. The 4-nm ALD HfOx together with the pre-oxidization contributes to the optimal performance and stability of top-gate a-IGZO TFT.

Inserting Interfacial Layer for Atomic-Scaled Hydrogen Control to Enhance Electrical Properties of InZnO TFTs

As the application of oxide semiconductor thin-film transistors (oxide TFTs) expands, higher electrical properties are required. Hydrogen (H) is a crucial element related to both the mobility and stability of oxide TFTs. Appropriate H incorporation induces enhanced characteristics; however, excessive H degrades TFTs. In this letter, we suggest inserting an interfacial layer (IL) deposited via plasma-enhanced atomic layer deposition of several cycles to control H at the atomic-scale. As the number of IL deposition cycles increase from 0 to 10 cy, both mobility and stability improve. Furthermore, TFT with IL of 15 cy lost its on/off characteristic. Considering the analysis results, it was confirmed that the control of H concentration through IL can effectively improve the electrical characteristics of oxide TFTs. The oxide TFT with IL of 10 cy and optimized incorporation of H exhibits a high mobility of 50.12 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V∙s with great stability.

Addressing the Conflict between Mobility and Stability in Oxide Thin‐film Transistors

Amorphous oxide semiconductor thin-film transistors (AOS TFTs) are ever-increasingly utilized in displays. However, to bring high mobility and excellent stability together is a daunting challenge. Here, the carrier transport/relaxation bilayer stacked AOS TFTs are investigated to solve the mobility-stability conflict. The charge transport layer (CTL) is made of amorphous In-rich InSnZnO, which favors big average effective coordination number for all cations and more edge-shared structures for better charge transport. Praseodymium-doped InSnZnO is used as the charge relaxation layer (CRL), which substantially shortens the photoelectron lifetime as revealed by femtosecond transient absorption spectroscopy. The CTL and CRL with the thickness suitable for industrial production respectively afford minute potential barrier fluctuation for charge transport and fast relaxation for photo-generated carriers, resulting in transistors with an ultrahigh mobility (75.5 cm2 V-1 s-1 ) and small negative-bias-illumination-stress/positive-bias-temperature-stress voltage shifts (-1.64/0.76V). The design concept provides a promising route to address the mobility-stability conflict for high-end displays.

Impact of the Source/Drain Electrode Process on the Mobility-Threshold Trade-Off for InSnZnO Thin-Film Transistors

In this work, the source/drain (S/D) electrode process is considered to have a great impact on the mobility (μFE)–threshold (Vth) trade-off for high-mobility amorphous oxide semiconductor (AOS) thin-film transistors. High-mobility AOS materials have worse oxygen-fixation ability compared to InGaZnO. In this work, we show that this is the case for the Mo S/D electrode process on InSnZnO channels and has a great impact on the mobility-threshold trade-off. Oxygen vacancy gradients are observed in the depth profile X-ray photoelectron spectroscopy analysis on InSnZnO after Mo S/D deposition and show a bigger change in oxygen vacancies (VO) between the surface and inner layers and thicker compared to InGaZnO. This leads to an obvious negative shift in Vth or even no switching characteristic. Postprocessing such as oxygen-plasma treatment can make Vth positive but degrade the μFE. In situ replenishing oxygen via adopting ITO S/D electrodes deposited in an oxygen-containing atmosphere facilitates the achievement of excellent overall electrical characteristics, with μFE up to 87.1 cm2/Vs, Vth ∼ −0.64 V, and Ion/Ioff ∼ 2.3 × 108.