Output Voltage Standing Wave Ratio Research Articles

Analysis and Design of a Wideband Low-Noise Amplifier with Bias and Parasitic Parameters Derived Wide Bandpass Matching Networks

This paper proposes a 110% relative bandwidth (RBW) low-noise amplifier (LNA) for broadband receivers with flat gain, low noise and high linearity. Bias and parasitic parameters derived wide bandpass (BPDWB) matching networks and a cascode with dual feedbacks are introduced for broadband performance. Matching network design procedures are demonstrated, and results show that the frequency response of the network fits the target impedance well from 1 GHz to 3.5 GHz. The proposed BPDWB network improves the design efficiency and enhances the prediction accuracy of impedance matching. The proposed LNA in 0.25 μm GaAs pseudomorphic high electron mobility transistor (GaAs pHEMT) technology realizes a minimum NF of 0.45 dB at 1.6 GHz where the NF is less than 0.55 dB within the operating frequency band. A flat gain of 22.5–25.2 dB is achieved with the input voltage standing wave ratio (VSWR) below 1.22 and output VSWR less than 2.5. In addition, the proposed LNA has good linearity where the output third-order intercept point (OIP3) is better than +31.5 dBm, and the output 1 dB compression point (OP1dB) is better than +19 dBm over the wide frequency range.

Four‐way hybrid SIW/microstrip‐line power divider with improved output isolation

This Letter presents a four-way hybrid substrate integrated waveguide/microstrip-line power divider circuit based on the double microstrip-slot coupling. By slotting between T branch and loading isolation resistance, the isolation and output voltage standing wave ratio between non-adjacent ports is improved. By putting four output ports on the same side, the practicability of the circuit is improved. The test results show that the input return loss is >17.5 dB and insertion loss is <2 dB in 9–10.5 GHz.

A Novel Load Mismatch Detection and Correction Technique for 3G/4G Load Insensitive Power Amplifier Application

This paper proposes a novel load mismatch detection and correction technique to develop a load insensitive power amplifier (PA). The presented algorithm for the technique can simply be implemented by handling load impedance as a region rather than a point. Based on the detection results, a tunable output matching network (TOMN) corrects a mismatched load and transforms it into a desired region, thereby dramatically enhancing PA performances under load mismatched condition with a minimal compromising at a matched load. The detectors and TOMN were simply implemented using a 0.18-μm silicon-on-insulator field-effect transistor, which were integrated with a 2-μm InGaP/GaAs HBT PA monolithic microwave integrated circuit into a single module. A PA module was implemented using more advanced impedance detectors having eight-phase regions, which was measured with WCDMA R'99 and 10-MHz 16QAM long-term evolution signals centered at 1.95 GHz for verification of the proposed idea. When compared to a conventional PA, excellent adjacent channel leakage ratio improvements of 12.7 and 8.3 dB, respectively, were achieved under output voltage standing-wave ratio (VSWR) of 2.5:1 for both applications. Moreover, the idea was extended for efficiency enhancement in a linearity spec-compliant impedance region, and the PA showed power-added efficiency improvements of 1.6% and 0.5%, respectively, under output VSWR of 2.5:1 for both applications.

Temperature dependence on RF avalanche breakdown of RF mosfets in the impact ionization region

ABSTRACTIn this article, temperature dependence on radio‐frequency (RF) avalanche effects of metal–oxide–semiconductor field‐effect transistors (MOSFETs) in the impact ionization region is investigated using RF measurements for the first time. Equivalent circuit parameters of MOSFETs including the inductive breakdown network are extracted from low to high temperatures to characterize device performance and its temperature dependency in the breakdown regime. At elevated temperatures, inductive behavior resulting from a RF avalanche mechanism becomes evident due to the pronounced inductive network with increasing temperature. When the RF avalanche mechanism is not considered, a deviation of the extracted channel resistance increases with raising temperature. The effect of inductive breakdown on output voltage standing wave ratio performance when designing an output matching network for the MOSFETs is also analyzed at different temperatures. The presented analysis of temperature dependence on device performance can be beneficial to RF power amplifier design in the breakdown region for high‐altitude applications at different temperatures. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:817–820, 2015

Characterisation of measurement uncertainties due to preamplifier gain variation

The measurement uncertainties associated with preamplifier gain variation due to temperature change are investigated. It is shown that when temperature decreases from the room temperature (25°C) to 0°C, the uncertainty of the preamplifier gain variation is found to be as large as 1.277 dB. Further investigation of mismatch uncertainty between the preamplifier and the system due to temperature change has been carried out. It is expected that mismatch uncertainty will be greatly affected if the preamplifier input and output voltage standing wave ratio varies at different operating temperatures.

Single Stage RF Amplifier with High Gain for 2.4GHz Receiver Front-Ends

The paper deals with the numerical and experimental development of single stage radio frequency (RF) amplifier with high gain for 2.4GHz receiver front-ends. The work is motivated by the increasing demand of high-gain receiver amplifier in low-cost especially for wireless local area network (WLAN) application. Prior hardware realization and experimental characterization, the proposed amplifier which uses a single RF transistor of BFP420 type is numerically designed using ADS® software to satisfy the required specification. To obtain the impedance matching at ports of amplifier, microstrip lines are employed at the input and output ports. The prototype of amplifier is realized by use of a dielectric substrate of glass-reinforced epoxy lamination (FR4) board which has thickness of 0.762mm and relative permittivity of 4.3. The prototype is then experimentally characterized and demonstrates the gain of 13.35dB at frequency of 2.4GHz with the noise figure of 3.33dB, the input and output voltage standing wave ratio (VSWR) of 2.08 and 2.55, respectively.

Design and Simulation of S-Band Low Noise Amplifier Based on ATF-54143

This design used a low noise enhanced high electron mobility transistor ATF54143 and Agilent's ADS simulation software to achieve the good performance of operating frequency at 2.45GHz, noise figure (NF) is less than 0.8dB, band gain (S21) is greater than 15dB, input voltage standing-wave ratio (VSWR1) is less than 1.4dB, output voltage standing-wave ratio (VSWR2) is less than 1.6dB.

Wideband 5-bit MMIC Digital Attenuator With High Precision

This paper mainly introduces the Wideband 5-bit MMIC digital attenuator with high precision. Firstly, the theories of basic GaAs digital attenuator MMICâ??s configurations are searched. Secondly, every possible configuration is contrasted, subsequently, appropriate topology is selected for each stage. This attenuator has been realized by 0.5µm GaAs pHEMT process. Simulation results of the digital attenuator has 0.25dB resolution and 7.75dB dynamic attenuation range, Input Voltage Standing Wave Ratio(VSWRIN) was less than 1.55 and Output Voltage Standing Wave Ratio(VSWROUT) was less than 1.6 for all attenuation states, high attenuation accuracy is less than ±0.26dB; insertion loss is less than 1.3dB; The layout of the digital attenuator with a chip size is 0.93 mmA?1.45 mm

Research on cryogenic behaviors of low noise amplifier with build-in PIN diode limiter

In this article we elucidate the design and fabrication of a P-band cryogenic low noise amplifier (CLNA) with built-in limiter circuit, and further studied the characteristics of PIN diode limiter at different temperature. Measurements at 75 K shows the P-band CLNA with build-in limiter has a good performance with noise figure lower than 0.5 dB, the input and output voltage standing wave ratio (VSWR) less than 1.5 and input 1 dB power compression point −4 dBm within the band width 300 MHz. The variation of the gain within ±0.1 dB under the impact of 20 dBm input power level signals. In addition, the maximum allowed input power of the CLNA has increased from 13 dBm to 22 dBm.

Self Oscillating Mixer with Dielectric Resonator for Low Noise Block Application

In this paper, the development of a self oscillating mixer (SOM) as part of a low noise block (LNB) for a satellite television receiver is investigated numerically and experimentally. In contrast to other mixers, the developed SOM requires no separate local oscillator as it generates own local oscillator signal. The SOM is developed using a monolithic microwave integrated circuit (MMIC) comprised of two bipolar transistors coupled as a Darlington pair and a dielectric resonator to establish a local oscillator signal. The SOM is designed to oscillate at 3.62GHz driven from 50 W signal generator. The prototype of SOM is fabricated on a dielectric substrate of glass-reinforced hydrocarbon/ceramic lamination (RO4350B) board which has a thickness of 0.762mm and relative permittivity of 3.66. The prototype is then characterized experimentally and exhibits a conversion gain of 8dB with the input and output voltage standing wave ratio (VSWR) less than 2 across the 2520MHz to 2670MHz operating frequency band .

위성 DAB 수신을 위한 저잡음 증폭기의 설계 및 구현에 관한 연구

본 논문에서는 1,452∼l,492 MHz L-Band 대역의 위성 DAB 수신기를 위한 저잡음증폭기를 입ㆍ출력 반사계수와 전압정재파비를 개선하기 위하여 평형증폭기 형태로 설계 및 제작하였다. 저 잡음증폭기는 GaAs FET소자인 ATF-10136을 사용한 저 잡음증폭단과 MMIC 소자인 VNA-25을 사용한 이득증폭단을 하이브리드 방식으로 구성하였으며, 최적의 바이어스를 인가하기 위하여 능동 바이어스 회로를 사용하였다. 적용된 능동 바이어스 회로는 소자의 펀치오프전압(<TEX>$V_P$</TEX>)과 포화드래인 전류(<TEX>$I_{DSS}$</TEX>)의 변화에 따라 주어진 바이어스 조건을 만족시키기 위해 소스 저항과 드래인 저항의 조절이 필요없다. 즉, 능동 바이어스 회로는 요구된 드래인 전류와 전압을 공급하기 위해 게이트-소스 전압(<TEX>$V_{gs}$</TEX>)을 자동적으로 조절한다. 저잡음증폭기는 바이어스 회로와 RF 회로를 FR-4기판 위에 제작하였고, 알류미늄 기구물에 장착하였다. 제작된 저잡음증폭기는 이득 32 dB, 이득평탄도 0.2 dB, 0,95 dB 이하의 잡음지수, 입ㆍ출력 전압정재파비는 각각 1.28, 1.43이고, <TEX>$P_{1dB}$</TEX> 는 13 dBm으로 측정되었다. In this paper, a LNA(Low Noise Amplifier) has been developed, which is operating at L-band i.e., 1452∼1492 MHz for satellite DAB(Digital Audio Brcadcasting) receiver. The LNA is designed to improve input and output reflection coefficient and VSWR(Voltage Standing Wave Ratio) by balanced amplifier. The LNA consists of low noise amplification stage and gain amplification stage, which make a using of GaAs FET ATF-10136 and VNA-25 respectively, and is fabricated by hybrid method. To supply most suitable voltage and current, active bias circuit is designed Active biasing offers the advantage that variations in <TEX>$V_P$</TEX> and <TEX>$I_{DSS}$</TEX> will not necessitate a change in either the source or drain resistor value for a given bias condition. The active bias network automatically sets <TEX>$V_{gs}$</TEX> for the desired drain voltage and drain current. The LNA is fabricated on FR-4 substrate with RF circuit and bias circuit, and integrated in aluminum housing. As a reults, the characteristics of the LNA implemented more than 32 dB in gain. 0.2 dB in gain flatness. lower than 0.95 dB in noise figure, 1.28 and 1.43 each input and output VSWR, and -13 dBm in <TEX>$P_{1dB}$</TEX>.

An integrated CMOS distributed amplifier utilizing packaging inductance

An integrated CMOS distributed amplifier is presented. The required inductance needed for the distributed waveguide structure is realized by the parasitic packaging inductance of a plastic surface-mount package. A fully packaged three-stage distributed amplifier fabricated in a 0.8-/spl mu/m CMOS process is presented. The distributed amplifier has a unity gain cutoff frequency of 4.7 GHz, a gain of 5 dB, with a gain flatness of /spl plusmn/1.2 dB over the 300-kHz to 3-GHz band. At a frequency of 2 GHz the amplifier has an input referred third-order intercept point of +15 dBm and an input referred 1-dB compression point of +7 dBm. The amplifier consumes 18 mA from a 3.0-V supply. The distributed amplifier is matched to 50 /spl Omega/ at the input and output and has a maximum input voltage standing-wave ratio (VSWR) of 1.7:1, and a maximum output VSWR of 1.3:1 over the 300 kHz to 3 GHz band. The amplifier has a noise figure of 5.1 dB at 2 GHz.

Wide-band, low-noise, matched-impedance amplifiers in submicrometer MOS technology

Circuit design techniques for realizing wideband, low-noise, matched-impedance amplifiers in submicrometer MOS technology are discussed. A circuit configuration with two feedback loops has been fabricated in an experimental 1-/spl mu/m NMOS technology. The fabricated amplifier has an insertion gain of 16.35 dB, a -3-dB bandwidth of 758 MHz, a maximum input voltage standing-wave ratio (VSWR) of 2.45, a maximum output VSWR of 1.60, and an average noise figure of 6.7 dB (with reference to a 50-/spl mu/m source resistance) from 10 to 758 MHz.

Cryogenically Cooled Broad-Band Gaas Field-Effect Transistor Preamplifier

A cryogenically cooled 1-2 GHz low-noise broad-band prototype preamplifier utilizing GaAs field-effect transistors is described. The preamplifier has an average gain of 30 dB and 35 dB at ambient temperatures of 293°K and 18°K, respectively. The noise figure has a minimum value of 0.75dB at 300°K and 0.24dB at 18°K. The optimum preamplifier operating conditions for a minimum noise figure at temperatures of 293°K, 80°K and 18°K are given and are discussed. Also, the phase-shift characteristics, the input and output voltage standing-wave ratio as a function of frequency and intermodulation products content as a function of the input power level were measured.