Output Voltage Spike Research Articles

(Invited) Nanoscale Devices for Accelerating AI Algorithms

The energy consumption of training and deploying state-of-the-art artificial intelligence (AI) models has experienced exponential growth, driven by increasing model parameters and the necessary training data. Recent models demand over 1 billion PetaFLOPs of total computation for training, potentially taking weeks to complete. With current GPU performance at approximately 1-3 TOPS/W, GPU training energy consumption alone can exceed 100,000 kWh, equivalent to the monthly energy expenditure of 100 US households. Over the next decade, these models are expected to scale up further, driving total computing energy to constitute a significant portion of global consumption. In this talk, we describe both synaptic and neuronal devices that can accelerate AI algorithms with potentially multiple orders of magnitude improvement in power efficiency.First, we describe an oscillatory retinal neuron (ORN) that directly converts incident DC light into voltage spikes. Coupled arrays of this device result in an imager that carries out in-sensor processing while capturing an image. Uniquely, the conversion from input light to output voltage spikes occurs without external power. When coupled in arrays, the neighboring neurons interact with each other to influence the spiking frequency spectrum. This allows the arrays to carry out frequency multiplexed computation on an input image. It is shown that this approach can achieve>20,000 TOPS/W, multiple orders of magnitude greater than the current approaches. Theory and simulation is used to elucidate how coupled ORNs carry out computation on an input image. When coupled, each output frequency band encodes a unique computation on the input image. By tuning the coupling impedances and the frequency bands, user defined computations can be carried out on the input. We experimentally show that this can be carried out with a 3x3 array that demonstrates simultaneous edge detection, intensity filtering, image segmentation and other functions. This hardware is then used to demonstrate improvement in MNIST handwritten digit classification accuracy over a traditional imager connected to a fully connected network.Next, we describe spiking synaptic devices that can be directly fabricated in the back-end of line of CMOS devices. These devices consist of an InP transistor channel with an engineered gate stack. Using a uniform gate insulator, we can demonstrate behaviors of biological synapses, such as potentiation, depression, spike number dependent plasticity, and spike timing dependent plasticity. By introducing a heterostructured gate insulator, it is shown that short-term to long-term memory transitions can be designed into the device. Finally, by using a transparent gate, an in-sensor synaptic phototransistor is demonstrated and the performance of these devices at a system level is demonstrated.

DC operating points of Mott neuristor circuits

In 1960 Hewitt Crane conceptualized neuristors as electronic logic networks that could mimic action potential generation by biological neurons. In 2012 Mott memristors were presented as nano-scale electronic devices for physically constructing neuristor networks. Both the original Mott memristor model and the simplified model presented in 2020 are stiff nonlinear first-order ordinary differential equations (ODEs) that describe the voltage controlled threshold switching and current controlled negative differential resistance, attributed to a Mott insulator-to-metal phase transition. By design, a Mott neuristor contains two identical Mott memristors plus linear resistors and capacitors (no inductors), which enables alternating threshold switching by the memristors to generate periodic (AC) output voltage spikes in response to a DC current or voltage input. This paper presents a steady-state analysis of dynamic neuristor models, including four-, five-, and six-state variables (each of which is a system of first-order ODEs involving the states) based on the original phenomenological model of the Mott memristor. Specifically, it reveals the unique stable operating points that occur for applied currents or voltages below the amounts needed to induce resistive switching. These DC operating points represent the physically meaningful “OFF” states for the circuit when the neuristor does not output voltage spikes. Jacques Hadamard's mathematical criteria for a well-posed physical model (existence, uniqueness, continuity, stability) motivated the search for these DC operating points (OFF states), which are needed for efficiently initializing neuristor models before conducting dynamic neuristor simulations. The key result of our analysis is the neuristor steady-state eq. (29) which is useful for understanding neuristor OFF states as well as the role of negative-differential resistance (NDR) in the operation of the Mott memristor model and neuristor circuits. In addition to the steady-state analysis, three numerical examples of dynamic neuristor circuit operation are also given and MATLAB code for the dynamic four-state model is available for interested readers.

A novel control method for enhanced performance of single‐phase matrix converters

AbstractThe conventional topology of direct single‐to‐single‐phase matrix converter (SSMC) is widely adopted in industrial and power system‐related applications owing to its desired features. Current control methods in the literature either limit the voltage transfer ratio (VTR) or prohibit their utilization to drive inductive (RL) loads. In this study, we propose a novel control method that overcomes these limitations by enabling the SSMC to achieve relatively high VTRs while driving RL loads with negligible output voltage spikes and without current commutation problems. Further, the proposed control method improves the overall performance by reducing output voltage and source input current total harmonic distortion (THD) and offering soft‐switching at the commutation instances. The rigidity of the proposed control method over the counterpart methods in the literature is verified through simulation and experimental case studies over a wide range of synthesized output frequencies and modulation indexes. A 530‐W laboratory prototype is built for the experimental study. Results demonstrated the ability of the proposed method in enabling the SSMC to drive an RL load without current commutation issues and with mitigated output voltage spikes while achieving relatively high VTRs and suppressing the output voltage and source input current THD.

Low-Voltage LDO Regulator Based on Native MOS Transistor with Improved PSR and Fast Response

In this paper, a low-voltage low-dropout analog regulator (ALDO) based on a native n-channel MOS transistor is proposed. Application of the native transistor with the threshold voltage close to zero allows elimination of the charge pump in low-voltage regulators using the pass element in a common drain configuration. Such a native pass transistor configuration allows simplification of regulator design and improved performance, with supply voltages below 1 V, compared to commonly used regulators with p-channel MOS transistors. In the presented design of ALDO regulator in 180 nm CMOS X-FAB technology, an output voltage of 0.7 V was achieved with an output current of 10 mA and a supply voltage of 0.8 V. Simulation results show that despite the low supply voltage, output voltage spikes do not exceed 70 mV at the worst technology corner when output current transients from 100 µA to 10 mA. Under such conditions, stable operation and power supply rejection PSR = 35 dB were achieved with an output capacitance of 0–500 pF. The proposed regulator allows to push the limit of ALDO regulator applications to voltages below 1 V with only slight degradation of its performance.

A Fast-Transient Low-Dropout Regulator With Current-Efficient Super Transconductance Cell and Dynamic Reference Control

A fast-transient, current-efficient low-dropout regulator (LDO) with super transconductance cell (STC) is proposed in this paper. By adopting advanced current amplifier (CA) and dynamic biasing (DB) techniques for the error amplifier (EA), the feedback loop bandwidth can be significantly extended without increasing much quiescent power, which reduces output voltage spikes and response time greatly. Moreover, dynamic reference control (DRC) with robust loop stability is embedded in the LDO to adaptively adjust voltage reference during transient so as to further enhance the slew rate of EA, realizing significant enhancement for the transient performances. This circuit has been implemented in a 0.35μm CMOS process and occupies an active chip area of 456×278 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><b>2</b></sup> . Experimental results show that it is able to provide 100mA load current at 200mV dropout voltage, with current efficiency of 99.88%. The output voltage spike under maximum load current change in 20ns edge time is less than 11.2mV with a 0.054μs response time. The power-supply rejection (PSR) at 100kHz is -75.6dB.

Practical increases in power output from soil-based microbial fuel cells under dynamic temperature variations

Oscillating ambient temperatures cause spikes in output voltage of soil microbial fuel cells, independent of temperature direction. The resulting output is higher than could be achieved at any constant temperature.

Co nstant on Time Controller f or Voltage Regulator with and without Adaptive Voltage Positioning

Advancement in electronics prompted for incremental usage of power supplies in digital circuits. In devices such as Central Processing Unit (CPU), Graphic Processing Unit (GPU) a Voltage regulator (VR) is utilized for microprocessors powering application. During load transients, microprocessor input voltage losses stability. High speed devices need quick response from the converters under transient conditions. Therefore, futuristic electronic devices demand a VR with new control schemes to operate at low operating voltage with improved efficiency thereby improving light load efficiency. In this paper a comparative study about the performance of Constant on Time (COT) controller with and without Adaptive Voltage Positioning (AVP) technique is presented. . The aim of the paper is to present the idea of AVP with COT during transients. Since load transient demands large number of capacitors to maintain stable voltage but increases the cost and volume. Thus, to overcome the transient time frame problem, voltage spikes and to reduce the number of capacitors. The converters need to operate under a new control scheme i.e. COT controller with AVP. Simulation of the voltage regulator is carried out for both Non AVP and AVP compliant schematics in LTSpice software. The simulation results show Non-AVP topology with output voltage spikes for 445uF but the AVP compliant topology with 222uF shows smooth output voltage transition.

A 600-mA, Fast-Transient Low-Dropout Regulator With Pseudo-ESR Technique in 0.18-$\mu$ m CMOS Process

In this article, a dual loop-compensated, fast-transient, low-dropout regulator (LDO) is proposed for battery-powered applications. It is successfully implemented in a 0.18- $\mu \text{m}$ CMOS process with a total silicon area of $210\,\,\mu \text{m}\,\,\times 593\,\,\mu \text{m}$ . The proposed LDO is composed of two feedback loops. The fast feedback loop (FFL) employs direct output voltage spike detection through capacitive coupling, resulting in significantly improved, large signal transient response and loop bandwidth at the same time. Its voltage spike is 15 mV for a load step of 600 mA. The proposed LDO has a loop bandwidth of 2.3 MHz at a load current of 600 mA with a 30- $\mu \text{A}$ no-load bias current. A power transistor with pseudo-equivalent series resistance (ESR) technique is proposed for loop stability improvement. It enables the usage of the low-cost, multilayer ceramic capacitors in mobile applications. The constant biased voltage feedback loop (VFL) has a loop gain larger than 60 dB under all load conditions, which enables a good line and load regulation.

Fast Transient Capacitor-Less Low-Dropout Regulator Based on Output Voltage Spike Reduction Circuits for SOC Applications

A fast transient capacitor-less low-dropout regulator is presented in this study. The proposed LDO structure is based on Output Voltage Spike Reduction (OVSR) circuits and capacitance compensation circuits to enable a fast-transient response with ultra-low power dissipation and to make the LDO stable for a wide range of output load currents (0–50[Formula: see text]mA). The slew rate is improved with more slew current from the OVSR circuit and unity gain bandwidth is improved by a capacitor multiplayer circuit. The proposed LDO has been simulated with a standard 0.18[Formula: see text][Formula: see text]m CMOS process. The output voltage of the LDO was set to 1.2[Formula: see text]V for an input voltage of 1.4–2[Formula: see text]V. The Simulation results verify that the transient times are less than 2.8[Formula: see text][Formula: see text]s and the maximum undershoot and overshoot are 20[Formula: see text]mV while consuming only 26[Formula: see text][Formula: see text]A quiescent current. The proposed LDO is stable with an on-chip capacitor at the output node within the wide range of 1100[Formula: see text]PF.

A 0.45-to-1.2-V Fully Digital Low-Dropout Voltage Regulator With Fast-Transient Controller for Near/Subthreshold Circuits

A low quiescent current digital low-dropout (D-LDO) voltage regulator with fast-transient response time is proposed for self-powered wireless sensor applications operating at near/subthreshold supply voltage. The D-LDO regulator incorporates both hill-climbing and binary search algorithms (HCBS) in the control logic, thus leveraging on each other's strengths to minimize the output voltage's ripple and the quiescent current during the steady-state period as well as output voltage's spike and response time during the transition period. Additional features such as hysteresis mode control and freeze mode control are incorporated into the system to improve the performance of the D-LDO regulator. A dynamic comparator is proposed for the near/subthreshold supply voltage operation, which minimizes the voltage error and improves the maximum operating frequency. Fabricated in 130-nm CMOS technology, the D-LDO regulator regulates the output voltage ${V}_{{\rm OUT}}$ from 350 to 1150 mV, while the input supply voltage ${V}_{\text{IN}}$ ranges from 450 to 1200 mV. At a ${V}_{{\rm OUT}}$ of 450 mV, ${V}_{{\rm IN}}$ of 500 mV and an operating frequency of 10 MHz, the regulator delivers 1500- ${\mu }$ A load current with $I_{\text{QUIESCENT}}$ of 8.9 ${\mu }$ A and a transient response time of 1.6 ${\mu }$ s. The maximum current and power efficiencies reach 99.9% and 89.9%, respectively. The measured line regulation and load regulation are 1.6 and 0.6 mV/mA, respectively.

MPPT for PV systems based on a dormant PSO algorithm

Since the power–voltage characteristic curve of photovoltaic (PV) arrays has multiple peaks under partially shaded conditions, the conventional maximum power point tracking (MPPT) control methods will fail to work. However, the particle swarm optimization (PSO) algorithm is very suitable to solve the multi-extreme optimization problem. Then this paper proposes a dual-algorithm search method: first, a dormant particle swarm optimization (DPSO) algorithm is activated to search the area of global peak, and then the algorithm will be switched to conventional incremental conductance (INC) algorithm to track the maximum output power of photovoltaic arrays. During the iteration process of DPSO, if particles happen to search repeatedly or sway in a small region, they will be turned into dormant state so as to reduce convergence time and improve efficiency. Due to the elimination of searching repeatedly, the number of particles can be large to strengthen optimization capability. In addition, the optimal number of particles for DPSO is found by analysis and simulation. Furthermore, the searching sequence of particles is optimized to effectively reduce fluctuation of voltage and suppress output voltage spike. Finally, the excellent performance of the proposed model is verified by simulations and experiments.

Power‐area‐efficient transient‐improved capacitor‐free FVF‐LDO with digital detecting technique

A fast-transient capacitor-free low-dropout regulator (LDO) based on a flipped-voltage-follower (FVF) structure has been designed with the proposed digital detecting technique. By increasing the slewing at the gate of the power transistor through detecting the dynamic changes inside the circuit, load-transient recovery time can be decreased by 99.8%. The quiescent current of the proposed LDO is only 3.9 μA under normal operation. In addition, the circuit maintains a small chip area of 0.04 mm 2 under 0.18 μm CMOS technology since no large RC components are needed to couple the output voltage spikes.

A dynamic-biased dual-loop-feedback CMOS LDO regulator with fast transient response

This paper presents a low-dropout regulator (LDO) for portable applications with dual-loop feedback and a dynamic bias circuit. The dual-loop feedback structure is adopted to reduce the output voltage spike and the response time of the LDO. The dynamic bias circuit enhances the slew rate at the gate of the power transistor. In addition, an adaptive miller compensation technique is employed, from which a single pole system is realized and over a 59° phase margin is achieved under the full range of the load current. The proposed LDO has been implemented in a 0.6-μm CMOS process. From the experimental results, the regulator can operate with a minimum dropout voltage of 200 mV at a maximum 300 mA load and IQ of 113 μA. The line regulation and load regulation are improved to 0.1 mV/V and 3.4 μV/mA due to the sufficient loop gain provided by the dual feedback loops. Under a full range load current step, the voltage spikes and the recovery time of the proposed LDO is reduced to 97 mV and 0.142 μs respectively.

Internally compensated LDO regulator based on the cascoded FVF

In this paper, an internally compensated low dropout (LDO) voltage regulator based on the Flipped Voltage Follower (FVF) is proposed. By means of capacitive coupling and dynamic biasing, the transient response to both load and line variations is enhanced. The proposed circuit has been designed and fabricated in a standard 0.5µm CMOS technology. Experimental results show that the proposed circuit features a line and a load regulation of 132.04µV/V and 153.53µV/mA, respectively. Moreover, the output voltage spikes are kept under 150mV for a 2V-to-5V supply variation and for 1mA-to-100mA load variation, both in 1µs.

Fast Transient Low-Dropout Voltage Regulator With Hybrid Dynamic Biasing Technique for SoC Application

This brief presents a low-dropout (LDO) voltage regulator without output capacitors that achieves fast transient responses by hybrid dynamic biasing. The hybrid dynamic biasing in the proposed transient improvement circuit is activated through capacitive coupling. The proposed circuit senses the LDO regulator output change so as to increase the bias current instantly. The proposed circuit was applied to an LDO regulator without output capacitors implemented in standard 0.35- μm CMOS technology. The device consumes only 25 μA of quiescent current with a dropout voltage of 180 mV. The proposed circuit reduces the output voltage spike of the LDO regulator to 80 mV when the output current is changed from 0 to 100 mA. The output voltage spike is reduced to 20 mV when the supply voltage varies between 1.3 and 2.3 V with a load current of 100 mA.

An Ultrafast Adaptively Biased Capacitorless LDO With Dynamic Charging Control

This brief presents a current-efficient fully integrated low-dropout regulator (LDO) for system-on-a-chip applications. A common-gate error amplifier with high bandwidth and slew rate is proposed to reduce the output voltage spike and the response time of the LDO greatly. In addition, the loop employs a direct dynamic charging technique to enhance load-transient responses by directly detecting voltage variations through a capacitive coupling high-pass filter. The circuit has been implemented in a 0.35-μm standard complementary metal-oxide-semiconductor process and occupies an active chip area of 0.064 mm2. Experimental results show that it can deliver a load current of 100 mA at a dropout voltage of 150 mV. It only consumes a quiescent current of 7 μA at light loads and can recover within 0.15 μs, even under the maximum load current change. Consequently, a faster and more accurate capacitorless LDO can be achieved.

Novel digitally controlled low-drop-out voltage regulator

Low-drop-out (LDO) voltage regulators have been widely used in the power supply of the integrated circuits (ICs). With the evolution of the IC manufacturing process and its applications, the design of the analog controlled LDO has encountered more challenges in recent years. This paper starts with the discussion of low supply voltage and low output capacitor problems that have been found in the analog controlled LDO. To solve the mentioned problems, a novel design concept of the digitally controlled LDO is then presented. To verify the feasibility of the real implementation, the designed circuit is validated using the NanoSim/VCS software in a 0.18µm manufacturing process before the circuit is taped-out. With the test condition of 1V supply voltage, the stability of the proposed LDO is guaranteed when a small output capacitor (1µF) with very low equivalent series resistance(1mΩ) is used. Load test result shows that the output voltage spike is only 40mV with 3µs recovery time when the load current steps-up from 1 to 51mA.

Transient-Voltage-Clamp Circuit Design Based on Constant Load Line Impedance for Voltage Regulator Module

A transient-voltage-clamp (TVC) circuit acts as a replacement of bulk capacitors, which is required for voltage regulator (VR) module (VRM) to clamp output voltage spikes. With the TVC circuit, VRM size is greatly reduced with similar transient performance. This paper presents a new TVC circuit. This TVC circuit is designed based on the constant load line impedance which is recently given by Intel's VRM11.0. The TVC circuit works in parallel with VR decoupling capacitors to achieve faster voltage regulation. The impedances of the VR, output capacitors, and the proposed TVC circuit are analyzed. The TVC circuit design procedure is described, and the transient performance and power consumption are discussed. The theoretical analysis is verified by simulation results. Moreover, the proposed TVC circuit is fabricated with a 0.6-μm CMOS process, and experimental results verify the simulation results and theoretical analysis.

Ionic polymer metallic composite as wearable impact sensor for sport science

Ionic polymer metallic composite (IPMC) is a type of ionic electroactive polymer that has electromechanical property that can be used as actuators or sensors. IPMC sensors offer several advantages over conventional sensors; such as flexibility, conformability and durability are useful for impact sensing. The aim of the paper is to demonstrate the ability of IPMC as an impact sensor to be used in sport science. The ability to measure impact force or energy is important in sport science as this information can be used to improve athletes' performances. In this research, experiments were conducted for different impact energies and a mathematical model based on the impact sensor's output voltage spike's slope was developed. Testing using this model demonstrated that the accuracy of the measured impact energy is mostly within ±10% although an error of up to 25% was observed at low impact energies.

Design and Implementation of an FPGA-Based CCFL Driving System With Digital Dimming Capability

The proliferation of liquid-crystal display (LCD) monitors and notebook computers places an ever-increasing demand on display technology. The LCD with cold cathode fluorescent lamp (CCFL) best satisfies display performance, size, and efficiency. To operate the CCFL, a driving circuit is needed to light the lamp with a relatively high voltage and then stabilize the arc current. For minimizing the component count and size, a high-frequency zero-voltage switching (ZVS) resonant converter is preferred. In this paper, a field-programmable-gate-array-based ZVS resonant converter for driving CCFL with digital dimming capability is presented. The proposed digital controller utilizes the pulse density modulation technique to adjust the output power. A 3-W prototyping system is built and tested; experimental results show that the proposed system can reduce the voltage spike by more than 15%, compared to the low-frequency dimming methods. The overall system power efficiency is approximately 85%. The advantages of the proposed system include high efficiency, low output voltage and current spike, wide dimming range, flexibility, and compactness.